2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1990 The Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
9 * This code is derived from software contributed to Berkeley by
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
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16 * notice, this list of conditions and the following disclaimer.
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22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)vmparam.h 5.9 (Berkeley) 5/12/91
37 * from: FreeBSD: src/sys/i386/include/vmparam.h,v 1.33 2000/03/30
41 #ifndef _MACHINE_VMPARAM_H_
42 #define _MACHINE_VMPARAM_H_
45 * Virtual memory related constants, all in bytes
48 #define MAXTSIZ (1*1024*1024*1024) /* max text size */
51 #define DFLDSIZ (128*1024*1024) /* initial data size limit */
54 #define MAXDSIZ (1*1024*1024*1024) /* max data size */
57 #define DFLSSIZ (128*1024*1024) /* initial stack size limit */
60 #define MAXSSIZ (1*1024*1024*1024) /* max stack size */
63 #define SGROWSIZ (128*1024) /* amount to grow stack */
67 * The physical address space is sparsely populated.
69 #define VM_PHYSSEG_SPARSE
72 * The number of PHYSSEG entries must be one greater than the number
73 * of phys_avail entries because the phys_avail entry that spans the
74 * largest physical address that is accessible by ISA DMA is split
75 * into two PHYSSEG entries.
77 #define VM_PHYSSEG_MAX 64
80 * Create two free page pools: VM_FREEPOOL_DEFAULT is the default pool
81 * from which physical pages are allocated and VM_FREEPOOL_DIRECT is
82 * the pool from which physical pages for small UMA objects are
85 #define VM_NFREEPOOL 2
86 #define VM_FREEPOOL_DEFAULT 0
87 #define VM_FREEPOOL_DIRECT 1
90 * Create two free page lists: VM_FREELIST_DEFAULT is for physical
91 * pages that are above the largest physical address that is
92 * accessible by ISA DMA and VM_FREELIST_ISADMA is for physical pages
93 * that are below that address.
95 #define VM_NFREELIST 2
96 #define VM_FREELIST_DEFAULT 0
97 #define VM_FREELIST_ISADMA 1
100 * An allocation size of 16MB is supported in order to optimize the
101 * use of the direct map by UMA. Specifically, a cache line contains
102 * at most four TTEs, collectively mapping 16MB of physical memory.
103 * By reducing the number of distinct 16MB "pages" that are used by UMA,
104 * the physical memory allocator reduces the likelihood of both 4MB
105 * page TLB misses and cache misses caused by 4MB page TLB misses.
107 #define VM_NFREEORDER 12
110 * Enable superpage reservations: 1 level.
112 #ifndef VM_NRESERVLEVEL
113 #define VM_NRESERVLEVEL 1
117 * Level 0 reservations consist of 512 pages.
119 #ifndef VM_LEVEL_0_ORDER
120 #define VM_LEVEL_0_ORDER 9
124 * Address space layout.
126 * UltraSPARC I and II implement a 44 bit virtual address space. The address
127 * space is split into 2 regions at each end of the 64 bit address space, with
128 * an out of range "hole" in the middle. UltraSPARC III implements the full
129 * 64 bit virtual address space, but we don't really have any use for it and
130 * 43 bits of user address space is considered to be "enough", so we ignore it.
132 * Upper region: 0xffffffffffffffff
135 * Hole: 0xfffff7ffffffffff
138 * Lower region: 0x000007ffffffffff
141 * In general we ignore the upper region, and use the lower region as mappable
144 * We define some interesting address constants:
146 * VM_MIN_ADDRESS and VM_MAX_ADDRESS define the start and end of the entire
147 * 64 bit address space, mostly just for convenience.
149 * VM_MIN_DIRECT_ADDRESS and VM_MAX_DIRECT_ADDRESS define the start and end
150 * of the direct mapped region. This maps virtual addresses to physical
151 * addresses directly using 4mb tlb entries, with the physical address encoded
152 * in the lower 43 bits of virtual address. These mappings are convenient
153 * because they do not require page tables, and because they never change they
154 * do not require tlb flushes. However, since these mappings are cacheable,
155 * we must ensure that all pages accessed this way are either not double
156 * mapped, or that all other mappings have virtual color equal to physical
157 * color, in order to avoid creating illegal aliases in the data cache.
159 * VM_MIN_KERNEL_ADDRESS and VM_MAX_KERNEL_ADDRESS define the start and end of
160 * mappable kernel virtual address space. VM_MIN_KERNEL_ADDRESS is basically
161 * arbitrary, a convenient address is chosen which allows both the kernel text
162 * and data and the prom's address space to be mapped with 1 4mb tsb page.
163 * VM_MAX_KERNEL_ADDRESS is variable, computed at startup time based on the
164 * amount of physical memory available. Each 4mb tsb page provides 1g of
165 * virtual address space, with the only practical limit being available
168 * VM_MIN_PROM_ADDRESS and VM_MAX_PROM_ADDRESS define the start and end of the
169 * prom address space. On startup the prom's mappings are duplicated in the
170 * kernel tsb, to allow prom memory to be accessed normally by the kernel.
172 * VM_MIN_USER_ADDRESS and VM_MAX_USER_ADDRESS define the start and end of the
173 * user address space. There are some hardware errata about using addresses
174 * at the boundary of the va hole, so we allow just under 43 bits of user
175 * address space. Note that the kernel and user address spaces overlap, but
176 * this doesn't matter because they use different tlb contexts, and because
177 * the kernel address space is not mapped into each process' address space.
179 #define VM_MIN_ADDRESS (0x0000000000000000UL)
180 #define VM_MAX_ADDRESS (0xffffffffffffffffUL)
182 #define VM_MIN_DIRECT_ADDRESS (0xfffff80000000000UL)
183 #define VM_MAX_DIRECT_ADDRESS (VM_MAX_ADDRESS)
185 #define VM_MIN_KERNEL_ADDRESS (0x00000000c0000000UL)
186 #define VM_MAX_KERNEL_ADDRESS (vm_max_kernel_address)
188 #define VM_MIN_PROM_ADDRESS (0x00000000f0000000UL)
189 #define VM_MAX_PROM_ADDRESS (0x00000000ffffffffUL)
191 #define VM_MIN_USER_ADDRESS (0x0000000000000000UL)
192 #define VM_MAX_USER_ADDRESS (0x000007fe00000000UL)
194 #define VM_MINUSER_ADDRESS (VM_MIN_USER_ADDRESS)
195 #define VM_MAXUSER_ADDRESS (VM_MAX_USER_ADDRESS)
197 #define KERNBASE (VM_MIN_KERNEL_ADDRESS)
198 #define PROMBASE (VM_MIN_PROM_ADDRESS)
199 #define USRSTACK (VM_MAX_USER_ADDRESS)
202 * How many physical pages per kmem arena virtual page.
204 #ifndef VM_KMEM_SIZE_SCALE
205 #define VM_KMEM_SIZE_SCALE (tsb_kernel_ldd_phys == 0 ? 3 : 2)
209 * Optional floor (in bytes) on the size of the kmem arena.
211 #ifndef VM_KMEM_SIZE_MIN
212 #define VM_KMEM_SIZE_MIN (16 * 1024 * 1024)
216 * Optional ceiling (in bytes) on the size of the kmem arena: 60% of the
219 #ifndef VM_KMEM_SIZE_MAX
220 #define VM_KMEM_SIZE_MAX ((VM_MAX_KERNEL_ADDRESS - \
221 VM_MIN_KERNEL_ADDRESS + 1) * 3 / 5)
225 * Initial pagein size of beginning of executable file.
227 #ifndef VM_INITIAL_PAGEIN
228 #define VM_INITIAL_PAGEIN 16
231 #define UMA_MD_SMALL_ALLOC
233 extern u_int tsb_kernel_ldd_phys;
234 extern vm_offset_t vm_max_kernel_address;
237 * Older sparc64 machines have a virtually indexed L1 data cache of 16KB.
238 * Consequently, mapping the same physical page multiple times may have
241 #define ZERO_REGION_SIZE PAGE_SIZE
243 #include <machine/tlb.h>
248 #define PMAP_HAS_DMAP dcache_color_ignore
249 #define PHYS_TO_DMAP(x) (TLB_PHYS_TO_DIRECT(x))
251 #endif /* !_MACHINE_VMPARAM_H_ */