2 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
7 * This code is derived from software contributed to Berkeley by
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11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
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18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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34 * from: @(#)vmparam.h 5.9 (Berkeley) 5/12/91
35 * from: FreeBSD: src/sys/i386/include/vmparam.h,v 1.33 2000/03/30
39 #ifndef _MACHINE_VMPARAM_H_
40 #define _MACHINE_VMPARAM_H_
43 * Virtual memory related constants, all in bytes
46 #define MAXTSIZ (1*1024*1024*1024) /* max text size */
49 #define DFLDSIZ (128*1024*1024) /* initial data size limit */
52 #define MAXDSIZ (1*1024*1024*1024) /* max data size */
55 #define DFLSSIZ (128*1024*1024) /* initial stack size limit */
58 #define MAXSSIZ (1*1024*1024*1024) /* max stack size */
61 #define SGROWSIZ (128*1024) /* amount to grow stack */
65 * The physical address space is sparsely populated.
67 #define VM_PHYSSEG_SPARSE
70 * The number of PHYSSEG entries must be one greater than the number
71 * of phys_avail entries because the phys_avail entry that spans the
72 * largest physical address that is accessible by ISA DMA is split
73 * into two PHYSSEG entries.
75 #define VM_PHYSSEG_MAX 64
78 * Create two free page pools: VM_FREEPOOL_DEFAULT is the default pool
79 * from which physical pages are allocated and VM_FREEPOOL_DIRECT is
80 * the pool from which physical pages for small UMA objects are
83 #define VM_NFREEPOOL 2
84 #define VM_FREEPOOL_DEFAULT 0
85 #define VM_FREEPOOL_DIRECT 1
88 * Create two free page lists: VM_FREELIST_DEFAULT is for physical
89 * pages that are above the largest physical address that is
90 * accessible by ISA DMA and VM_FREELIST_ISADMA is for physical pages
91 * that are below that address.
93 #define VM_NFREELIST 2
94 #define VM_FREELIST_DEFAULT 0
95 #define VM_FREELIST_ISADMA 1
98 * An allocation size of 16MB is supported in order to optimize the
99 * use of the direct map by UMA. Specifically, a cache line contains
100 * at most four TTEs, collectively mapping 16MB of physical memory.
101 * By reducing the number of distinct 16MB "pages" that are used by UMA,
102 * the physical memory allocator reduces the likelihood of both 4MB
103 * page TLB misses and cache misses caused by 4MB page TLB misses.
105 #define VM_NFREEORDER 12
108 * Enable superpage reservations: 1 level.
110 #ifndef VM_NRESERVLEVEL
111 #define VM_NRESERVLEVEL 1
115 * Level 0 reservations consist of 512 pages.
117 #ifndef VM_LEVEL_0_ORDER
118 #define VM_LEVEL_0_ORDER 9
122 * Address space layout.
124 * UltraSPARC I and II implement a 44 bit virtual address space. The address
125 * space is split into 2 regions at each end of the 64 bit address space, with
126 * an out of range "hole" in the middle. UltraSPARC III implements the full
127 * 64 bit virtual address space, but we don't really have any use for it and
128 * 43 bits of user address space is considered to be "enough", so we ignore it.
130 * Upper region: 0xffffffffffffffff
133 * Hole: 0xfffff7ffffffffff
136 * Lower region: 0x000007ffffffffff
139 * In general we ignore the upper region, and use the lower region as mappable
142 * We define some interesting address constants:
144 * VM_MIN_ADDRESS and VM_MAX_ADDRESS define the start and end of the entire
145 * 64 bit address space, mostly just for convenience.
147 * VM_MIN_DIRECT_ADDRESS and VM_MAX_DIRECT_ADDRESS define the start and end
148 * of the direct mapped region. This maps virtual addresses to physical
149 * addresses directly using 4mb tlb entries, with the physical address encoded
150 * in the lower 43 bits of virtual address. These mappings are convenient
151 * because they do not require page tables, and because they never change they
152 * do not require tlb flushes. However, since these mappings are cacheable,
153 * we must ensure that all pages accessed this way are either not double
154 * mapped, or that all other mappings have virtual color equal to physical
155 * color, in order to avoid creating illegal aliases in the data cache.
157 * VM_MIN_KERNEL_ADDRESS and VM_MAX_KERNEL_ADDRESS define the start and end of
158 * mappable kernel virtual address space. VM_MIN_KERNEL_ADDRESS is basically
159 * arbitrary, a convenient address is chosen which allows both the kernel text
160 * and data and the prom's address space to be mapped with 1 4mb tsb page.
161 * VM_MAX_KERNEL_ADDRESS is variable, computed at startup time based on the
162 * amount of physical memory available. Each 4mb tsb page provides 1g of
163 * virtual address space, with the only practical limit being available
166 * VM_MIN_PROM_ADDRESS and VM_MAX_PROM_ADDRESS define the start and end of the
167 * prom address space. On startup the prom's mappings are duplicated in the
168 * kernel tsb, to allow prom memory to be accessed normally by the kernel.
170 * VM_MIN_USER_ADDRESS and VM_MAX_USER_ADDRESS define the start and end of the
171 * user address space. There are some hardware errata about using addresses
172 * at the boundary of the va hole, so we allow just under 43 bits of user
173 * address space. Note that the kernel and user address spaces overlap, but
174 * this doesn't matter because they use different tlb contexts, and because
175 * the kernel address space is not mapped into each process' address space.
177 #define VM_MIN_ADDRESS (0x0000000000000000UL)
178 #define VM_MAX_ADDRESS (0xffffffffffffffffUL)
180 #define VM_MIN_DIRECT_ADDRESS (0xfffff80000000000UL)
181 #define VM_MAX_DIRECT_ADDRESS (VM_MAX_ADDRESS)
183 #define VM_MIN_KERNEL_ADDRESS (0x00000000c0000000UL)
184 #define VM_MAX_KERNEL_ADDRESS (vm_max_kernel_address)
186 #define VM_MIN_PROM_ADDRESS (0x00000000f0000000UL)
187 #define VM_MAX_PROM_ADDRESS (0x00000000ffffffffUL)
189 #define VM_MIN_USER_ADDRESS (0x0000000000000000UL)
190 #define VM_MAX_USER_ADDRESS (0x000007fe00000000UL)
192 #define VM_MINUSER_ADDRESS (VM_MIN_USER_ADDRESS)
193 #define VM_MAXUSER_ADDRESS (VM_MAX_USER_ADDRESS)
195 #define KERNBASE (VM_MIN_KERNEL_ADDRESS)
196 #define PROMBASE (VM_MIN_PROM_ADDRESS)
197 #define USRSTACK (VM_MAX_USER_ADDRESS)
200 * How many physical pages per kmem arena virtual page.
202 #ifndef VM_KMEM_SIZE_SCALE
203 #define VM_KMEM_SIZE_SCALE (tsb_kernel_ldd_phys == 0 ? 3 : 2)
207 * Optional floor (in bytes) on the size of the kmem arena.
209 #ifndef VM_KMEM_SIZE_MIN
210 #define VM_KMEM_SIZE_MIN (16 * 1024 * 1024)
214 * Optional ceiling (in bytes) on the size of the kmem arena: 60% of the
217 #ifndef VM_KMEM_SIZE_MAX
218 #define VM_KMEM_SIZE_MAX ((VM_MAX_KERNEL_ADDRESS - \
219 VM_MIN_KERNEL_ADDRESS + 1) * 3 / 5)
223 * Initial pagein size of beginning of executable file.
225 #ifndef VM_INITIAL_PAGEIN
226 #define VM_INITIAL_PAGEIN 16
229 #define UMA_MD_SMALL_ALLOC
231 extern u_int tsb_kernel_ldd_phys;
232 extern vm_offset_t vm_max_kernel_address;
235 * Older sparc64 machines have a virtually indexed L1 data cache of 16KB.
236 * Consequently, mapping the same physical page multiple times may have
239 #define ZERO_REGION_SIZE PAGE_SIZE
243 #define SFBUF_OPTIONAL_DIRECT_MAP dcache_color_ignore
244 #include <machine/tlb.h>
245 #define SFBUF_PHYS_DMAP(x) TLB_PHYS_TO_DIRECT(x)
247 #endif /* !_MACHINE_VMPARAM_H_ */