2 * Copyright (c) 2003 by Thomas Moestl <tmm@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
21 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
23 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include "opt_ofw_pci.h"
31 #include <sys/param.h>
32 #include <sys/systm.h>
35 #include <dev/ofw/ofw_bus.h>
36 #include <dev/ofw/ofw_pci.h>
37 #include <dev/ofw/openfirm.h>
39 #include <machine/bus.h>
40 #include <machine/ofw_bus.h>
42 #include <dev/pci/pcireg.h>
43 #include <dev/pci/pcivar.h>
44 #include <dev/pci/pcib_private.h>
48 #include <sparc64/pci/ofw_pci.h>
49 #include <sparc64/pci/ofw_pcib_subr.h>
52 ofw_pcib_gen_setup(device_t bridge)
54 struct ofw_pcib_gen_softc *sc;
59 sc = device_get_softc(bridge);
60 sc->ops_pcib_sc.dev = bridge;
61 sc->ops_node = ofw_bus_get_node(bridge);
62 KASSERT(sc->ops_node != 0,
63 ("ofw_pcib_gen_setup: no ofw pci parent bus!"));
66 * Setup the secondary bus number register, if supported, by
67 * allocating a new unique bus number for it; the firmware
68 * preset does not always seem to be correct in that case.
71 secbus = OFW_PCI_ALLOC_BUSNO(bridge);
73 pci_write_config(bridge, PCIR_PRIBUS_1, pci_get_bus(bridge), 1);
74 pci_write_config(bridge, PCIR_SECBUS_1, secbus, 1);
75 pci_write_config(bridge, PCIR_SUBBUS_1, secbus, 1);
76 sc->ops_pcib_sc.subbus = sc->ops_pcib_sc.secbus = secbus;
77 /* Notify parent bridges. */
78 OFW_PCI_ADJUST_BUSRANGE(device_get_parent(bridge), secbus);
82 ofw_bus_setup_iinfo(sc->ops_node, &sc->ops_iinfo,
83 sizeof(ofw_pci_intr_t));
87 ofw_pcib_gen_route_interrupt(device_t bridge, device_t dev, int intpin)
89 struct ofw_pcib_gen_softc *sc;
90 struct ofw_bus_iinfo *ii;
91 struct ofw_pci_register reg;
92 ofw_pci_intr_t pintr, mintr;
93 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
95 sc = device_get_softc(bridge);
97 if (ii->opi_imapsz > 0) {
99 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), ii, ®,
100 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
103 * If we've found a mapping, return it and don't map
104 * it again on higher levels - that causes problems
105 * in some cases, and never seems to be required.
109 } else if (intpin >= 1 && intpin <= 4) {
111 * When an interrupt map is missing, we need to do the
112 * standard PCI swizzle and continue mapping at the parent.
114 return (pcib_route_interrupt(bridge, dev, intpin));
116 /* Try at the parent. */
117 return (PCIB_ROUTE_INTERRUPT(device_get_parent(device_get_parent(
118 bridge)), bridge, intpin));
122 ofw_pcib_gen_get_node(device_t bridge, device_t dev)
124 struct ofw_pcib_gen_softc *sc;
126 sc = device_get_softc(bridge);
127 return (sc->ops_node);
131 ofw_pcib_gen_adjust_busrange(device_t bridge, u_int subbus)
133 struct ofw_pcib_gen_softc *sc;
135 sc = device_get_softc(bridge);
136 if (subbus > sc->ops_pcib_sc.subbus) {
138 device_printf(bridge,
139 "adjusting subordinate bus number from %d to %d\n",
140 sc->ops_pcib_sc.subbus, subbus);
142 pci_write_config(bridge, PCIR_SUBBUS_1, subbus, 1);
143 sc->ops_pcib_sc.subbus = subbus;
144 /* Notify parent bridges. */
145 OFW_PCI_ADJUST_BUSRANGE(device_get_parent(bridge), subbus);