2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * Copyright (c) 2003, Thomas Moestl <tmm@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include "opt_ofw_pci.h"
35 #include <sys/param.h>
37 #include <sys/kernel.h>
38 #include <sys/libkern.h>
39 #include <sys/module.h>
40 #include <sys/pciio.h>
42 #include <dev/ofw/ofw_bus.h>
43 #include <dev/ofw/ofw_pci.h>
44 #include <dev/ofw/openfirm.h>
46 #include <machine/bus.h>
47 #include <machine/bus_common.h>
48 #include <machine/iommureg.h>
49 #include <machine/resource.h>
51 #include <dev/pci/pcireg.h>
52 #include <dev/pci/pcivar.h>
53 #include <dev/pci/pci_private.h>
55 #include <sparc64/pci/ofw_pci.h>
60 /* Helper functions */
61 static void ofw_pcibus_setup_device(device_t bridge, uint32_t clock,
62 u_int busno, u_int slot, u_int func);
65 static device_probe_t ofw_pcibus_probe;
66 static device_attach_t ofw_pcibus_attach;
67 static pci_assign_interrupt_t ofw_pcibus_assign_interrupt;
68 static ofw_bus_get_compat_t ofw_pcibus_get_compat;
69 static ofw_bus_get_model_t ofw_pcibus_get_model;
70 static ofw_bus_get_name_t ofw_pcibus_get_name;
71 static ofw_bus_get_node_t ofw_pcibus_get_node;
72 static ofw_bus_get_type_t ofw_pcibus_get_type;
74 static device_method_t ofw_pcibus_methods[] = {
75 /* Device interface */
76 DEVMETHOD(device_probe, ofw_pcibus_probe),
77 DEVMETHOD(device_attach, ofw_pcibus_attach),
82 DEVMETHOD(pci_assign_interrupt, ofw_pcibus_assign_interrupt),
84 /* ofw_bus interface */
85 DEVMETHOD(ofw_bus_get_compat, ofw_pcibus_get_compat),
86 DEVMETHOD(ofw_bus_get_model, ofw_pcibus_get_model),
87 DEVMETHOD(ofw_bus_get_name, ofw_pcibus_get_name),
88 DEVMETHOD(ofw_bus_get_node, ofw_pcibus_get_node),
89 DEVMETHOD(ofw_bus_get_type, ofw_pcibus_get_type),
94 struct ofw_pcibus_devinfo {
95 struct pci_devinfo opd_dinfo;
103 static devclass_t pci_devclass;
105 DEFINE_CLASS_1(pci, ofw_pcibus_driver, ofw_pcibus_methods, 1 /* no softc */,
107 DRIVER_MODULE(ofw_pcibus, pcib, ofw_pcibus_driver, pci_devclass, 0, 0);
108 MODULE_VERSION(ofw_pcibus, 1);
109 MODULE_DEPEND(ofw_pcibus, pci, 1, 1, 1);
112 ofw_pcibus_probe(device_t dev)
115 if (ofw_bus_get_node(dev) == 0)
117 device_set_desc(dev, "OFW PCI bus");
123 * Perform miscellaneous setups the firmware usually does not do for us.
126 ofw_pcibus_setup_device(device_t bridge, uint32_t clock, u_int busno,
127 u_int slot, u_int func)
132 * Initialize the latency timer register for busmaster devices to
133 * work properly. This is another task which the firmware doesn't
134 * always perform. The Min_Gnt register can be used to compute its
135 * recommended value: it contains the desired latency in units of
136 * 1/4 us assuming a clock rate of 33MHz. To calculate the correct
137 * latency timer value, the clock frequency of the bus (defaulting
138 * to 33MHz) should be used and no wait states assumed.
139 * For bridges, we additionally set up the bridge control and the
140 * secondary latency registers.
142 if ((PCIB_READ_CONFIG(bridge, busno, slot, func, PCIR_HDRTYPE, 1) &
143 PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) {
144 reg = PCIB_READ_CONFIG(bridge, busno, slot, func,
145 PCIR_BRIDGECTL_1, 1);
147 reg |= PCIB_BCR_MASTER_ABORT_MODE | PCIB_BCR_SERR_ENABLE |
149 reg |= PCIB_BCR_SERR_ENABLE |
151 PCIB_BCR_PERR_ENABLE;
153 device_printf(bridge,
154 "bridge %d/%d/%d: control 0x%x -> 0x%x\n",
155 busno, slot, func, PCIB_READ_CONFIG(bridge, busno, slot,
156 func, PCIR_BRIDGECTL_1, 1), reg);
157 #endif /* OFW_PCI_DEBUG */
158 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_BRIDGECTL_1,
161 reg = OFW_PCI_LATENCY;
163 device_printf(bridge,
164 "bridge %d/%d/%d: latency timer %d -> %d\n",
165 busno, slot, func, PCIB_READ_CONFIG(bridge, busno, slot,
166 func, PCIR_SECLAT_1, 1), reg);
167 #endif /* OFW_PCI_DEBUG */
168 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_SECLAT_1,
171 reg = PCIB_READ_CONFIG(bridge, busno, slot, func,
184 reg = OFW_PCI_LATENCY;
187 device_printf(bridge, "device %d/%d/%d: latency timer %d -> %d\n",
188 busno, slot, func, PCIB_READ_CONFIG(bridge, busno, slot, func,
189 PCIR_LATTIMER, 1), reg);
190 #endif /* OFW_PCI_DEBUG */
191 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_LATTIMER, reg, 1);
194 * Compute a value to write into the cache line size register.
195 * The role of the streaming cache is unclear in write invalidate
196 * transfers, so it is made sure that it's line size is always
197 * reached. Generally, the cache line size is fixed at 64 bytes
198 * by Fireplane/Safari, JBus and UPA.
200 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_CACHELNSZ,
201 STRBUF_LINESZ / sizeof(uint32_t), 1);
204 * The preset in the intline register is usually wrong. Reset
205 * it to 255, so that the PCI code will reroute the interrupt if
208 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_INTLINE,
213 ofw_pcibus_attach(device_t dev)
216 struct ofw_pci_register pcir;
217 struct ofw_pcibus_devinfo *dinfo;
218 phandle_t node, child;
221 u_int busno, func, slot;
223 pcib = device_get_parent(dev);
225 * Ask the bridge for the bus number - in some cases, we need to
226 * renumber buses, so the firmware information cannot be trusted.
228 busno = pcib_get_bus(dev);
230 device_printf(dev, "physical bus=%d\n", busno);
231 node = ofw_bus_get_node(dev);
232 if (OF_getprop(ofw_bus_get_node(pcib), "clock-frequency", &clock,
233 sizeof(clock)) == -1)
235 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
236 if ((OF_getprop_alloc(child, "name", 1, (void **)&cname)) == -1)
239 if (OF_getprop(child, "reg", &pcir, sizeof(pcir)) == -1) {
240 device_printf(dev, "<%s>: incomplete\n", cname);
241 free(cname, M_OFWPROP);
244 slot = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi);
245 func = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi);
246 if (pci_find_bsf(busno, slot, func) != NULL)
248 ofw_pcibus_setup_device(pcib, clock, busno, slot, func);
249 dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib,
250 busno, slot, func, sizeof(*dinfo));
252 dinfo->opd_name = cname;
253 dinfo->opd_node = child;
254 OF_getprop_alloc(child, "compatible", 1,
255 (void **)&dinfo->opd_compat);
256 OF_getprop_alloc(child, "device_type", 1,
257 (void **)&dinfo->opd_type);
258 OF_getprop_alloc(child, "model", 1,
259 (void **)&dinfo->opd_model);
260 pci_add_child(dev, (struct pci_devinfo *)dinfo);
262 free(cname, M_OFWPROP);
265 return (bus_generic_attach(dev));
269 ofw_pcibus_assign_interrupt(device_t dev, device_t child)
274 isz = OF_getprop(ofw_bus_get_node(child), "interrupts", &intr,
276 if (isz != sizeof(intr)) {
277 /* No property; our best guess is the intpin. */
278 intr = pci_get_intpin(child);
279 } else if (intr >= 255) {
281 * A fully specified interrupt (including IGN), as present on
282 * SPARCengine Ultra AX and E450. Extract the INO and return
285 return (INTINO(intr));
288 * If we got intr from a property, it may or may not be an intpin.
289 * For on-board devices, it frequently is not, and is completely out
290 * of the valid intpin range. For PCI slots, it hopefully is,
291 * otherwise we will have trouble interfacing with non-OFW buses
293 * Since we cannot tell which it is without violating layering, we
294 * will always use the route_interrupt method, and treat exceptions
295 * on the level they become apparent.
297 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr));
301 ofw_pcibus_get_compat(device_t bus, device_t dev)
303 struct ofw_pcibus_devinfo *dinfo;
305 dinfo = device_get_ivars(dev);
306 return (dinfo->opd_compat);
310 ofw_pcibus_get_model(device_t bus, device_t dev)
312 struct ofw_pcibus_devinfo *dinfo;
314 dinfo = device_get_ivars(dev);
315 return (dinfo->opd_model);
319 ofw_pcibus_get_name(device_t bus, device_t dev)
321 struct ofw_pcibus_devinfo *dinfo;
323 dinfo = device_get_ivars(dev);
324 return (dinfo->opd_name);
328 ofw_pcibus_get_node(device_t bus, device_t dev)
330 struct ofw_pcibus_devinfo *dinfo;
332 dinfo = device_get_ivars(dev);
333 return (dinfo->opd_node);
337 ofw_pcibus_get_type(device_t bus, device_t dev)
339 struct ofw_pcibus_devinfo *dinfo;
341 dinfo = device_get_ivars(dev);
342 return (dinfo->opd_type);