2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * Copyright (c) 2003, Thomas Moestl <tmm@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include "opt_ofw_pci.h"
35 #include <sys/param.h>
37 #include <sys/kernel.h>
38 #include <sys/libkern.h>
39 #include <sys/module.h>
40 #include <sys/pciio.h>
42 #include <dev/ofw/ofw_bus.h>
43 #include <dev/ofw/ofw_bus_subr.h>
44 #include <dev/ofw/ofw_pci.h>
45 #include <dev/ofw/openfirm.h>
47 #include <machine/bus.h>
48 #include <machine/bus_common.h>
50 #include <machine/cache.h>
51 #include <machine/iommureg.h>
53 #include <machine/resource.h>
55 #include <dev/pci/pcireg.h>
56 #include <dev/pci/pcivar.h>
57 #include <dev/pci/pci_private.h>
59 #include <sparc64/pci/ofw_pci.h>
64 /* Helper functions. */
65 static void ofw_pcibus_setup_device(device_t, u_int, u_int, u_int);
68 static device_probe_t ofw_pcibus_probe;
69 static device_attach_t ofw_pcibus_attach;
70 static pci_assign_interrupt_t ofw_pcibus_assign_interrupt;
71 static ofw_bus_get_devinfo_t ofw_pcibus_get_devinfo;
73 static device_method_t ofw_pcibus_methods[] = {
74 /* Device interface */
75 DEVMETHOD(device_probe, ofw_pcibus_probe),
76 DEVMETHOD(device_attach, ofw_pcibus_attach),
81 DEVMETHOD(pci_assign_interrupt, ofw_pcibus_assign_interrupt),
83 /* ofw_bus interface */
84 DEVMETHOD(ofw_bus_get_devinfo, ofw_pcibus_get_devinfo),
85 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
86 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
87 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
88 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
89 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
94 struct ofw_pcibus_devinfo {
95 struct pci_devinfo opd_dinfo;
96 struct ofw_bus_devinfo opd_obdinfo;
99 static devclass_t pci_devclass;
101 DEFINE_CLASS_1(pci, ofw_pcibus_driver, ofw_pcibus_methods, 1 /* no softc */,
103 DRIVER_MODULE(ofw_pcibus, pcib, ofw_pcibus_driver, pci_devclass, 0, 0);
104 MODULE_VERSION(ofw_pcibus, 1);
105 MODULE_DEPEND(ofw_pcibus, pci, 1, 1, 1);
108 ofw_pcibus_probe(device_t dev)
111 if (ofw_bus_get_node(dev) == 0)
113 device_set_desc(dev, "OFW PCI bus");
119 * Perform miscellaneous setups the firmware usually does not do for us.
122 ofw_pcibus_setup_device(device_t bridge, u_int busno, u_int slot, u_int func)
129 * Initialize the latency timer register for busmaster devices to work
130 * properly. This is another task which the firmware does not always
131 * perform. The Min_Gnt register can be used to compute it's recommended
132 * value: it contains the desired latency in units of 1/4 us. To
133 * calculate the correct latency timer value, a bus clock of 33MHz and
134 * no wait states should be assumed.
136 lat = PCIB_READ_CONFIG(bridge, busno, slot, func, PCIR_MINGNT, 1) *
140 device_printf(bridge, "device %d/%d/%d: latency timer %d -> "
141 "%d\n", busno, slot, func,
142 PCIB_READ_CONFIG(bridge, busno, slot, func,
143 PCIR_LATTIMER, 1), lat);
144 #endif /* OFW_PCI_DEBUG */
145 PCIB_WRITE_CONFIG(bridge, busno, slot, func,
146 PCIR_LATTIMER, min(lat, 255), 1);
151 * Compute a value to write into the cache line size register.
152 * The role of the streaming cache is unclear in write invalidate
153 * transfers, so it is made sure that it's line size is always reached.
155 clnsz = max(cache.ec_linesize, STRBUF_LINESZ);
156 KASSERT((clnsz / STRBUF_LINESZ) * STRBUF_LINESZ == clnsz &&
157 (clnsz / cache.ec_linesize) * cache.ec_linesize == clnsz &&
158 (clnsz / 4) * 4 == clnsz, ("bogus cache line size %d", clnsz));
159 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_CACHELNSZ,
164 * The preset in the intline register is usually wrong. Reset it to 255,
165 * so that the PCI code will reroute the interrupt if needed.
167 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_INTLINE,
172 ofw_pcibus_attach(device_t dev)
175 struct ofw_pci_register pcir;
176 struct ofw_pcibus_devinfo *dinfo;
177 phandle_t node, child;
178 u_int slot, busno, func;
180 pcib = device_get_parent(dev);
183 * Ask the bridge for the bus number - in some cases, we need to
184 * renumber buses, so the firmware information cannot be trusted.
186 busno = pcib_get_bus(dev);
188 device_printf(dev, "physical bus=%d\n", busno);
190 node = ofw_bus_get_node(dev);
191 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
192 if (OF_getprop(child, "reg", &pcir, sizeof(pcir)) == -1)
194 slot = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi);
195 func = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi);
196 if (pci_find_bsf(busno, slot, func) != NULL)
198 ofw_pcibus_setup_device(pcib, busno, slot, func);
199 dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib,
200 busno, slot, func, sizeof(*dinfo));
203 if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, child) !=
205 pci_freecfg((struct pci_devinfo *)dinfo);
208 pci_add_child(dev, (struct pci_devinfo *)dinfo);
211 return (bus_generic_attach(dev));
215 ofw_pcibus_assign_interrupt(device_t dev, device_t child)
220 isz = OF_getprop(ofw_bus_get_node(child), "interrupts", &intr,
222 if (isz != sizeof(intr)) {
223 /* No property; our best guess is the intpin. */
224 intr = pci_get_intpin(child);
225 } else if (intr >= 255) {
227 * A fully specified interrupt (including IGN), as present on
228 * SPARCengine Ultra AX and e450. Extract the INO and return it.
230 return (INTINO(intr));
233 * If we got intr from a property, it may or may not be an intpin.
234 * For on-board devices, it frequently is not, and is completely out
235 * of the valid intpin range. For PCI slots, it hopefully is, otherwise
236 * we will have trouble interfacing with non-OFW buses such as cardbus.
237 * Since we cannot tell which it is without violating layering, we
238 * will always use the route_interrupt method, and treat exceptions on
239 * the level they become apparent.
241 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr));
244 static const struct ofw_bus_devinfo *
245 ofw_pcibus_get_devinfo(device_t bus, device_t dev)
247 struct ofw_pcibus_devinfo *dinfo;
249 dinfo = device_get_ivars(dev);
250 return (&dinfo->opd_obdinfo);