2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+'
38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges.
41 #include "opt_ofw_pci.h"
42 #include "opt_psycho.h"
44 #include <sys/param.h>
45 #include <sys/systm.h>
47 #include <sys/endian.h>
49 #include <sys/kernel.h>
51 #include <sys/malloc.h>
52 #include <sys/module.h>
53 #include <sys/mutex.h>
55 #include <sys/reboot.h>
58 #include <dev/ofw/ofw_bus.h>
59 #include <dev/ofw/ofw_pci.h>
60 #include <dev/ofw/openfirm.h>
62 #include <machine/bus.h>
63 #include <machine/bus_common.h>
64 #include <machine/bus_private.h>
65 #include <machine/iommureg.h>
66 #include <machine/iommuvar.h>
67 #include <machine/resource.h>
68 #include <machine/ver.h>
70 #include <dev/pci/pcireg.h>
71 #include <dev/pci/pcivar.h>
73 #include <sparc64/pci/ofw_pci.h>
74 #include <sparc64/pci/psychoreg.h>
75 #include <sparc64/pci/psychovar.h>
79 static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *,
81 static const struct psycho_desc *psycho_get_desc(device_t);
82 static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t,
83 driver_filter_t, driver_intr_t);
84 static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *,
85 bus_addr_t *, u_long *);
86 static void sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map,
88 static void psycho_intr_enable(void *);
89 static void psycho_intr_disable(void *);
90 static void psycho_intr_assign(void *);
91 static void psycho_intr_clear(void *);
93 /* Interrupt handlers */
94 static driver_filter_t psycho_ue;
95 static driver_filter_t psycho_ce;
96 static driver_filter_t psycho_pci_bus;
97 static driver_filter_t psycho_powerfail;
98 static driver_intr_t psycho_overtemp;
99 #ifdef PSYCHO_MAP_WAKEUP
100 static driver_filter_t psycho_wakeup;
104 static void psycho_iommu_init(struct psycho_softc *, int, uint32_t);
109 static device_probe_t psycho_probe;
110 static device_attach_t psycho_attach;
111 static bus_read_ivar_t psycho_read_ivar;
112 static bus_setup_intr_t psycho_setup_intr;
113 static bus_alloc_resource_t psycho_alloc_resource;
114 static bus_activate_resource_t psycho_activate_resource;
115 static bus_adjust_resource_t psycho_adjust_resource;
116 static bus_get_dma_tag_t psycho_get_dma_tag;
117 static pcib_maxslots_t psycho_maxslots;
118 static pcib_read_config_t psycho_read_config;
119 static pcib_write_config_t psycho_write_config;
120 static pcib_route_interrupt_t psycho_route_interrupt;
121 static ofw_bus_get_node_t psycho_get_node;
122 static ofw_pci_setup_device_t psycho_setup_device;
124 static device_method_t psycho_methods[] = {
125 /* Device interface */
126 DEVMETHOD(device_probe, psycho_probe),
127 DEVMETHOD(device_attach, psycho_attach),
128 DEVMETHOD(device_shutdown, bus_generic_shutdown),
129 DEVMETHOD(device_suspend, bus_generic_suspend),
130 DEVMETHOD(device_resume, bus_generic_resume),
133 DEVMETHOD(bus_read_ivar, psycho_read_ivar),
134 DEVMETHOD(bus_setup_intr, psycho_setup_intr),
135 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
136 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource),
137 DEVMETHOD(bus_activate_resource, psycho_activate_resource),
138 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
139 DEVMETHOD(bus_adjust_resource, psycho_adjust_resource),
140 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
141 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag),
144 DEVMETHOD(pcib_maxslots, psycho_maxslots),
145 DEVMETHOD(pcib_read_config, psycho_read_config),
146 DEVMETHOD(pcib_write_config, psycho_write_config),
147 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt),
149 /* ofw_bus interface */
150 DEVMETHOD(ofw_bus_get_node, psycho_get_node),
152 /* ofw_pci interface */
153 DEVMETHOD(ofw_pci_setup_device, psycho_setup_device),
158 static devclass_t psycho_devclass;
160 DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods,
161 sizeof(struct psycho_softc));
162 EARLY_DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0,
165 static SLIST_HEAD(, psycho_softc) psycho_softcs =
166 SLIST_HEAD_INITIALIZER(psycho_softcs);
168 static const struct intr_controller psycho_ic = {
175 struct psycho_icarg {
176 struct psycho_softc *pica_sc;
181 #define PSYCHO_READ8(sc, off) \
182 bus_read_8((sc)->sc_mem_res, (off))
183 #define PSYCHO_WRITE8(sc, off, v) \
184 bus_write_8((sc)->sc_mem_res, (off), (v))
185 #define PCICTL_READ8(sc, off) \
186 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off))
187 #define PCICTL_WRITE8(sc, off, v) \
188 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v))
191 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a
192 * single PCI bus and does not have a streaming buffer. It often has an APB
193 * (advanced PCI bridge) connected to it, which was designed specifically for
194 * the IIi. The APB let's the IIi handle two independednt PCI buses, and
195 * appears as two "Simba"'s underneath the Sabre.
197 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's
198 * basically the same as Sabre but without an APB underneath it.
200 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA
201 * bus and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while
202 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You
203 * will usually find a "Psycho+" since I don't think the original "Psycho"
204 * ever shipped, and if it did it would be in the U30.
206 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are
207 * both part of the same IC, they only have a single register space. As such,
208 * they need to be configured together, even though the autoconfiguration will
209 * attach them separately.
211 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often
212 * as pci1 and pci2, although they have been implemented with other PCI bus
213 * numbers on some machines.
215 * On UltraII machines, there can be any number of "Psycho+" ICs, each
216 * providing two PCI buses.
220 const char *pd_string;
225 static const struct psycho_desc psycho_compats[] = {
226 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" },
227 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" },
228 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" },
232 static const struct psycho_desc psycho_models[] = {
233 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" },
234 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" },
238 static const struct psycho_desc *
239 psycho_find_desc(const struct psycho_desc *table, const char *string)
241 const struct psycho_desc *desc;
245 for (desc = table; desc->pd_string != NULL; desc++)
246 if (strcmp(desc->pd_string, string) == 0)
251 static const struct psycho_desc *
252 psycho_get_desc(device_t dev)
254 const struct psycho_desc *rv;
256 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev));
258 rv = psycho_find_desc(psycho_compats,
259 ofw_bus_get_compat(dev));
264 psycho_probe(device_t dev)
268 dtype = ofw_bus_get_type(dev);
269 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 &&
270 psycho_get_desc(dev) != NULL) {
271 device_set_desc(dev, "U2P UPA-PCI bridge");
278 psycho_attach(device_t dev)
280 struct psycho_icarg *pica;
281 struct psycho_softc *asc, *sc, *osc;
282 struct ofw_pci_ranges *range;
283 const struct psycho_desc *desc;
284 bus_addr_t intrclr, intrmap;
287 uint32_t dvmabase, prop, prop_array[2];
291 node = ofw_bus_get_node(dev);
292 sc = device_get_softc(dev);
293 desc = psycho_get_desc(dev);
297 sc->sc_mode = desc->pd_mode;
300 * The Psycho gets three register banks:
301 * (0) per-PBM configuration and status registers
302 * (1) per-PBM PCI configuration space, containing only the
303 * PBM 256-byte PCI header
304 * (2) the shared Psycho configuration registers
306 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
309 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) -
310 bus_get_resource_start(dev, SYS_RES_MEMORY, 2);
311 switch (sc->sc_pcictl) {
319 panic("%s: bogus PCI control register location",
325 sc->sc_pcictl = PSR_PCICTL0;
328 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i,
329 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) |
331 if (sc->sc_mem_res == NULL)
332 panic("%s: could not allocate registers", __func__);
335 * Match other Psychos that are already configured against
336 * the base physical address. This will be the same for a
337 * pair of devices that share register space.
340 SLIST_FOREACH(asc, &psycho_softcs, sc_link) {
341 if (rman_get_start(asc->sc_mem_res) ==
342 rman_get_start(sc->sc_mem_res)) {
349 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF,
351 if (sc->sc_mtx == NULL)
352 panic("%s: could not malloc mutex", __func__);
353 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
355 if (sc->sc_mode != PSYCHO_MODE_PSYCHO)
356 panic("%s: no partner expected", __func__);
357 if (mtx_initialized(osc->sc_mtx) == 0)
358 panic("%s: mutex not initialized", __func__);
359 sc->sc_mtx = osc->sc_mtx;
362 csr = PSYCHO_READ8(sc, PSR_CS);
363 ver = PSYCHO_GCSR_VERS(csr);
364 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */
365 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
366 sc->sc_ign = PSYCHO_GCSR_IGN(csr);
367 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
371 "%s, impl %d, version %d, IGN %#x, bus %c, %dMHz\n",
372 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign,
373 'A' + sc->sc_half, prop / 1000 / 1000);
375 /* Set up the PCI control and PCI diagnostic registers. */
377 csr = PCICTL_READ8(sc, PCR_CS);
378 csr &= ~PCICTL_ARB_PARK;
379 if (OF_getproplen(node, "no-bus-parking") < 0)
380 csr |= PCICTL_ARB_PARK;
382 /* Workarounds for version specific bugs. */
383 dr = PCICTL_READ8(sc, PCR_DIAG);
387 dr &= ~DIAG_DWSYNC_DIS;
391 csr &= ~PCICTL_ARB_PARK;
392 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS;
396 dr |= DIAG_DWSYNC_DIS;
397 dr &= ~DIAG_RTRY_DIS;
402 csr |= PCICTL_ERRINTEN | PCICTL_ARB_4;
403 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN);
405 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n",
406 (unsigned long long)PCICTL_READ8(sc, PCR_CS),
407 (unsigned long long)csr);
409 PCICTL_WRITE8(sc, PCR_CS, csr);
411 dr &= ~DIAG_ISYNC_DIS;
413 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
414 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG),
415 (unsigned long long)dr);
417 PCICTL_WRITE8(sc, PCR_DIAG, dr);
419 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
420 /* Use the PROM preset for now. */
421 csr = PCICTL_READ8(sc, PCR_TAS);
423 panic("%s: Hummingbird/Sabre TAS not initialized.",
425 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT;
429 /* Initialize memory and I/O rmans. */
430 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
431 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports";
432 if (rman_init(&sc->sc_pci_io_rman) != 0 ||
433 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0)
434 panic("%s: failed to set up I/O rman", __func__);
435 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
436 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory";
437 if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
438 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0)
439 panic("%s: failed to set up memory rman", __func__);
441 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range);
443 * Make sure that the expected ranges are present. The
444 * OFW_PCI_CS_MEM64 one is not currently used though.
446 if (i != PSYCHO_NRANGE)
447 panic("%s: unsupported number of ranges", __func__);
449 * Find the addresses of the various bus spaces.
450 * There should not be multiple ones of one kind.
451 * The physical start addresses of the ranges are the configuration,
452 * memory and I/O handles.
454 for (i = 0; i < PSYCHO_NRANGE; i++) {
455 j = OFW_PCI_RANGE_CS(&range[i]);
456 if (sc->sc_pci_bh[j] != 0)
457 panic("%s: duplicate range for space %d",
459 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]);
461 free(range, M_OFWPROP);
463 /* Register the softc, this is needed for paired Psychos. */
464 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link);
467 * If we're a Hummingbird/Sabre or the first of a pair of Psychos
468 * to arrive here, do the interrupt setup and start up the IOMMU.
472 * Hunt through all the interrupt mapping regs and register
473 * our interrupt controller for the corresponding interrupt
474 * vectors. We do this early in order to be able to catch
477 for (i = 0; i <= PSYCHO_MAX_INO; i++) {
478 if (psycho_find_intrmap(sc, i, &intrmap, &intrclr,
481 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT);
483 panic("%s: could not allocate interrupt "
484 "controller argument", __func__);
486 pica->pica_map = intrmap;
487 pica->pica_clr = intrclr;
490 * Enable all interrupts and clear all interrupt
491 * states. This aids the debugging of interrupt
495 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n",
496 i, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO",
497 (u_long)intrmap, (u_long)PSYCHO_READ8(sc,
498 intrmap), (u_long)intrclr);
499 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, i));
500 PSYCHO_WRITE8(sc, intrclr, INTCLR_IDLE);
501 PSYCHO_WRITE8(sc, intrmap,
502 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, i),
505 j = intr_controller_register(INTMAP_VEC(sc->sc_ign,
506 i), &psycho_ic, pica);
508 device_printf(dev, "could not register "
509 "interrupt controller for INO %d (%d)\n",
513 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
514 sparc64_counter_init(device_get_nameunit(dev),
515 rman_get_bustag(sc->sc_mem_res),
516 rman_get_bushandle(sc->sc_mem_res), PSR_TC0);
519 * Set up IOMMU and PCI configuration if we're the first
520 * of a pair of Psychos to arrive here or a Hummingbird
523 * We should calculate a TSB size based on amount of RAM
524 * and number of bus controllers and number and type of
527 * For the moment, 32KB should be more than enough.
529 sc->sc_is = malloc(sizeof(*sc->sc_is), M_DEVBUF, M_NOWAIT |
531 if (sc->sc_is == NULL)
532 panic("%s: could not malloc IOMMU state", __func__);
533 sc->sc_is->is_flags = IOMMU_PRESERVE_PROM;
534 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
536 malloc(sizeof(*sc->sc_dma_methods), M_DEVBUF,
538 if (sc->sc_dma_methods == NULL)
539 panic("%s: could not malloc DMA methods",
541 memcpy(sc->sc_dma_methods, &iommu_dma_methods,
542 sizeof(*sc->sc_dma_methods));
543 sc->sc_dma_methods->dm_dmamap_sync =
545 sc->sc_is->is_pmaxaddr =
546 IOMMU_MAXADDR(SABRE_IOMMU_BITS);
548 sc->sc_dma_methods = &iommu_dma_methods;
549 sc->sc_is->is_pmaxaddr =
550 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS);
552 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = 0;
553 if (OF_getproplen(node, "no-streaming-cache") < 0)
554 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF;
555 sc->sc_is->is_flags |= (rerun != 1) ? IOMMU_RERUN_DISABLE : 0;
556 psycho_iommu_init(sc, 3, dvmabase);
558 /* Just copy IOMMU state, config tag and address. */
559 sc->sc_dma_methods = &iommu_dma_methods;
560 sc->sc_is = osc->sc_is;
561 if (OF_getproplen(node, "no-streaming-cache") < 0)
562 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF;
563 iommu_reset(sc->sc_is);
566 /* Allocate our tags. */
567 sc->sc_pci_iot = sparc64_alloc_bus_tag(NULL, rman_get_bustag(
568 sc->sc_mem_res), PCI_IO_BUS_SPACE, NULL);
569 if (sc->sc_pci_iot == NULL)
570 panic("%s: could not allocate PCI I/O tag", __func__);
571 sc->sc_pci_cfgt = sparc64_alloc_bus_tag(NULL, rman_get_bustag(
572 sc->sc_mem_res), PCI_CONFIG_BUS_SPACE, NULL);
573 if (sc->sc_pci_cfgt == NULL)
574 panic("%s: could not allocate PCI configuration space tag",
576 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
577 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr,
578 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
579 panic("%s: could not create PCI DMA tag", __func__);
580 /* Customize the tag. */
581 sc->sc_pci_dmat->dt_cookie = sc->sc_is;
582 sc->sc_pci_dmat->dt_mt = sc->sc_dma_methods;
584 i = OF_getprop(node, "bus-range", (void *)prop_array,
587 panic("%s: could not get bus-range", __func__);
588 if (i != sizeof(prop_array))
589 panic("%s: broken bus-range (%d)", __func__, i);
590 sc->sc_pci_secbus = prop_array[0];
591 sc->sc_pci_subbus = prop_array[1];
593 device_printf(dev, "bus range %u to %u; PCI bus %d\n",
594 sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus);
596 /* Clear any pending PCI error bits. */
597 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
598 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus,
599 PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2);
600 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS));
601 PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS));
605 * Establish handlers for interesting interrupts...
607 * XXX We need to remember these and remove this to support
608 * hotplug on the UPA/FHC bus.
610 * XXX Not all controllers have these, but installing them
611 * is better than trying to sort through this mess.
613 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL);
614 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL);
615 #ifdef DEBUGGER_ON_POWERFAIL
616 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail,
619 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL,
620 (driver_intr_t *)psycho_powerfail);
622 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
624 * Hummingbirds/Sabres do not have the following two
629 * The spare hardware interrupt is used for the
630 * over-temperature interrupt.
632 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP,
633 NULL, psycho_overtemp);
634 #ifdef PSYCHO_MAP_WAKEUP
636 * psycho_wakeup() doesn't do anything useful right
639 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP,
640 psycho_wakeup, NULL);
641 #endif /* PSYCHO_MAP_WAKEUP */
645 * Register a PCI bus error interrupt handler according to which
646 * half this is. Hummingbird/Sabre don't have a PCI bus B error
647 * interrupt but they are also only used for PCI bus A.
649 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP :
650 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL);
653 * Set the latency timer register as this isn't always done by the
656 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
657 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
659 for (i = PCIR_VENDOR; i < PCIR_STATUS; i += sizeof(uint16_t))
660 le16enc(&sc->sc_pci_hpbcfg[i], bus_space_read_2(
661 sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG],
662 PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE,
664 for (i = PCIR_REVID; i <= PCIR_BIST; i += sizeof(uint8_t))
665 sc->sc_pci_hpbcfg[i] = bus_space_read_1(sc->sc_pci_cfgt,
666 sc->sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF(
667 sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, i));
669 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
671 * On E250 the interrupt map entry for the EBus bridge is wrong,
672 * causing incorrect interrupts to be assigned to some devices on
673 * the EBus. Work around it by changing our copy of the interrupt
674 * map mask to perform a full comparison of the INO. That way
675 * the interrupt map entry for the EBus bridge won't match at all
676 * and the INOs specified in the "interrupts" properties of the
677 * EBus devices will be used directly instead.
679 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 &&
680 sc->sc_pci_iinfo.opi_imapmsk != NULL)
681 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[
682 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK;
684 device_add_child(dev, "pci", -1);
685 return (bus_generic_attach(dev));
689 psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap,
690 driver_filter_t filt, driver_intr_t intr)
696 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev,
697 SYS_RES_IRQ, &rid, RF_ACTIVE);
698 if (sc->sc_irq_res[index] == NULL && intrmap >= PSR_POWER_INT_MAP) {
700 * These interrupts aren't mandatory and not available
701 * with all controllers (not even Psychos).
705 if (sc->sc_irq_res[index] == NULL ||
706 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) !=
708 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec ||
709 intr_vectors[vec].iv_ic != &psycho_ic ||
710 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index],
711 INTR_TYPE_MISC | INTR_BRIDGE, filt, intr, sc,
712 &sc->sc_ihand[index]) != 0)
713 panic("%s: failed to set up interrupt %d", __func__, index);
717 psycho_find_intrmap(struct psycho_softc *sc, u_int ino,
718 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr)
720 bus_addr_t intrclr, intrmap;
725 * XXX we only compare INOs rather than INRs since the firmware may
726 * not provide the IGN and the IGN is constant for all devices on
727 * that PCI controller.
728 * This could cause problems for the FFB/external interrupt which
729 * has a full vector that can be set arbitrarily.
732 if (ino > PSYCHO_MAX_INO) {
733 device_printf(sc->sc_dev, "out of range INO %d requested\n",
739 /* Hunt through OBIO first. */
740 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG);
741 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR;
742 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8,
744 if (sc->sc_mode == PSYCHO_MODE_SABRE &&
745 (intrmap == PSR_TIMER0_INT_MAP ||
746 intrmap == PSR_TIMER1_INT_MAP ||
747 intrmap == PSR_PCIBERR_INT_MAP ||
748 intrmap == PSR_PWRMGT_INT_MAP))
750 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) {
758 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG);
759 /* Now do PCI interrupts. */
760 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR;
761 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32,
763 if (sc->sc_mode == PSYCHO_MODE_PSYCHO &&
764 (intrmap == PSR_PCIA2_INT_MAP ||
765 intrmap == PSR_PCIA3_INT_MAP))
767 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) {
768 intrclr += 8 * (ino & 3);
769 diag = (diag >> ((ino & 3) * 2)) & 2;
775 if (intrmapptr != NULL)
776 *intrmapptr = intrmap;
777 if (intrclrptr != NULL)
778 *intrclrptr = intrclr;
779 if (intrdiagptr != NULL)
790 struct psycho_softc *sc = arg;
793 afar = PSYCHO_READ8(sc, PSR_UE_AFA);
794 afsr = PSYCHO_READ8(sc, PSR_UE_AFS);
796 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause
797 * the AFAR to be set to the physical address of the TTE entry that
798 * was invalid/write protected. Call into the IOMMU code to have
799 * them decoded to virtual I/O addresses.
801 if ((afsr & UEAFSR_P_DTE) != 0)
802 iommu_decode_fault(sc->sc_is, afar);
803 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx",
804 device_get_nameunit(sc->sc_dev), (u_long)afar, (u_long)afsr);
805 return (FILTER_HANDLED);
811 struct psycho_softc *sc = arg;
814 mtx_lock_spin(sc->sc_mtx);
815 afar = PSYCHO_READ8(sc, PSR_CE_AFA);
816 afsr = PSYCHO_READ8(sc, PSR_CE_AFS);
817 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx "
818 "AFSR %#lx\n", (u_long)afar, (u_long)afsr);
819 /* Clear the error bits that we caught. */
820 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr);
821 mtx_unlock_spin(sc->sc_mtx);
822 return (FILTER_HANDLED);
826 psycho_pci_bus(void *arg)
828 struct psycho_softc *sc = arg;
831 afar = PCICTL_READ8(sc, PCR_AFA);
832 afsr = PCICTL_READ8(sc, PCR_AFS);
833 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx",
834 device_get_nameunit(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar,
836 return (FILTER_HANDLED);
840 psycho_powerfail(void *arg)
842 #ifdef DEBUGGER_ON_POWERFAIL
843 struct psycho_softc *sc = arg;
845 kdb_enter(KDB_WHY_POWERFAIL, "powerfail");
849 /* As the interrupt is cleared we may be called multiple times. */
851 return (FILTER_HANDLED);
853 printf("Power Failure Detected: Shutting down NOW.\n");
856 return (FILTER_HANDLED);
860 psycho_overtemp(void *arg)
864 /* As the interrupt is cleared we may be called multiple times. */
868 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n");
869 shutdown_nice(RB_POWEROFF);
872 #ifdef PSYCHO_MAP_WAKEUP
874 psycho_wakeup(void *arg)
876 struct psycho_softc *sc = arg;
878 /* We don't really have a framework to deal with this properly. */
879 device_printf(sc->sc_dev, "power management wakeup\n");
880 return (FILTER_HANDLED);
882 #endif /* PSYCHO_MAP_WAKEUP */
885 psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase)
887 struct iommu_state *is = sc->sc_is;
889 /* Punch in our copies. */
890 is->is_bustag = rman_get_bustag(sc->sc_mem_res);
891 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res);
892 is->is_iommu = PSR_IOMMU;
893 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG;
894 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG;
895 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG;
896 is->is_dva = PSR_IOMMU_SVADIAG;
897 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG;
899 iommu_init(device_get_nameunit(sc->sc_dev), is, tsbsize, dvmabase, 0);
903 psycho_maxslots(device_t dev)
906 /* XXX: is this correct? */
907 return (PCI_SLOTMAX);
911 psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
914 struct psycho_softc *sc;
915 bus_space_handle_t bh;
922 sc = device_get_softc(dev);
923 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
924 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
927 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
930 * The Hummingbird and Sabre bridges are picky in that they
931 * only allow their config space to be accessed using the
932 * "native" width of the respective register being accessed
933 * and return semi-random other content of their config space
934 * otherwise. Given that the PCI specs don't say anything
935 * about such a (unusual) limitation and lots of stuff expects
936 * to be able to access the contents of the config space at
937 * any width we allow just that. We do this by using a copy
938 * of the header of the bridge (the rest is all zero anyway)
939 * read during attach (expect for PCIR_STATUS) in order to
941 * The Psycho bridges contain a dupe of their header at 0x80
942 * which we nullify that way also.
944 if (bus == sc->sc_pci_secbus && slot == PCS_DEVICE &&
946 if (offset % width != 0)
949 if (reg >= sizeof(sc->sc_pci_hpbcfg))
952 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) ||
953 reg == PCIR_STATUS || reg == PCIR_STATUS + 1)
954 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS],
955 bus_space_read_2(sc->sc_pci_cfgt, bh,
956 PSYCHO_CONF_OFF(sc->sc_pci_secbus,
957 PCS_DEVICE, PCS_FUNC, PCIR_STATUS)));
961 return (sc->sc_pci_hpbcfg[reg]);
963 return (le16dec(&sc->sc_pci_hpbcfg[reg]));
965 return (le32dec(&sc->sc_pci_hpbcfg[reg]));
969 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
972 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
976 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
980 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
984 panic("%s: bad width", __func__);
990 printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
991 __func__, bus, slot, func, reg);
999 psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func,
1000 u_int reg, uint32_t val, int width)
1002 struct psycho_softc *sc;
1003 bus_space_handle_t bh;
1006 sc = device_get_softc(dev);
1007 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
1008 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
1011 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
1012 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
1015 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
1018 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
1021 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
1024 panic("%s: bad width", __func__);
1030 psycho_route_interrupt(device_t bridge, device_t dev, int pin)
1032 struct psycho_softc *sc;
1033 struct ofw_pci_register reg;
1035 ofw_pci_intr_t pintr, mintr;
1036 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
1038 sc = device_get_softc(bridge);
1040 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
1041 ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
1045 * If this is outside of the range for an intpin, it's likely a full
1046 * INO, and no mapping is required at all; this happens on the U30,
1047 * where there's no interrupt map at the Psycho node. Fortunately,
1048 * there seem to be no INOs in the intpin range on this boxen, so
1049 * this easy heuristics will do.
1054 * Guess the INO; we always assume that this is a non-OBIO
1055 * device, and that pin is a "real" intpin number. Determine
1056 * the mapping register to be used by the slot number.
1057 * We only need to do this on E450s, it seems; here, the slot numbers
1058 * for bus A are one-based, while those for bus B seemingly have an
1059 * offset of 2 (hence the factor of 3 below).
1061 intrmap = PSR_PCIA0_INT_MAP +
1062 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half);
1063 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1;
1064 device_printf(bridge,
1065 "guessing interrupt %d for device %d.%d pin %d\n",
1066 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin);
1071 psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1073 struct psycho_softc *sc;
1075 sc = device_get_softc(dev);
1077 case PCIB_IVAR_DOMAIN:
1078 *result = device_get_unit(dev);
1081 *result = sc->sc_pci_secbus;
1088 sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
1090 struct iommu_state *is = dt->dt_cookie;
1092 if ((map->dm_flags & DMF_LOADED) == 0)
1095 if ((op & BUS_DMASYNC_POSTREAD) != 0)
1096 (void)bus_space_read_8(is->is_bustag, is->is_bushandle,
1097 PSR_DMA_WRITE_SYNC);
1099 if ((op & BUS_DMASYNC_PREWRITE) != 0)
1104 psycho_intr_enable(void *arg)
1106 struct intr_vector *iv = arg;
1107 struct psycho_icarg *pica = iv->iv_icarg;
1109 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map,
1110 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
1114 psycho_intr_disable(void *arg)
1116 struct intr_vector *iv = arg;
1117 struct psycho_icarg *pica = iv->iv_icarg;
1119 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec);
1123 psycho_intr_assign(void *arg)
1125 struct intr_vector *iv = arg;
1126 struct psycho_icarg *pica = iv->iv_icarg;
1128 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, INTMAP_TID(
1129 PSYCHO_READ8(pica->pica_sc, pica->pica_map), iv->iv_mid));
1133 psycho_intr_clear(void *arg)
1135 struct intr_vector *iv = arg;
1136 struct psycho_icarg *pica = iv->iv_icarg;
1138 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, INTCLR_IDLE);
1142 psycho_setup_intr(device_t dev, device_t child, struct resource *ires,
1143 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
1146 struct psycho_softc *sc;
1149 sc = device_get_softc(dev);
1151 * Make sure the vector is fully specified and we registered
1152 * our interrupt controller for it.
1154 vec = rman_get_start(ires);
1155 if (INTIGN(vec) != sc->sc_ign ||
1156 intr_vectors[vec].iv_ic != &psycho_ic) {
1157 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
1160 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
1164 static struct resource *
1165 psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
1166 u_long start, u_long end, u_long count, u_int flags)
1168 struct psycho_softc *sc;
1169 struct resource *rv;
1172 sc = device_get_softc(bus);
1176 * XXX: Don't accept blank ranges for now, only single
1177 * interrupts. The other case should not happen with
1178 * the MI PCI code...
1179 * XXX: This may return a resource that is out of the
1180 * range that was specified. Is this correct...?
1183 panic("%s: XXX: interrupt range", __func__);
1184 start = end = INTMAP_VEC(sc->sc_ign, end);
1185 return (bus_generic_alloc_resource(bus, child, type, rid,
1186 start, end, count, flags));
1187 case SYS_RES_MEMORY:
1188 rm = &sc->sc_pci_mem_rman;
1190 case SYS_RES_IOPORT:
1191 rm = &sc->sc_pci_io_rman;
1197 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE,
1201 rman_set_rid(rv, *rid);
1203 if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child, type,
1205 rman_release_resource(rv);
1212 psycho_activate_resource(device_t bus, device_t child, int type, int rid,
1215 struct psycho_softc *sc;
1216 struct bus_space_tag *tag;
1218 sc = device_get_softc(bus);
1221 return (bus_generic_activate_resource(bus, child, type, rid,
1223 case SYS_RES_MEMORY:
1224 tag = sparc64_alloc_bus_tag(r, rman_get_bustag(
1225 sc->sc_mem_res), PCI_MEMORY_BUS_SPACE, NULL);
1228 rman_set_bustag(r, tag);
1229 rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_MEM32] +
1232 case SYS_RES_IOPORT:
1233 rman_set_bustag(r, sc->sc_pci_iot);
1234 rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_IO] +
1238 return (rman_activate_resource(r));
1242 psycho_adjust_resource(device_t bus, device_t child, int type,
1243 struct resource *r, u_long start, u_long end)
1245 struct psycho_softc *sc;
1248 sc = device_get_softc(bus);
1251 return (bus_generic_adjust_resource(bus, child, type, r,
1253 case SYS_RES_MEMORY:
1254 rm = &sc->sc_pci_mem_rman;
1256 case SYS_RES_IOPORT:
1257 rm = &sc->sc_pci_io_rman;
1262 if (rman_is_region_manager(r, rm) == 0)
1264 return (rman_adjust_resource(r, start, end));
1267 static bus_dma_tag_t
1268 psycho_get_dma_tag(device_t bus, device_t child __unused)
1270 struct psycho_softc *sc;
1272 sc = device_get_softc(bus);
1273 return (sc->sc_pci_dmat);
1277 psycho_get_node(device_t bus, device_t child __unused)
1279 struct psycho_softc *sc;
1281 sc = device_get_softc(bus);
1282 /* We only have one child, the PCI bus, which needs our own node. */
1283 return (sc->sc_node);
1287 psycho_setup_device(device_t bus, device_t child)
1289 struct psycho_softc *sc;
1292 sc = device_get_softc(bus);
1294 * Revision 0 EBus bridges have a bug which prevents them from
1295 * working when bus parking is enabled.
1297 if ((strcmp(ofw_bus_get_name(child), "ebus") == 0 ||
1298 strcmp(ofw_bus_get_name(child), "pci108e,1000") == 0) &&
1299 OF_getprop(ofw_bus_get_node(child), "revision-id", &rev,
1300 sizeof(rev)) > 0 && rev == 0)
1301 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS) &