2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+'
38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges.
41 #include "opt_ofw_pci.h"
42 #include "opt_psycho.h"
44 #include <sys/param.h>
45 #include <sys/systm.h>
47 #include <sys/endian.h>
49 #include <sys/kernel.h>
51 #include <sys/malloc.h>
52 #include <sys/module.h>
53 #include <sys/mutex.h>
55 #include <sys/reboot.h>
58 #include <dev/ofw/ofw_bus.h>
59 #include <dev/ofw/ofw_pci.h>
60 #include <dev/ofw/openfirm.h>
62 #include <machine/bus.h>
63 #include <machine/bus_common.h>
64 #include <machine/bus_private.h>
65 #include <machine/iommureg.h>
66 #include <machine/iommuvar.h>
67 #include <machine/ofw_bus.h>
68 #include <machine/resource.h>
69 #include <machine/ver.h>
71 #include <dev/pci/pcireg.h>
72 #include <dev/pci/pcivar.h>
74 #include <sparc64/pci/ofw_pci.h>
75 #include <sparc64/pci/psychoreg.h>
76 #include <sparc64/pci/psychovar.h>
80 static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *,
82 static const struct psycho_desc *psycho_get_desc(device_t);
83 static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t,
84 driver_filter_t, driver_intr_t);
85 static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *,
86 bus_addr_t *, u_long *);
87 static driver_filter_t psycho_dmasync;
88 static void psycho_intr_enable(void *);
89 static void psycho_intr_disable(void *);
90 static void psycho_intr_assign(void *);
91 static void psycho_intr_clear(void *);
92 static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int);
94 /* Interrupt handlers */
95 static driver_filter_t psycho_ue;
96 static driver_filter_t psycho_ce;
97 static driver_filter_t psycho_pci_bus;
98 static driver_filter_t psycho_powerfail;
99 static driver_intr_t psycho_overtemp;
100 #ifdef PSYCHO_MAP_WAKEUP
101 static driver_filter_t psycho_wakeup;
105 static void psycho_iommu_init(struct psycho_softc *, int, uint32_t);
110 static device_probe_t psycho_probe;
111 static device_attach_t psycho_attach;
112 static bus_read_ivar_t psycho_read_ivar;
113 static bus_setup_intr_t psycho_setup_intr;
114 static bus_teardown_intr_t psycho_teardown_intr;
115 static bus_alloc_resource_t psycho_alloc_resource;
116 static bus_activate_resource_t psycho_activate_resource;
117 static bus_deactivate_resource_t psycho_deactivate_resource;
118 static bus_release_resource_t psycho_release_resource;
119 static bus_get_dma_tag_t psycho_get_dma_tag;
120 static pcib_maxslots_t psycho_maxslots;
121 static pcib_read_config_t psycho_read_config;
122 static pcib_write_config_t psycho_write_config;
123 static pcib_route_interrupt_t psycho_route_interrupt;
124 static ofw_bus_get_node_t psycho_get_node;
126 static device_method_t psycho_methods[] = {
127 /* Device interface */
128 DEVMETHOD(device_probe, psycho_probe),
129 DEVMETHOD(device_attach, psycho_attach),
130 DEVMETHOD(device_shutdown, bus_generic_shutdown),
131 DEVMETHOD(device_suspend, bus_generic_suspend),
132 DEVMETHOD(device_resume, bus_generic_resume),
135 DEVMETHOD(bus_print_child, bus_generic_print_child),
136 DEVMETHOD(bus_read_ivar, psycho_read_ivar),
137 DEVMETHOD(bus_setup_intr, psycho_setup_intr),
138 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr),
139 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource),
140 DEVMETHOD(bus_activate_resource, psycho_activate_resource),
141 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource),
142 DEVMETHOD(bus_release_resource, psycho_release_resource),
143 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag),
146 DEVMETHOD(pcib_maxslots, psycho_maxslots),
147 DEVMETHOD(pcib_read_config, psycho_read_config),
148 DEVMETHOD(pcib_write_config, psycho_write_config),
149 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt),
151 /* ofw_bus interface */
152 DEVMETHOD(ofw_bus_get_node, psycho_get_node),
157 static devclass_t psycho_devclass;
159 DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods,
160 sizeof(struct psycho_softc));
161 DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0);
163 static SLIST_HEAD(, psycho_softc) psycho_softcs =
164 SLIST_HEAD_INITIALIZER(psycho_softcs);
166 static const struct intr_controller psycho_ic = {
173 struct psycho_icarg {
174 struct psycho_softc *pica_sc;
179 struct psycho_dmasync {
180 struct psycho_softc *pds_sc;
181 driver_filter_t *pds_handler; /* handler to call */
182 void *pds_arg; /* argument for the handler */
183 void *pds_cookie; /* parent bus int. cookie */
184 device_t pds_ppb; /* farest PCI-PCI bridge */
185 uint8_t pds_bus; /* bus of farest PCI device */
186 uint8_t pds_slot; /* slot of farest PCI device */
187 uint8_t pds_func; /* func. of farest PCI device */
190 #define PSYCHO_READ8(sc, off) \
191 bus_read_8((sc)->sc_mem_res, (off))
192 #define PSYCHO_WRITE8(sc, off, v) \
193 bus_write_8((sc)->sc_mem_res, (off), (v))
194 #define PCICTL_READ8(sc, off) \
195 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off))
196 #define PCICTL_WRITE8(sc, off, v) \
197 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v))
200 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a
201 * single PCI bus and does not have a streaming buffer. It often has an APB
202 * (advanced PCI bridge) connected to it, which was designed specifically for
203 * the IIi. The APB let's the IIi handle two independednt PCI buses, and
204 * appears as two "Simba"'s underneath the Sabre.
206 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's
207 * basically the same as Sabre but without an APB underneath it.
209 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA bus
210 * and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while
211 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You
212 * will usually find a "Psycho+" since I don't think the original "Psycho"
213 * ever shipped, and if it did it would be in the U30.
215 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are
216 * both part of the same IC, they only have a single register space. As such,
217 * they need to be configured together, even though the autoconfiguration will
218 * attach them separately.
220 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often
221 * as pci1 and pci2, although they have been implemented with other PCI bus
222 * numbers on some machines.
224 * On UltraII machines, there can be any number of "Psycho+" ICs, each
225 * providing two PCI buses.
228 #define OFW_PCI_TYPE "pci"
231 const char *pd_string;
236 static const struct psycho_desc psycho_compats[] = {
237 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" },
238 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" },
239 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" },
243 static const struct psycho_desc psycho_models[] = {
244 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" },
245 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" },
249 static const struct psycho_desc *
250 psycho_find_desc(const struct psycho_desc *table, const char *string)
252 const struct psycho_desc *desc;
256 for (desc = table; desc->pd_string != NULL; desc++)
257 if (strcmp(desc->pd_string, string) == 0)
262 static const struct psycho_desc *
263 psycho_get_desc(device_t dev)
265 const struct psycho_desc *rv;
267 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev));
269 rv = psycho_find_desc(psycho_compats, ofw_bus_get_compat(dev));
274 psycho_probe(device_t dev)
278 dtype = ofw_bus_get_type(dev);
279 if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 &&
280 psycho_get_desc(dev) != NULL) {
281 device_set_desc(dev, "U2P UPA-PCI bridge");
288 psycho_attach(device_t dev)
290 char name[sizeof("pci108e,1000")];
291 struct psycho_icarg *pica;
292 struct psycho_softc *asc, *sc, *osc;
293 struct ofw_pci_ranges *range;
294 const struct psycho_desc *desc;
295 bus_addr_t intrclr, intrmap;
297 phandle_t child, node;
298 uint32_t dvmabase, prop, prop_array[2];
301 int i, n, nrange, rid;
303 node = ofw_bus_get_node(dev);
304 sc = device_get_softc(dev);
305 desc = psycho_get_desc(dev);
309 sc->sc_mode = desc->pd_mode;
312 * The Psycho gets three register banks:
313 * (0) per-PBM configuration and status registers
314 * (1) per-PBM PCI configuration space, containing only the
315 * PBM 256-byte PCI header
316 * (2) the shared Psycho configuration registers
318 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
321 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) -
322 bus_get_resource_start(dev, SYS_RES_MEMORY, 2);
323 switch (sc->sc_pcictl) {
331 panic("%s: bogus PCI control register location",
337 sc->sc_pcictl = PSR_PCICTL0;
340 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
341 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) |
343 if (sc->sc_mem_res == NULL)
344 panic("%s: could not allocate registers", __func__);
347 * Match other Psycho's that are already configured against
348 * the base physical address. This will be the same for a
349 * pair of devices that share register space.
352 SLIST_FOREACH(asc, &psycho_softcs, sc_link) {
353 if (rman_get_start(asc->sc_mem_res) ==
354 rman_get_start(sc->sc_mem_res)) {
361 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF,
363 if (sc->sc_mtx == NULL)
364 panic("%s: could not malloc mutex", __func__);
365 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
367 if (mtx_initialized(osc->sc_mtx) == 0)
368 panic("%s: mutex not initialized", __func__);
369 sc->sc_mtx = osc->sc_mtx;
372 csr = PSYCHO_READ8(sc, PSR_CS);
373 ver = PSYCHO_GCSR_VERS(csr);
374 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */
375 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
376 sc->sc_ign = PSYCHO_GCSR_IGN(csr);
377 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
381 "%s, impl %d, version %d, IGN %#x, bus %c, %dMHz\n",
382 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign,
383 'A' + sc->sc_half, prop / 1000 / 1000);
385 /* Set up the PCI control and PCI diagnostic registers. */
388 * Revision 0 EBus bridges have a bug which prevents them from
389 * working when bus parking is enabled.
392 csr = PCICTL_READ8(sc, PCR_CS);
393 csr &= ~PCICTL_ARB_PARK;
394 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
395 if (OF_getprop(child, "name", name, sizeof(name)) == -1)
397 if ((strcmp(name, "ebus") == 0 ||
398 strcmp(name, "pci108e,1000") == 0) &&
399 OF_getprop(child, "revision-id", &rev, sizeof(rev)) > 0 &&
403 if (rev != 0 && OF_getproplen(node, "no-bus-parking") < 0)
404 csr |= PCICTL_ARB_PARK;
406 /* Workarounds for version specific bugs. */
407 dr = PCICTL_READ8(sc, PCR_DIAG);
411 dr &= ~DIAG_DWSYNC_DIS;
412 /* XXX need to also disable rerun of the streaming buffers. */
415 csr &= ~PCICTL_ARB_PARK;
416 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS;
417 /* XXX need to also disable rerun of the streaming buffers. */
420 dr |= DIAG_DWSYNC_DIS;
421 dr &= ~DIAG_RTRY_DIS;
425 csr |= PCICTL_ERRINTEN | PCICTL_ARB_4;
426 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN);
428 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n",
429 (unsigned long long)PCICTL_READ8(sc, PCR_CS),
430 (unsigned long long)csr);
432 PCICTL_WRITE8(sc, PCR_CS, csr);
434 dr &= ~DIAG_ISYNC_DIS;
436 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
437 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG),
438 (unsigned long long)dr);
440 PCICTL_WRITE8(sc, PCR_DIAG, dr);
442 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
443 /* Use the PROM preset for now. */
444 csr = PCICTL_READ8(sc, PCR_TAS);
446 panic("%s: Hummingbird/Sabre TAS not initialized.",
448 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT;
452 /* Initialize memory and I/O rmans. */
453 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
454 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports";
455 if (rman_init(&sc->sc_pci_io_rman) != 0 ||
456 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0)
457 panic("%s: failed to set up I/O rman", __func__);
458 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
459 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory";
460 if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
461 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0)
462 panic("%s: failed to set up memory rman", __func__);
464 nrange = OF_getprop_alloc(node, "ranges", sizeof(*range),
467 * Make sure that the expected ranges are present. The
468 * OFW_PCI_CS_MEM64 one is not currently used though.
470 if (nrange != PSYCHO_NRANGE)
471 panic("%s: unsupported number of ranges", __func__);
473 * Find the addresses of the various bus spaces.
474 * There should not be multiple ones of one kind.
475 * The physical start addresses of the ranges are the configuration,
476 * memory and I/O handles.
478 for (n = 0; n < PSYCHO_NRANGE; n++) {
479 i = OFW_PCI_RANGE_CS(&range[n]);
480 if (sc->sc_pci_bh[i] != 0)
481 panic("%s: duplicate range for space %d", __func__, i);
482 sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]);
484 free(range, M_OFWPROP);
486 /* Register the softc, this is needed for paired Psychos. */
487 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link);
490 * If we're a Hummingbird/Sabre or the first of a pair of Psychos
491 * to arrive here, do the interrupt setup and start up the IOMMU.
495 * Hunt through all the interrupt mapping regs and register
496 * our interrupt controller for the corresponding interrupt
499 for (n = 0; n <= PSYCHO_MAX_INO; n++) {
500 if (psycho_find_intrmap(sc, n, &intrmap, &intrclr,
503 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT);
505 panic("%s: could not allocate interrupt "
506 "controller argument", __func__);
508 pica->pica_map = intrmap;
509 pica->pica_clr = intrclr;
512 * Enable all interrupts and clear all interrupt
513 * states. This aids the debugging of interrupt
517 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n",
518 n, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO",
519 (u_long)intrmap, (u_long)PSYCHO_READ8(sc, intrmap),
521 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, n));
522 PSYCHO_WRITE8(sc, intrclr, 0);
523 PSYCHO_WRITE8(sc, intrmap,
524 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, n),
527 if (intr_controller_register(INTMAP_VEC(sc->sc_ign, n),
528 &psycho_ic, pica) != 0)
529 panic("%s: could not register interrupt "
530 "controller for INO %d", __func__, n);
533 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
534 /* Initialize the counter-timer. */
535 sparc64_counter_init(device_get_nameunit(dev),
536 rman_get_bustag(sc->sc_mem_res),
537 rman_get_bushandle(sc->sc_mem_res), PSR_TC0);
541 * Set up IOMMU and PCI configuration if we're the first
542 * of a pair of Psycho's to arrive here.
544 * We should calculate a TSB size based on amount of RAM
545 * and number of bus controllers and number and type of
548 * For the moment, 32KB should be more than enough.
550 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF,
552 if (sc->sc_is == NULL)
553 panic("%s: malloc iommu_state failed", __func__);
554 if (sc->sc_mode == PSYCHO_MODE_SABRE)
555 sc->sc_is->is_pmaxaddr =
556 IOMMU_MAXADDR(SABRE_IOMMU_BITS);
558 sc->sc_is->is_pmaxaddr =
559 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS);
560 sc->sc_is->is_sb[0] = 0;
561 sc->sc_is->is_sb[1] = 0;
562 if (OF_getproplen(node, "no-streaming-cache") < 0)
563 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF;
564 psycho_iommu_init(sc, 3, dvmabase);
566 /* Just copy IOMMU state, config tag and address. */
567 sc->sc_is = osc->sc_is;
568 if (OF_getproplen(node, "no-streaming-cache") < 0)
569 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF;
570 iommu_reset(sc->sc_is);
573 /* Allocate our tags. */
574 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE);
575 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE);
576 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE);
577 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
578 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr,
579 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
580 panic("%s: bus_dma_tag_create failed", __func__);
581 /* Customize the tag. */
582 sc->sc_pci_dmat->dt_cookie = sc->sc_is;
583 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods;
585 n = OF_getprop(node, "bus-range", (void *)prop_array,
588 panic("%s: could not get bus-range", __func__);
589 if (n != sizeof(prop_array))
590 panic("%s: broken bus-range (%d)", __func__, n);
592 device_printf(dev, "bus range %u to %u; PCI bus %d\n",
593 prop_array[0], prop_array[1], prop_array[0]);
594 sc->sc_pci_secbus = prop_array[0];
596 /* Clear any pending PCI error bits. */
597 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
598 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus,
599 PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2);
600 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS));
601 PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS));
605 * Establish handlers for interesting interrupts...
607 * XXX We need to remember these and remove this to support
608 * hotplug on the UPA/FHC bus.
610 * XXX Not all controllers have these, but installing them
611 * is better than trying to sort through this mess.
613 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL);
614 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL);
615 #ifdef DEBUGGER_ON_POWERFAIL
616 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail,
619 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL,
620 (driver_intr_t *)psycho_powerfail);
622 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
624 * Hummingbirds/Sabres do not have the following two
629 * The spare hardware interrupt is used for the
630 * over-temperature interrupt.
632 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP,
633 NULL, psycho_overtemp);
634 #ifdef PSYCHO_MAP_WAKEUP
636 * psycho_wakeup() doesn't do anything useful right
639 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP,
640 psycho_wakeup, NULL);
641 #endif /* PSYCHO_MAP_WAKEUP */
645 * Register a PCI bus error interrupt handler according to which
646 * half this is. Hummingbird/Sabre don't have a PCI bus B error
647 * interrupt but they are also only used for PCI bus A.
649 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP :
650 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL);
653 * Set the latency timer register as this isn't always done by the
656 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
657 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
659 for (n = PCIR_VENDOR; n < PCIR_STATUS; n += sizeof(uint16_t))
660 le16enc(&sc->sc_pci_hpbcfg[n], bus_space_read_2(
661 sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG],
662 PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE,
664 for (n = PCIR_REVID; n <= PCIR_BIST; n += sizeof(uint8_t))
665 sc->sc_pci_hpbcfg[n] = bus_space_read_1(sc->sc_pci_cfgt,
666 sc->sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF(
667 sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, n));
669 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
671 * On E250 the interrupt map entry for the EBus bridge is wrong,
672 * causing incorrect interrupts to be assigned to some devices on
673 * the EBus. Work around it by changing our copy of the interrupt
674 * map mask to perform a full comparison of the INO. That way
675 * the interrupt map entry for the EBus bridge won't match at all
676 * and the INOs specified in the "interrupts" properties of the
677 * EBus devices will be used directly instead.
679 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 &&
680 sc->sc_pci_iinfo.opi_imapmsk != NULL)
681 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[
682 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK;
684 device_add_child(dev, "pci", -1);
685 return (bus_generic_attach(dev));
689 psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap,
690 driver_filter_t filt, driver_intr_t intr)
696 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ,
698 if (sc->sc_irq_res[index] == NULL ||
699 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign ||
700 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec ||
701 intr_vectors[vec].iv_ic != &psycho_ic ||
702 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], INTR_TYPE_MISC,
703 filt, intr, sc, &sc->sc_ihand[index]) != 0)
704 panic("%s: failed to set up interrupt %d", __func__, index);
708 psycho_find_intrmap(struct psycho_softc *sc, u_int ino, bus_addr_t *intrmapptr,
709 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr)
711 bus_addr_t intrclr, intrmap;
716 * XXX we only compare INOs rather than INRs since the firmware may
717 * not provide the IGN and the IGN is constant for all devices on
718 * that PCI controller.
719 * This could cause problems for the FFB/external interrupt which
720 * has a full vector that can be set arbitrarily.
723 if (ino > PSYCHO_MAX_INO) {
724 device_printf(sc->sc_dev, "out of range INO %d requested\n",
730 /* Hunt through OBIO first. */
731 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG);
732 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR;
733 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8,
735 if (sc->sc_mode == PSYCHO_MODE_SABRE &&
736 (intrmap == PSR_TIMER0_INT_MAP ||
737 intrmap == PSR_TIMER1_INT_MAP ||
738 intrmap == PSR_PCIBERR_INT_MAP ||
739 intrmap == PSR_PWRMGT_INT_MAP))
741 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) {
749 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG);
750 /* Now do PCI interrupts. */
751 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR;
752 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32,
754 if (sc->sc_mode == PSYCHO_MODE_PSYCHO &&
755 (intrmap == PSR_PCIA2_INT_MAP ||
756 intrmap == PSR_PCIA3_INT_MAP))
758 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) {
759 intrclr += 8 * (ino & 3);
760 diag = (diag >> ((ino & 3) * 2)) & 2;
766 if (intrmapptr != NULL)
767 *intrmapptr = intrmap;
768 if (intrclrptr != NULL)
769 *intrclrptr = intrclr;
770 if (intrdiagptr != NULL)
781 struct psycho_softc *sc = arg;
784 afar = PSYCHO_READ8(sc, PSR_UE_AFA);
785 afsr = PSYCHO_READ8(sc, PSR_UE_AFS);
787 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause
788 * the AFAR to be set to the physical address of the TTE entry that
789 * was invalid/write protected. Call into the IOMMU code to have
790 * them decoded to virtual I/O addresses.
792 if ((afsr & UEAFSR_P_DTE) != 0)
793 iommu_decode_fault(sc->sc_is, afar);
794 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx",
795 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr);
796 return (FILTER_HANDLED);
802 struct psycho_softc *sc = arg;
805 mtx_lock_spin(sc->sc_mtx);
806 afar = PSYCHO_READ8(sc, PSR_CE_AFA);
807 afsr = PSYCHO_READ8(sc, PSR_CE_AFS);
808 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx "
809 "AFSR %#lx\n", (u_long)afar, (u_long)afsr);
810 /* Clear the error bits that we caught. */
811 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr);
812 mtx_unlock_spin(sc->sc_mtx);
813 return (FILTER_HANDLED);
817 psycho_pci_bus(void *arg)
819 struct psycho_softc *sc = arg;
822 afar = PCICTL_READ8(sc, PCR_AFA);
823 afsr = PCICTL_READ8(sc, PCR_AFS);
824 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx",
825 device_get_name(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar,
827 return (FILTER_HANDLED);
831 psycho_powerfail(void *arg)
833 #ifdef DEBUGGER_ON_POWERFAIL
834 struct psycho_softc *sc = arg;
836 kdb_enter(KDB_WHY_POWERFAIL, "powerfail");
840 /* As the interrupt is cleared we may be called multiple times. */
842 return (FILTER_HANDLED);
844 printf("Power Failure Detected: Shutting down NOW.\n");
847 return (FILTER_HANDLED);
851 psycho_overtemp(void *arg)
855 /* As the interrupt is cleared we may be called multiple times. */
859 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n");
860 shutdown_nice(RB_POWEROFF);
863 #ifdef PSYCHO_MAP_WAKEUP
865 psycho_wakeup(void *arg)
867 struct psycho_softc *sc = arg;
869 /* Gee, we don't really have a framework to deal with this properly. */
870 device_printf(sc->sc_dev, "power management wakeup\n");
871 return (FILTER_HANDLED);
873 #endif /* PSYCHO_MAP_WAKEUP */
876 psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase)
878 struct iommu_state *is = sc->sc_is;
880 /* Punch in our copies. */
881 is->is_bustag = rman_get_bustag(sc->sc_mem_res);
882 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res);
883 is->is_iommu = PSR_IOMMU;
884 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG;
885 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG;
886 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG;
887 is->is_dva = PSR_IOMMU_SVADIAG;
888 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG;
890 iommu_init(device_get_nameunit(sc->sc_dev), is, tsbsize, dvmabase, 0);
894 psycho_maxslots(device_t dev)
897 /* XXX: is this correct? */
898 return (PCI_SLOTMAX);
902 psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
905 struct psycho_softc *sc;
906 bus_space_handle_t bh;
913 sc = device_get_softc(dev);
914 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
917 * The Hummingbird and Sabre bridges are picky in that they
918 * only allow their config space to be accessed using the
919 * "native" width of the respective register being accessed
920 * and return semi-random other content of their config space
921 * otherwise. Given that the PCI specs don't say anything
922 * about such a (unusual) limitation and lots of stuff expects
923 * to be able to access the contents of the config space at
924 * any width we allow just that. We do this by using a copy
925 * of the header of the bridge (the rest is all zero anyway)
926 * read during attach (expect for PCIR_STATUS) in order to
928 * The Psycho bridges contain a dupe of their header at 0x80
929 * which we nullify that way also.
931 if (bus == sc->sc_pci_secbus && slot == PCS_DEVICE &&
933 if (offset % width != 0)
936 if (reg >= sizeof(sc->sc_pci_hpbcfg))
939 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) ||
940 reg == PCIR_STATUS || reg == PCIR_STATUS + 1)
941 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS],
942 bus_space_read_2(sc->sc_pci_cfgt, bh,
943 PSYCHO_CONF_OFF(sc->sc_pci_secbus,
944 PCS_DEVICE, PCS_FUNC, PCIR_STATUS)));
948 return (sc->sc_pci_hpbcfg[reg]);
950 return (le16dec(&sc->sc_pci_hpbcfg[reg]));
952 return (le32dec(&sc->sc_pci_hpbcfg[reg]));
956 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
959 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
963 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
967 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
971 panic("%s: bad width", __func__);
977 printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
978 __func__, bus, slot, func, reg);
986 psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
987 uint32_t val, int width)
989 struct psycho_softc *sc;
990 bus_space_handle_t bh;
993 sc = device_get_softc(dev);
994 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
995 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
998 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
1001 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
1004 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
1007 panic("%s: bad width", __func__);
1013 psycho_route_interrupt(device_t bridge, device_t dev, int pin)
1015 struct psycho_softc *sc;
1016 struct ofw_pci_register reg;
1018 ofw_pci_intr_t pintr, mintr;
1019 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
1021 sc = device_get_softc(bridge);
1023 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®,
1024 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf))
1027 * If this is outside of the range for an intpin, it's likely a full
1028 * INO, and no mapping is required at all; this happens on the U30,
1029 * where there's no interrupt map at the Psycho node. Fortunately,
1030 * there seem to be no INOs in the intpin range on this boxen, so
1031 * this easy heuristics will do.
1036 * Guess the INO; we always assume that this is a non-OBIO
1037 * device, and that pin is a "real" intpin number. Determine
1038 * the mapping register to be used by the slot number.
1039 * We only need to do this on E450s, it seems; here, the slot numbers
1040 * for bus A are one-based, while those for bus B seemingly have an
1041 * offset of 2 (hence the factor of 3 below).
1043 intrmap = PSR_PCIA0_INT_MAP +
1044 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half);
1045 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1;
1046 device_printf(bridge, "guessing interrupt %d for device %d.%d pin %d\n",
1047 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin);
1052 psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1054 struct psycho_softc *sc;
1056 sc = device_get_softc(dev);
1058 case PCIB_IVAR_DOMAIN:
1059 *result = device_get_unit(dev);
1062 *result = sc->sc_pci_secbus;
1069 psycho_dmasync(void *arg)
1071 struct psycho_dmasync *pds = arg;
1073 (void)PCIB_READ_CONFIG(pds->pds_ppb, pds->pds_bus, pds->pds_slot,
1074 pds->pds_func, PCIR_VENDOR, 2);
1075 (void)PSYCHO_READ8(pds->pds_sc, PSR_DMA_WRITE_SYNC);
1076 return (pds->pds_handler(pds->pds_arg));
1080 psycho_intr_enable(void *arg)
1082 struct intr_vector *iv = arg;
1083 struct psycho_icarg *pica = iv->iv_icarg;
1085 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map,
1086 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
1090 psycho_intr_disable(void *arg)
1092 struct intr_vector *iv = arg;
1093 struct psycho_icarg *pica = iv->iv_icarg;
1095 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec);
1099 psycho_intr_assign(void *arg)
1101 struct intr_vector *iv = arg;
1102 struct psycho_icarg *pica = iv->iv_icarg;
1104 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, INTMAP_TID(
1105 PSYCHO_READ8(pica->pica_sc, pica->pica_map), iv->iv_mid));
1109 psycho_intr_clear(void *arg)
1111 struct intr_vector *iv = arg;
1112 struct psycho_icarg *pica = iv->iv_icarg;
1114 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, 0);
1118 psycho_setup_intr(device_t dev, device_t child, struct resource *ires,
1119 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
1126 devclass_t pci_devclass;
1127 device_t cdev, pdev, pcidev;
1128 struct psycho_softc *sc;
1129 struct psycho_dmasync *pds;
1133 sc = device_get_softc(dev);
1135 * Make sure the vector is fully specified and we registered
1136 * our interrupt controller for it.
1138 vec = rman_get_start(ires);
1139 if (INTIGN(vec) != sc->sc_ign ||
1140 intr_vectors[vec].iv_ic != &psycho_ic) {
1141 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
1146 * The Sabre-APB-combination has a bug where it does not drain
1147 * DMA write data for devices behind additional PCI-PCI bridges
1148 * underneath the APB PCI-PCI bridge. The workaround is to do
1149 * a read on the farest PCI-PCI bridge followed by a read of the
1150 * PCI DMA write sync register of the Sabre.
1151 * XXX installing the wrapper for an affected device and the
1152 * actual workaround in psycho_dmasync() should be moved to
1153 * psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync()
1154 * methods, respectively, once DMA tag creation is newbus'ified,
1155 * so the workaround isn't only applied for interrupt handlers
1156 * but also for polling(4) callbacks.
1158 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
1159 pds = malloc(sizeof(*pds), M_DEVBUF, M_NOWAIT | M_ZERO);
1163 found.apb = found.ppb = 0;
1164 pci_devclass = devclass_find("pci");
1165 for (cdev = child; cdev != dev; cdev = pdev) {
1166 pdev = device_get_parent(cdev);
1167 if (pcidev == NULL) {
1168 if (device_get_devclass(pdev) != pci_devclass)
1174 * NB: APB would also match as PCI-PCI bridges.
1176 if (pci_get_vendor(cdev) == 0x108e &&
1177 pci_get_device(cdev) == 0x5000) {
1181 if (pci_get_class(cdev) == PCIC_BRIDGE &&
1182 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI)
1185 if (found.apb && found.ppb && pcidev != NULL) {
1189 device_get_parent(device_get_parent(pcidev));
1190 pds->pds_bus = pci_get_bus(pcidev);
1191 pds->pds_slot = pci_get_slot(pcidev);
1192 pds->pds_func = pci_get_function(pcidev);
1194 device_printf(dev, "installed DMA sync "
1195 "workaround for device %d.%d on bus %d\n",
1196 pds->pds_slot, pds->pds_func,
1199 pds->pds_handler = filt;
1200 error = bus_generic_setup_intr(dev, child,
1201 ires, flags, psycho_dmasync, intr, pds,
1204 pds->pds_handler = (driver_filter_t *)intr;
1205 error = bus_generic_setup_intr(dev, child,
1207 (driver_intr_t *)psycho_dmasync, pds,
1211 error = bus_generic_setup_intr(dev, child, ires,
1212 flags, filt, intr, arg, cookiep);
1214 free(pds, M_DEVBUF);
1217 pds->pds_cookie = *cookiep;
1221 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
1226 psycho_teardown_intr(device_t dev, device_t child, struct resource *vec,
1229 struct psycho_softc *sc;
1230 struct psycho_dmasync *pds;
1233 sc = device_get_softc(dev);
1234 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
1236 error = bus_generic_teardown_intr(dev, child, vec,
1239 free(pds, M_DEVBUF);
1242 return (bus_generic_teardown_intr(dev, child, vec, cookie));
1245 static struct resource *
1246 psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
1247 u_long start, u_long end, u_long count, u_int flags)
1249 struct psycho_softc *sc;
1250 struct resource *rv;
1253 bus_space_handle_t bh;
1254 int needactivate = flags & RF_ACTIVE;
1256 flags &= ~RF_ACTIVE;
1258 sc = device_get_softc(bus);
1259 if (type == SYS_RES_IRQ) {
1261 * XXX: Don't accept blank ranges for now, only single
1262 * interrupts. The other case should not happen with
1263 * the MI PCI code...
1264 * XXX: This may return a resource that is out of the
1265 * range that was specified. Is this correct...?
1268 panic("%s: XXX: interrupt range", __func__);
1269 start = end = INTMAP_VEC(sc->sc_ign, end);
1270 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type,
1271 rid, start, end, count, flags));
1274 case SYS_RES_MEMORY:
1275 rm = &sc->sc_pci_mem_rman;
1276 bt = sc->sc_pci_memt;
1277 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32];
1279 case SYS_RES_IOPORT:
1280 rm = &sc->sc_pci_io_rman;
1281 bt = sc->sc_pci_iot;
1282 bh = sc->sc_pci_bh[OFW_PCI_CS_IO];
1289 rv = rman_reserve_resource(rm, start, end, count, flags, child);
1292 rman_set_rid(rv, *rid);
1293 bh += rman_get_start(rv);
1294 rman_set_bustag(rv, bt);
1295 rman_set_bushandle(rv, bh);
1298 if (bus_activate_resource(child, type, *rid, rv)) {
1299 rman_release_resource(rv);
1307 psycho_activate_resource(device_t bus, device_t child, int type, int rid,
1313 if (type == SYS_RES_IRQ)
1314 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child,
1316 if (type == SYS_RES_MEMORY) {
1318 * Need to memory-map the device space, as some drivers depend
1319 * on the virtual address being set and useable.
1321 error = sparc64_bus_mem_map(rman_get_bustag(r),
1322 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p);
1325 rman_set_virtual(r, p);
1327 return (rman_activate_resource(r));
1331 psycho_deactivate_resource(device_t bus, device_t child, int type, int rid,
1335 if (type == SYS_RES_IRQ)
1336 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child,
1338 if (type == SYS_RES_MEMORY) {
1339 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r));
1340 rman_set_virtual(r, NULL);
1342 return (rman_deactivate_resource(r));
1346 psycho_release_resource(device_t bus, device_t child, int type, int rid,
1351 if (type == SYS_RES_IRQ)
1352 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child,
1354 if (rman_get_flags(r) & RF_ACTIVE) {
1355 error = bus_deactivate_resource(child, type, rid, r);
1359 return (rman_release_resource(r));
1362 static bus_dma_tag_t
1363 psycho_get_dma_tag(device_t bus, device_t child)
1365 struct psycho_softc *sc;
1367 sc = device_get_softc(bus);
1368 return (sc->sc_pci_dmat);
1372 psycho_get_node(device_t bus, device_t dev)
1374 struct psycho_softc *sc;
1376 sc = device_get_softc(bus);
1377 /* We only have one child, the PCI bus, which needs our own node. */
1378 return (sc->sc_node);
1381 static bus_space_tag_t
1382 psycho_alloc_bus_tag(struct psycho_softc *sc, int type)
1386 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, M_NOWAIT | M_ZERO);
1388 panic("%s: out of memory", __func__);
1390 bt->bst_cookie = sc;
1391 bt->bst_parent = rman_get_bustag(sc->sc_mem_res);
1392 bt->bst_type = type;