2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+'
38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges.
41 #include "opt_ofw_pci.h"
42 #include "opt_psycho.h"
44 #include <sys/param.h>
45 #include <sys/systm.h>
47 #include <sys/endian.h>
49 #include <sys/kernel.h>
51 #include <sys/malloc.h>
52 #include <sys/module.h>
53 #include <sys/mutex.h>
55 #include <sys/reboot.h>
57 #include <sys/sysctl.h>
59 #include <dev/ofw/ofw_bus.h>
60 #include <dev/ofw/openfirm.h>
62 #include <machine/bus.h>
63 #include <machine/bus_common.h>
64 #include <machine/bus_private.h>
65 #include <machine/iommureg.h>
66 #include <machine/iommuvar.h>
67 #include <machine/resource.h>
68 #include <machine/ver.h>
70 #include <dev/pci/pcireg.h>
71 #include <dev/pci/pcivar.h>
72 #include <dev/pci/pcib_private.h>
74 #include <sparc64/pci/ofw_pci.h>
75 #include <sparc64/pci/psychoreg.h>
76 #include <sparc64/pci/psychovar.h>
80 static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *,
82 static const struct psycho_desc *psycho_get_desc(device_t);
83 static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t,
84 driver_filter_t, driver_intr_t);
85 static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *,
86 bus_addr_t *, u_long *);
87 static void sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map,
89 static void psycho_intr_enable(void *);
90 static void psycho_intr_disable(void *);
91 static void psycho_intr_assign(void *);
92 static void psycho_intr_clear(void *);
94 /* Interrupt handlers */
95 static driver_filter_t psycho_ue;
96 static driver_filter_t psycho_ce;
97 static driver_filter_t psycho_pci_bus;
98 static driver_filter_t psycho_powerdebug;
99 static driver_intr_t psycho_powerdown;
100 static driver_intr_t psycho_overtemp;
101 #ifdef PSYCHO_MAP_WAKEUP
102 static driver_filter_t psycho_wakeup;
106 static void psycho_iommu_init(struct psycho_softc *, int, uint32_t);
111 static device_probe_t psycho_probe;
112 static device_attach_t psycho_attach;
113 static bus_setup_intr_t psycho_setup_intr;
114 static bus_alloc_resource_t psycho_alloc_resource;
115 static pcib_maxslots_t psycho_maxslots;
116 static pcib_read_config_t psycho_read_config;
117 static pcib_write_config_t psycho_write_config;
118 static pcib_route_interrupt_t psycho_route_interrupt;
119 static ofw_pci_setup_device_t psycho_setup_device;
121 static device_method_t psycho_methods[] = {
122 /* Device interface */
123 DEVMETHOD(device_probe, psycho_probe),
124 DEVMETHOD(device_attach, psycho_attach),
125 DEVMETHOD(device_shutdown, bus_generic_shutdown),
126 DEVMETHOD(device_suspend, bus_generic_suspend),
127 DEVMETHOD(device_resume, bus_generic_resume),
130 DEVMETHOD(bus_read_ivar, ofw_pci_read_ivar),
131 DEVMETHOD(bus_setup_intr, psycho_setup_intr),
132 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
133 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource),
134 DEVMETHOD(bus_activate_resource, ofw_pci_activate_resource),
135 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
136 DEVMETHOD(bus_adjust_resource, ofw_pci_adjust_resource),
137 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
138 DEVMETHOD(bus_get_dma_tag, ofw_pci_get_dma_tag),
141 DEVMETHOD(pcib_maxslots, psycho_maxslots),
142 DEVMETHOD(pcib_read_config, psycho_read_config),
143 DEVMETHOD(pcib_write_config, psycho_write_config),
144 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt),
145 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
147 /* ofw_bus interface */
148 DEVMETHOD(ofw_bus_get_node, ofw_pci_get_node),
150 /* ofw_pci interface */
151 DEVMETHOD(ofw_pci_setup_device, psycho_setup_device),
156 static devclass_t psycho_devclass;
158 DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods,
159 sizeof(struct psycho_softc));
160 EARLY_DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, NULL, NULL,
163 static SYSCTL_NODE(_hw, OID_AUTO, psycho, CTLFLAG_RD, 0, "psycho parameters");
165 static u_int psycho_powerfail = 1;
166 SYSCTL_UINT(_hw_psycho, OID_AUTO, powerfail, CTLFLAG_RDTUN, &psycho_powerfail,
167 0, "powerfail action (0: none, 1: shutdown (default), 2: debugger)");
169 static SLIST_HEAD(, psycho_softc) psycho_softcs =
170 SLIST_HEAD_INITIALIZER(psycho_softcs);
172 static const struct intr_controller psycho_ic = {
179 struct psycho_icarg {
180 struct psycho_softc *pica_sc;
185 #define PSYCHO_READ8(sc, off) \
186 bus_read_8((sc)->sc_mem_res, (off))
187 #define PSYCHO_WRITE8(sc, off, v) \
188 bus_write_8((sc)->sc_mem_res, (off), (v))
189 #define PCICTL_READ8(sc, off) \
190 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off))
191 #define PCICTL_WRITE8(sc, off, v) \
192 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v))
195 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a
196 * single PCI bus and does not have a streaming buffer. It often has an APB
197 * (advanced PCI bridge) connected to it, which was designed specifically for
198 * the IIi. The APB lets the IIi handle two independent PCI buses, and
199 * appears as two "Simba"'s underneath the Sabre.
201 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's
202 * basically the same as Sabre but without an APB underneath it.
204 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA
205 * bus and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while
206 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You
207 * will usually find a "Psycho+" since I don't think the original "Psycho"
208 * ever shipped, and if it did it would be in the U30.
210 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are
211 * both part of the same IC, they only have a single register space. As such,
212 * they need to be configured together, even though the autoconfiguration will
213 * attach them separately.
215 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often
216 * as pci1 and pci2, although they have been implemented with other PCI bus
217 * numbers on some machines.
219 * On UltraII machines, there can be any number of "Psycho+" ICs, each
220 * providing two PCI buses.
224 const char *pd_string;
229 static const struct psycho_desc psycho_compats[] = {
230 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" },
231 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" },
232 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" },
236 static const struct psycho_desc psycho_models[] = {
237 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" },
238 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" },
242 static const struct psycho_desc *
243 psycho_find_desc(const struct psycho_desc *table, const char *string)
245 const struct psycho_desc *desc;
249 for (desc = table; desc->pd_string != NULL; desc++)
250 if (strcmp(desc->pd_string, string) == 0)
255 static const struct psycho_desc *
256 psycho_get_desc(device_t dev)
258 const struct psycho_desc *rv;
260 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev));
262 rv = psycho_find_desc(psycho_compats,
263 ofw_bus_get_compat(dev));
268 psycho_probe(device_t dev)
272 dtype = ofw_bus_get_type(dev);
273 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 &&
274 psycho_get_desc(dev) != NULL) {
275 device_set_desc(dev, "U2P UPA-PCI bridge");
282 psycho_attach(device_t dev)
284 struct psycho_icarg *pica;
285 struct psycho_softc *asc, *sc, *osc;
286 const struct psycho_desc *desc;
287 bus_addr_t intrclr, intrmap;
291 uint32_t dvmabase, prop;
295 node = ofw_bus_get_node(dev);
296 sc = device_get_softc(dev);
297 desc = psycho_get_desc(dev);
300 sc->sc_mode = desc->pd_mode;
303 * The Psycho gets three register banks:
304 * (0) per-PBM configuration and status registers
305 * (1) per-PBM PCI configuration space, containing only the
306 * PBM 256-byte PCI header
307 * (2) the shared Psycho configuration registers
309 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
312 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) -
313 bus_get_resource_start(dev, SYS_RES_MEMORY, 2);
314 switch (sc->sc_pcictl) {
322 panic("%s: bogus PCI control register location",
328 sc->sc_pcictl = PSR_PCICTL0;
331 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i,
332 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) |
334 if (sc->sc_mem_res == NULL)
335 panic("%s: could not allocate registers", __func__);
338 * Match other Psychos that are already configured against
339 * the base physical address. This will be the same for a
340 * pair of devices that share register space.
343 SLIST_FOREACH(asc, &psycho_softcs, sc_link) {
344 if (rman_get_start(asc->sc_mem_res) ==
345 rman_get_start(sc->sc_mem_res)) {
352 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF,
354 if (sc->sc_mtx == NULL)
355 panic("%s: could not malloc mutex", __func__);
356 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
358 if (sc->sc_mode != PSYCHO_MODE_PSYCHO)
359 panic("%s: no partner expected", __func__);
360 if (mtx_initialized(osc->sc_mtx) == 0)
361 panic("%s: mutex not initialized", __func__);
362 sc->sc_mtx = osc->sc_mtx;
364 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link);
366 csr = PSYCHO_READ8(sc, PSR_CS);
367 ver = PSYCHO_GCSR_VERS(csr);
368 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */
369 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
370 sc->sc_ign = PSYCHO_GCSR_IGN(csr);
371 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
375 "%s, impl %d, version %d, IGN %#x, bus %c, %dMHz\n",
376 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign,
377 'A' + sc->sc_half, prop / 1000 / 1000);
379 /* Set up the PCI control and PCI diagnostic registers. */
381 csr = PCICTL_READ8(sc, PCR_CS);
382 csr &= ~PCICTL_ARB_PARK;
383 if (OF_getproplen(node, "no-bus-parking") < 0)
384 csr |= PCICTL_ARB_PARK;
386 /* Workarounds for version specific bugs. */
387 dr = PCICTL_READ8(sc, PCR_DIAG);
391 dr &= ~DIAG_DWSYNC_DIS;
395 csr &= ~PCICTL_ARB_PARK;
396 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS;
400 dr |= DIAG_DWSYNC_DIS;
401 dr &= ~DIAG_RTRY_DIS;
406 csr |= PCICTL_ERRINTEN | PCICTL_ARB_4;
407 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN);
409 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n",
410 (unsigned long long)PCICTL_READ8(sc, PCR_CS),
411 (unsigned long long)csr);
413 PCICTL_WRITE8(sc, PCR_CS, csr);
415 dr &= ~DIAG_ISYNC_DIS;
417 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
418 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG),
419 (unsigned long long)dr);
421 PCICTL_WRITE8(sc, PCR_DIAG, dr);
423 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
424 /* Use the PROM preset for now. */
425 csr = PCICTL_READ8(sc, PCR_TAS);
427 panic("%s: Hummingbird/Sabre TAS not initialized.",
429 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT;
434 * If we're a Hummingbird/Sabre or the first of a pair of Psychos
435 * to arrive here, do the interrupt setup and start up the IOMMU.
439 * Hunt through all the interrupt mapping regs and register
440 * our interrupt controller for the corresponding interrupt
441 * vectors. We do this early in order to be able to catch
444 for (i = 0; i <= PSYCHO_MAX_INO; i++) {
445 if (psycho_find_intrmap(sc, i, &intrmap, &intrclr,
448 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT);
450 panic("%s: could not allocate interrupt "
451 "controller argument", __func__);
453 pica->pica_map = intrmap;
454 pica->pica_clr = intrclr;
457 * Enable all interrupts and clear all interrupt
458 * states. This aids the debugging of interrupt
462 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n",
463 i, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO",
464 (u_long)intrmap, (u_long)PSYCHO_READ8(sc,
465 intrmap), (u_long)intrclr);
466 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, i));
467 PSYCHO_WRITE8(sc, intrclr, INTCLR_IDLE);
468 PSYCHO_WRITE8(sc, intrmap,
469 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, i),
472 j = intr_controller_register(INTMAP_VEC(sc->sc_ign,
473 i), &psycho_ic, pica);
475 device_printf(dev, "could not register "
476 "interrupt controller for INO %d (%d)\n",
480 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
481 sparc64_counter_init(device_get_nameunit(dev),
482 rman_get_bustag(sc->sc_mem_res),
483 rman_get_bushandle(sc->sc_mem_res), PSR_TC0);
486 * Set up IOMMU and PCI configuration if we're the first
487 * of a pair of Psychos to arrive here or a Hummingbird
490 * We should calculate a TSB size based on amount of RAM
491 * and number of bus controllers and number and type of
494 * For the moment, 32KB should be more than enough.
496 sc->sc_is = malloc(sizeof(*sc->sc_is), M_DEVBUF, M_NOWAIT |
498 if (sc->sc_is == NULL)
499 panic("%s: could not malloc IOMMU state", __func__);
500 sc->sc_is->is_flags = IOMMU_PRESERVE_PROM;
501 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
503 malloc(sizeof(*sc->sc_dma_methods), M_DEVBUF,
505 if (sc->sc_dma_methods == NULL)
506 panic("%s: could not malloc DMA methods",
508 memcpy(sc->sc_dma_methods, &iommu_dma_methods,
509 sizeof(*sc->sc_dma_methods));
510 sc->sc_dma_methods->dm_dmamap_sync =
512 sc->sc_is->is_pmaxaddr =
513 IOMMU_MAXADDR(SABRE_IOMMU_BITS);
515 sc->sc_dma_methods = &iommu_dma_methods;
516 sc->sc_is->is_pmaxaddr =
517 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS);
519 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = 0;
520 if (OF_getproplen(node, "no-streaming-cache") < 0)
521 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF;
522 sc->sc_is->is_flags |= (rerun != 1) ? IOMMU_RERUN_DISABLE : 0;
523 psycho_iommu_init(sc, 3, dvmabase);
525 /* Just copy IOMMU state, config tag and address. */
526 sc->sc_dma_methods = &iommu_dma_methods;
527 sc->sc_is = osc->sc_is;
528 if (OF_getproplen(node, "no-streaming-cache") < 0)
529 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF;
530 iommu_reset(sc->sc_is);
533 /* Create our DMA tag. */
534 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
535 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr,
536 0xff, 0xffffffff, 0, NULL, NULL, &dmat) != 0)
537 panic("%s: could not create PCI DMA tag", __func__);
538 dmat->dt_cookie = sc->sc_is;
539 dmat->dt_mt = sc->sc_dma_methods;
541 if (ofw_pci_attach_common(dev, dmat, PSYCHO_IO_SIZE,
542 PSYCHO_MEM_SIZE) != 0)
543 panic("%s: ofw_pci_attach_common() failed", __func__);
545 /* Clear any pending PCI error bits. */
546 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
547 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_ops.sc_pci_secbus,
548 PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2);
549 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS));
550 PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS));
554 * Establish handlers for interesting interrupts...
556 * XXX We need to remember these and remove this to support
557 * hotplug on the UPA/FHC bus.
559 * XXX Not all controllers have these, but installing them
560 * is better than trying to sort through this mess.
562 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL);
563 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL);
564 switch (psycho_powerfail) {
568 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP,
569 psycho_powerdebug, NULL);
572 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL,
576 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
578 * Hummingbirds/Sabres do not have the following two
583 * The spare hardware interrupt is used for the
584 * over-temperature interrupt.
586 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, NULL,
588 #ifdef PSYCHO_MAP_WAKEUP
590 * psycho_wakeup() doesn't do anything useful right
593 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP,
594 psycho_wakeup, NULL);
595 #endif /* PSYCHO_MAP_WAKEUP */
599 * Register a PCI bus error interrupt handler according to which
600 * half this is. Hummingbird/Sabre don't have a PCI bus B error
601 * interrupt but they are also only used for PCI bus A.
603 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP :
604 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL);
607 * Set the latency timer register as this isn't always done by the
610 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
611 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
613 for (i = PCIR_VENDOR; i < PCIR_STATUS; i += sizeof(uint16_t))
614 le16enc(&sc->sc_pci_hpbcfg[i],
615 bus_space_read_2(sc->sc_ops.sc_pci_cfgt,
616 sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG],
617 PSYCHO_CONF_OFF(sc->sc_ops.sc_pci_secbus, PCS_DEVICE,
619 for (i = PCIR_REVID; i <= PCIR_BIST; i += sizeof(uint8_t))
620 sc->sc_pci_hpbcfg[i] = bus_space_read_1(sc->sc_ops.sc_pci_cfgt,
621 sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF(
622 sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC, i));
625 * On E250 the interrupt map entry for the EBus bridge is wrong,
626 * causing incorrect interrupts to be assigned to some devices on
627 * the EBus. Work around it by changing our copy of the interrupt
628 * map mask to perform a full comparison of the INO. That way
629 * the interrupt map entry for the EBus bridge won't match at all
630 * and the INOs specified in the "interrupts" properties of the
631 * EBus devices will be used directly instead.
633 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 &&
634 sc->sc_ops.sc_pci_iinfo.opi_imapmsk != NULL)
635 *(ofw_pci_intr_t *)(&sc->sc_ops.sc_pci_iinfo.opi_imapmsk[
636 sc->sc_ops.sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK;
638 device_add_child(dev, "pci", -1);
639 return (bus_generic_attach(dev));
643 psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap,
644 driver_filter_t filt, driver_intr_t intr)
650 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev,
651 SYS_RES_IRQ, &rid, RF_ACTIVE);
652 if (sc->sc_irq_res[index] == NULL && intrmap >= PSR_POWER_INT_MAP) {
654 * These interrupts aren't mandatory and not available
655 * with all controllers (not even Psychos).
659 if (sc->sc_irq_res[index] == NULL ||
660 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) !=
662 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec ||
663 intr_vectors[vec].iv_ic != &psycho_ic ||
664 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index],
665 INTR_TYPE_MISC | INTR_BRIDGE, filt, intr, sc,
666 &sc->sc_ihand[index]) != 0)
667 panic("%s: failed to set up interrupt %d", __func__, index);
671 psycho_find_intrmap(struct psycho_softc *sc, u_int ino,
672 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr)
674 bus_addr_t intrclr, intrmap;
679 * XXX we only compare INOs rather than INRs since the firmware may
680 * not provide the IGN and the IGN is constant for all devices on
681 * that PCI controller.
682 * This could cause problems for the FFB/external interrupt which
683 * has a full vector that can be set arbitrarily.
686 if (ino > PSYCHO_MAX_INO) {
687 device_printf(sc->sc_dev, "out of range INO %d requested\n",
693 /* Hunt through OBIO first. */
694 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG);
695 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR;
696 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8,
698 if (sc->sc_mode == PSYCHO_MODE_SABRE &&
699 (intrmap == PSR_TIMER0_INT_MAP ||
700 intrmap == PSR_TIMER1_INT_MAP ||
701 intrmap == PSR_PCIBERR_INT_MAP ||
702 intrmap == PSR_PWRMGT_INT_MAP))
704 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) {
712 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG);
713 /* Now do PCI interrupts. */
714 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR;
715 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32,
717 if (sc->sc_mode == PSYCHO_MODE_PSYCHO &&
718 (intrmap == PSR_PCIA2_INT_MAP ||
719 intrmap == PSR_PCIA3_INT_MAP))
721 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) {
722 intrclr += 8 * (ino & 3);
723 diag = (diag >> ((ino & 3) * 2)) & 2;
729 if (intrmapptr != NULL)
730 *intrmapptr = intrmap;
731 if (intrclrptr != NULL)
732 *intrclrptr = intrclr;
733 if (intrdiagptr != NULL)
744 struct psycho_softc *sc = arg;
747 afar = PSYCHO_READ8(sc, PSR_UE_AFA);
748 afsr = PSYCHO_READ8(sc, PSR_UE_AFS);
750 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause
751 * the AFAR to be set to the physical address of the TTE entry that
752 * was invalid/write protected. Call into the IOMMU code to have
753 * them decoded to virtual I/O addresses.
755 if ((afsr & UEAFSR_P_DTE) != 0)
756 iommu_decode_fault(sc->sc_is, afar);
757 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx",
758 device_get_nameunit(sc->sc_dev), (u_long)afar, (u_long)afsr);
759 return (FILTER_HANDLED);
765 struct psycho_softc *sc = arg;
768 mtx_lock_spin(sc->sc_mtx);
769 afar = PSYCHO_READ8(sc, PSR_CE_AFA);
770 afsr = PSYCHO_READ8(sc, PSR_CE_AFS);
771 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx "
772 "AFSR %#lx\n", (u_long)afar, (u_long)afsr);
773 /* Clear the error bits that we caught. */
774 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr);
775 mtx_unlock_spin(sc->sc_mtx);
776 return (FILTER_HANDLED);
780 psycho_pci_bus(void *arg)
782 struct psycho_softc *sc = arg;
785 afar = PCICTL_READ8(sc, PCR_AFA);
786 afsr = PCICTL_READ8(sc, PCR_AFS);
787 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx",
788 device_get_nameunit(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar,
790 return (FILTER_HANDLED);
794 psycho_powerdebug(void *arg __unused)
797 kdb_enter(KDB_WHY_POWERFAIL, "powerfail");
798 return (FILTER_HANDLED);
802 psycho_powerdown(void *arg __unused)
806 /* As the interrupt is cleared we may be called multiple times. */
810 printf("Power Failure Detected: Shutting down NOW.\n");
811 shutdown_nice(RB_POWEROFF);
815 psycho_overtemp(void *arg __unused)
819 /* As the interrupt is cleared we may be called multiple times. */
823 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n");
824 shutdown_nice(RB_POWEROFF);
827 #ifdef PSYCHO_MAP_WAKEUP
829 psycho_wakeup(void *arg)
831 struct psycho_softc *sc = arg;
833 /* We don't really have a framework to deal with this properly. */
834 device_printf(sc->sc_dev, "power management wakeup\n");
835 return (FILTER_HANDLED);
837 #endif /* PSYCHO_MAP_WAKEUP */
840 psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase)
842 struct iommu_state *is = sc->sc_is;
844 /* Punch in our copies. */
845 is->is_bustag = rman_get_bustag(sc->sc_mem_res);
846 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res);
847 is->is_iommu = PSR_IOMMU;
848 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG;
849 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG;
850 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG;
851 is->is_dva = PSR_IOMMU_SVADIAG;
852 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG;
854 iommu_init(device_get_nameunit(sc->sc_dev), is, tsbsize, dvmabase, 0);
858 psycho_maxslots(device_t dev)
861 /* XXX: is this correct? */
862 return (PCI_SLOTMAX);
866 psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
869 struct psycho_softc *sc;
871 sc = device_get_softc(dev);
873 * The Hummingbird and Sabre bridges are picky in that they
874 * only allow their config space to be accessed using the
875 * "native" width of the respective register being accessed
876 * and return semi-random other content of their config space
877 * otherwise. Given that the PCI specs don't say anything
878 * about such a (unusual) limitation and lots of stuff expects
879 * to be able to access the contents of the config space at
880 * any width we allow just that. We do this by using a copy
881 * of the header of the bridge (the rest is all zero anyway)
882 * read during attach (expect for PCIR_STATUS) in order to
884 * The Psycho bridges contain a dupe of their header at 0x80
885 * which we nullify that way also.
887 if (bus == sc->sc_ops.sc_pci_secbus && slot == PCS_DEVICE &&
889 if (reg % width != 0)
892 if (reg >= sizeof(sc->sc_pci_hpbcfg))
895 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) ||
896 reg == PCIR_STATUS || reg == PCIR_STATUS + 1)
897 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS],
898 bus_space_read_2(sc->sc_ops.sc_pci_cfgt,
899 sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG],
900 PSYCHO_CONF_OFF(sc->sc_ops.sc_pci_secbus,
901 PCS_DEVICE, PCS_FUNC, PCIR_STATUS)));
905 return (sc->sc_pci_hpbcfg[reg]);
907 return (le16dec(&sc->sc_pci_hpbcfg[reg]));
909 return (le32dec(&sc->sc_pci_hpbcfg[reg]));
913 return (ofw_pci_read_config_common(dev, PCI_REGMAX,
914 PSYCHO_CONF_OFF(bus, slot, func, reg), bus, slot, func, reg,
919 psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func,
920 u_int reg, uint32_t val, int width)
923 ofw_pci_write_config_common(dev, PCI_REGMAX, PSYCHO_CONF_OFF(bus,
924 slot, func, reg), bus, slot, func, reg, val, width);
928 psycho_route_interrupt(device_t bridge, device_t dev, int pin)
930 struct psycho_softc *sc;
932 ofw_pci_intr_t mintr;
934 mintr = ofw_pci_route_interrupt_common(bridge, dev, pin);
935 if (PCI_INTERRUPT_VALID(mintr))
938 * If this is outside of the range for an intpin, it's likely a full
939 * INO, and no mapping is required at all; this happens on the U30,
940 * where there's no interrupt map at the Psycho node. Fortunately,
941 * there seem to be no INOs in the intpin range on this boxen, so
942 * this easy heuristics will do.
947 * Guess the INO; we always assume that this is a non-OBIO
948 * device, and that pin is a "real" intpin number. Determine
949 * the mapping register to be used by the slot number.
950 * We only need to do this on E450s, it seems; here, the slot numbers
951 * for bus A are one-based, while those for bus B seemingly have an
952 * offset of 2 (hence the factor of 3 below).
954 sc = device_get_softc(dev);
955 intrmap = PSR_PCIA0_INT_MAP +
956 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half);
957 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1;
958 device_printf(bridge,
959 "guessing interrupt %d for device %d.%d pin %d\n",
960 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin);
965 sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
967 struct iommu_state *is = dt->dt_cookie;
969 if ((map->dm_flags & DMF_LOADED) == 0)
972 if ((op & BUS_DMASYNC_POSTREAD) != 0)
973 (void)bus_space_read_8(is->is_bustag, is->is_bushandle,
976 if ((op & BUS_DMASYNC_PREWRITE) != 0)
981 psycho_intr_enable(void *arg)
983 struct intr_vector *iv = arg;
984 struct psycho_icarg *pica = iv->iv_icarg;
986 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map,
987 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
991 psycho_intr_disable(void *arg)
993 struct intr_vector *iv = arg;
994 struct psycho_icarg *pica = iv->iv_icarg;
996 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec);
1000 psycho_intr_assign(void *arg)
1002 struct intr_vector *iv = arg;
1003 struct psycho_icarg *pica = iv->iv_icarg;
1005 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, INTMAP_TID(
1006 PSYCHO_READ8(pica->pica_sc, pica->pica_map), iv->iv_mid));
1010 psycho_intr_clear(void *arg)
1012 struct intr_vector *iv = arg;
1013 struct psycho_icarg *pica = iv->iv_icarg;
1015 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, INTCLR_IDLE);
1019 psycho_setup_intr(device_t dev, device_t child, struct resource *ires,
1020 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
1023 struct psycho_softc *sc;
1026 sc = device_get_softc(dev);
1028 * Make sure the vector is fully specified and we registered
1029 * our interrupt controller for it.
1031 vec = rman_get_start(ires);
1032 if (INTIGN(vec) != sc->sc_ign ||
1033 intr_vectors[vec].iv_ic != &psycho_ic) {
1034 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
1037 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
1041 static struct resource *
1042 psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
1043 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1045 struct psycho_softc *sc;
1047 if (type == SYS_RES_IRQ) {
1048 sc = device_get_softc(bus);
1049 start = end = INTMAP_VEC(sc->sc_ign, end);
1051 return (ofw_pci_alloc_resource(bus, child, type, rid, start, end,
1056 psycho_setup_device(device_t bus, device_t child)
1058 struct psycho_softc *sc;
1061 sc = device_get_softc(bus);
1063 * Revision 0 EBus bridges have a bug which prevents them from
1064 * working when bus parking is enabled.
1066 if ((strcmp(ofw_bus_get_name(child), "ebus") == 0 ||
1067 strcmp(ofw_bus_get_name(child), "pci108e,1000") == 0) &&
1068 OF_getprop(ofw_bus_get_node(child), "revision-id", &rev,
1069 sizeof(rev)) > 0 && rev == 0)
1070 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS) &