2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+'
38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges.
41 #include "opt_ofw_pci.h"
42 #include "opt_psycho.h"
44 #include <sys/param.h>
45 #include <sys/systm.h>
48 #include <sys/kernel.h>
50 #include <sys/malloc.h>
51 #include <sys/module.h>
52 #include <sys/mutex.h>
54 #include <sys/reboot.h>
57 #include <dev/ofw/ofw_bus.h>
58 #include <dev/ofw/ofw_pci.h>
59 #include <dev/ofw/openfirm.h>
61 #include <machine/bus.h>
62 #include <machine/bus_common.h>
63 #include <machine/bus_private.h>
64 #include <machine/iommureg.h>
65 #include <machine/iommuvar.h>
66 #include <machine/ofw_bus.h>
67 #include <machine/resource.h>
68 #include <machine/ver.h>
70 #include <dev/pci/pcireg.h>
71 #include <dev/pci/pcivar.h>
73 #include <sparc64/pci/ofw_pci.h>
74 #include <sparc64/pci/psychoreg.h>
75 #include <sparc64/pci/psychovar.h>
79 static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *,
81 static const struct psycho_desc *psycho_get_desc(device_t);
82 static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t,
83 driver_filter_t, driver_intr_t);
84 static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *,
85 bus_addr_t *, u_long *);
86 static driver_filter_t psycho_dmasync;
87 static void psycho_intr_enable(void *);
88 static void psycho_intr_disable(void *);
89 static void psycho_intr_eoi(void *);
90 static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int);
92 /* Interrupt handlers */
93 static driver_filter_t psycho_ue;
94 static driver_filter_t psycho_ce;
95 static driver_filter_t psycho_pci_bus;
96 static driver_filter_t psycho_powerfail;
97 static driver_intr_t psycho_overtemp;
98 #ifdef PSYCHO_MAP_WAKEUP
99 static driver_filter_t psycho_wakeup;
103 static void psycho_iommu_init(struct psycho_softc *, int, uint32_t);
108 static device_probe_t psycho_probe;
109 static device_attach_t psycho_attach;
110 static bus_read_ivar_t psycho_read_ivar;
111 static bus_setup_intr_t psycho_setup_intr;
112 static bus_teardown_intr_t psycho_teardown_intr;
113 static bus_alloc_resource_t psycho_alloc_resource;
114 static bus_activate_resource_t psycho_activate_resource;
115 static bus_deactivate_resource_t psycho_deactivate_resource;
116 static bus_release_resource_t psycho_release_resource;
117 static bus_get_dma_tag_t psycho_get_dma_tag;
118 static pcib_maxslots_t psycho_maxslots;
119 static pcib_read_config_t psycho_read_config;
120 static pcib_write_config_t psycho_write_config;
121 static pcib_route_interrupt_t psycho_route_interrupt;
122 static ofw_pci_intr_pending_t psycho_intr_pending;
123 static ofw_bus_get_node_t psycho_get_node;
124 static ofw_pci_alloc_busno_t psycho_alloc_busno;
125 static ofw_pci_adjust_busrange_t psycho_adjust_busrange;
127 static device_method_t psycho_methods[] = {
128 /* Device interface */
129 DEVMETHOD(device_probe, psycho_probe),
130 DEVMETHOD(device_attach, psycho_attach),
131 DEVMETHOD(device_shutdown, bus_generic_shutdown),
132 DEVMETHOD(device_suspend, bus_generic_suspend),
133 DEVMETHOD(device_resume, bus_generic_resume),
136 DEVMETHOD(bus_print_child, bus_generic_print_child),
137 DEVMETHOD(bus_read_ivar, psycho_read_ivar),
138 DEVMETHOD(bus_setup_intr, psycho_setup_intr),
139 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr),
140 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource),
141 DEVMETHOD(bus_activate_resource, psycho_activate_resource),
142 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource),
143 DEVMETHOD(bus_release_resource, psycho_release_resource),
144 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag),
147 DEVMETHOD(pcib_maxslots, psycho_maxslots),
148 DEVMETHOD(pcib_read_config, psycho_read_config),
149 DEVMETHOD(pcib_write_config, psycho_write_config),
150 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt),
152 /* ofw_bus interface */
153 DEVMETHOD(ofw_bus_get_node, psycho_get_node),
155 /* ofw_pci interface */
156 DEVMETHOD(ofw_pci_intr_pending, psycho_intr_pending),
157 DEVMETHOD(ofw_pci_alloc_busno, psycho_alloc_busno),
158 DEVMETHOD(ofw_pci_adjust_busrange, psycho_adjust_busrange),
163 static driver_t psycho_driver = {
166 sizeof(struct psycho_softc),
169 static devclass_t psycho_devclass;
171 DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0);
173 static SLIST_HEAD(, psycho_softc) psycho_softcs =
174 SLIST_HEAD_INITIALIZER(psycho_softcs);
176 static uint8_t psycho_pci_bus_cnt;
178 static const struct intr_controller psycho_ic = {
184 struct psycho_icarg {
185 struct psycho_softc *pica_sc;
190 struct psycho_dmasync {
191 struct psycho_softc *pds_sc;
192 driver_filter_t *pds_handler; /* handler to call */
193 void *pds_arg; /* argument for the handler */
194 void *pds_cookie; /* parent bus int. cookie */
195 device_t pds_ppb; /* farest PCI-PCI bridge */
196 uint8_t pds_bus; /* bus of farest PCI device */
197 uint8_t pds_slot; /* slot of farest PCI device */
198 uint8_t pds_func; /* func. of farest PCI device */
201 #define PSYCHO_READ8(sc, off) \
202 bus_read_8((sc)->sc_mem_res, (off))
203 #define PSYCHO_WRITE8(sc, off, v) \
204 bus_write_8((sc)->sc_mem_res, (off), (v))
205 #define PCICTL_READ8(sc, off) \
206 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off))
207 #define PCICTL_WRITE8(sc, off, v) \
208 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v))
211 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a
212 * single PCI bus and does not have a streaming buffer. It often has an APB
213 * (advanced PCI bridge) connected to it, which was designed specifically for
214 * the IIi. The APB let's the IIi handle two independednt PCI buses, and
215 * appears as two "Simba"'s underneath the Sabre.
217 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's
218 * basically the same as Sabre but without an APB underneath it.
220 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA bus
221 * and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while
222 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You
223 * will usually find a "Psycho+" since I don't think the original "Psycho"
224 * ever shipped, and if it did it would be in the U30.
226 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are
227 * both part of the same IC, they only have a single register space. As such,
228 * they need to be configured together, even though the autoconfiguration will
229 * attach them separately.
231 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often
232 * as pci1 and pci2, although they have been implemented with other PCI bus
233 * numbers on some machines.
235 * On UltraII machines, there can be any number of "Psycho+" ICs, each
236 * providing two PCI buses.
239 #define OFW_PCI_TYPE "pci"
242 const char *pd_string;
247 static const struct psycho_desc psycho_compats[] = {
248 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" },
249 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" },
250 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" },
254 static const struct psycho_desc psycho_models[] = {
255 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" },
256 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" },
260 static const struct psycho_desc *
261 psycho_find_desc(const struct psycho_desc *table, const char *string)
263 const struct psycho_desc *desc;
267 for (desc = table; desc->pd_string != NULL; desc++)
268 if (strcmp(desc->pd_string, string) == 0)
273 static const struct psycho_desc *
274 psycho_get_desc(device_t dev)
276 const struct psycho_desc *rv;
278 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev));
280 rv = psycho_find_desc(psycho_compats, ofw_bus_get_compat(dev));
285 psycho_probe(device_t dev)
289 dtype = ofw_bus_get_type(dev);
290 if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 &&
291 psycho_get_desc(dev) != NULL) {
292 device_set_desc(dev, "U2P UPA-PCI bridge");
300 psycho_attach(device_t dev)
302 char name[sizeof("pci108e,1000")];
303 struct psycho_icarg *pica;
304 struct psycho_softc *asc, *sc, *osc;
305 struct ofw_pci_ranges *range;
306 const struct psycho_desc *desc;
307 phandle_t child, node;
308 bus_addr_t intrclr, intrmap;
310 uint32_t dvmabase, psycho_br[2];
313 int i, n, nrange, rid;
315 node = ofw_bus_get_node(dev);
316 sc = device_get_softc(dev);
317 desc = psycho_get_desc(dev);
321 sc->sc_mode = desc->pd_mode;
324 * The Psycho gets three register banks:
325 * (0) per-PBM configuration and status registers
326 * (1) per-PBM PCI configuration space, containing only the
327 * PBM 256-byte PCI header
328 * (2) the shared Psycho configuration registers
330 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
333 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) -
334 bus_get_resource_start(dev, SYS_RES_MEMORY, 2);
335 switch (sc->sc_pcictl) {
343 panic("%s: bogus PCI control register location",
348 sc->sc_pcictl = PSR_PCICTL0;
351 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
352 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) |
354 if (sc->sc_mem_res == NULL)
355 panic("%s: could not allocate registers", __func__);
358 * Match other Psycho's that are already configured against
359 * the base physical address. This will be the same for a
360 * pair of devices that share register space.
363 SLIST_FOREACH(asc, &psycho_softcs, sc_link) {
364 if (rman_get_start(asc->sc_mem_res) ==
365 rman_get_start(sc->sc_mem_res)) {
372 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF,
374 if (sc->sc_mtx == NULL)
375 panic("%s: could not malloc mutex", __func__);
376 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
378 if (mtx_initialized(osc->sc_mtx) == 0)
379 panic("%s: mutex not initialized", __func__);
380 sc->sc_mtx = osc->sc_mtx;
383 /* Clear PCI AFSR. */
384 PCICTL_WRITE8(sc, PCR_AFS, PCIAFSR_ERRMASK);
386 csr = PSYCHO_READ8(sc, PSR_CS);
387 ver = PSYCHO_GCSR_VERS(csr);
388 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */
389 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
390 sc->sc_ign = PSYCHO_GCSR_IGN(csr);
392 device_printf(dev, "%s, impl %d, version %d, IGN %#x, bus %c\n",
393 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign,
396 /* Set up the PCI control and PCI diagnostic registers. */
399 * Revision 0 EBus bridges have a bug which prevents them from
400 * working when bus parking is enabled.
403 csr = PCICTL_READ8(sc, PCR_CS);
404 csr &= ~PCICTL_ARB_PARK;
405 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
406 if (OF_getprop(child, "name", name, sizeof(name)) == -1)
408 if ((strcmp(name, "ebus") == 0 ||
409 strcmp(name, "pci108e,1000") == 0) &&
410 OF_getprop(child, "revision-id", &rev, sizeof(rev)) > 0 &&
414 if (rev != 0 && OF_getproplen(node, "no-bus-parking") < 0)
415 csr |= PCICTL_ARB_PARK;
417 /* Workarounds for version specific bugs. */
418 dr = PCICTL_READ8(sc, PCR_DIAG);
422 dr &= ~DIAG_DWSYNC_DIS;
423 /* XXX need to also disable rerun of the streaming buffers. */
426 csr &= ~PCICTL_ARB_PARK;
427 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS;
428 /* XXX need to also disable rerun of the streaming buffers. */
431 dr |= DIAG_DWSYNC_DIS;
432 dr &= ~DIAG_RTRY_DIS;
436 csr |= PCICTL_SERR | PCICTL_ERRINTEN | PCICTL_ARB_4;
437 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN);
439 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n",
440 (unsigned long long)PCICTL_READ8(sc, PCR_CS),
441 (unsigned long long)csr);
443 PCICTL_WRITE8(sc, PCR_CS, csr);
445 dr &= ~DIAG_ISYNC_DIS;
447 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
448 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG),
449 (unsigned long long)dr);
451 PCICTL_WRITE8(sc, PCR_DIAG, dr);
453 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
454 /* Use the PROM preset for now. */
455 csr = PCICTL_READ8(sc, PCR_TAS);
457 panic("%s: Hummingbird/Sabre TAS not initialized.",
459 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT;
463 /* Initialize memory and I/O rmans. */
464 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
465 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports";
466 if (rman_init(&sc->sc_pci_io_rman) != 0 ||
467 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0)
468 panic("%s: failed to set up I/O rman", __func__);
469 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
470 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory";
471 if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
472 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0)
473 panic("%s: failed to set up memory rman", __func__);
475 nrange = OF_getprop_alloc(node, "ranges", sizeof(*range),
478 * Make sure that the expected ranges are present. The OFW_PCI_CS_MEM64
479 * one is not currently used though.
481 if (nrange != PSYCHO_NRANGE)
482 panic("%s: unsupported number of ranges", __func__);
484 * Find the addresses of the various bus spaces.
485 * There should not be multiple ones of one kind.
486 * The physical start addresses of the ranges are the configuration,
487 * memory and I/O handles.
489 for (n = 0; n < PSYCHO_NRANGE; n++) {
490 i = OFW_PCI_RANGE_CS(&range[n]);
491 if (sc->sc_pci_bh[i] != 0)
492 panic("%s: duplicate range for space %d", __func__, i);
493 sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]);
495 free(range, M_OFWPROP);
497 /* Register the softc, this is needed for paired Psychos. */
498 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link);
501 * If we're a Hummingbird/Sabre or the first of a pair of Psychos
502 * to arrive here, do the interrupt setup and start up the IOMMU.
506 * Hunt through all the interrupt mapping regs and register
507 * our interrupt controller for the corresponding interrupt
510 for (n = 0; n <= PSYCHO_MAX_INO; n++) {
511 if (psycho_find_intrmap(sc, n, &intrmap, &intrclr,
514 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT);
516 panic("%s: could not allocate interrupt "
517 "controller argument", __func__);
519 pica->pica_map = intrmap;
520 pica->pica_clr = intrclr;
523 * Enable all interrupts and clear all interrupt
524 * states. This aids the debugging of interrupt
528 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n",
529 n, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO",
530 (u_long)intrmap, (u_long)PSYCHO_READ8(sc, intrmap),
532 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, n));
533 PSYCHO_WRITE8(sc, intrclr, 0);
534 PSYCHO_WRITE8(sc, intrmap,
535 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, n),
538 if (intr_controller_register(INTMAP_VEC(sc->sc_ign, n),
539 &psycho_ic, pica) != 0)
540 panic("%s: could not register interrupt "
541 "controller for INO %d", __func__, n);
545 * Establish handlers for interesting interrupts...
547 * XXX We need to remember these and remove this to support
548 * hotplug on the UPA/FHC bus.
550 * XXX Not all controllers have these, but installing them
551 * is better than trying to sort through this mess.
553 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL);
554 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL);
555 #ifdef DEBUGGER_ON_POWERFAIL
556 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail,
559 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL,
560 (driver_intr_t *)psycho_powerfail);
562 /* Psycho-specific initialization */
563 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
565 * Hummingbirds/Sabres do not have the following two
570 * The spare hardware interrupt is used for the
571 * over-temperature interrupt.
573 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP,
574 NULL, psycho_overtemp);
575 #ifdef PSYCHO_MAP_WAKEUP
577 * psycho_wakeup() doesn't do anything useful right
580 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP,
581 psycho_wakeup, NULL);
582 #endif /* PSYCHO_MAP_WAKEUP */
584 /* Initialize the counter-timer. */
585 sparc64_counter_init(rman_get_bustag(sc->sc_mem_res),
586 rman_get_bushandle(sc->sc_mem_res), PSR_TC0);
590 * Set up IOMMU and PCI configuration if we're the first
591 * of a pair of Psycho's to arrive here.
593 * We should calculate a TSB size based on amount of RAM
594 * and number of bus controllers and number and type of
597 * For the moment, 32KB should be more than enough.
599 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF,
601 if (sc->sc_is == NULL)
602 panic("%s: malloc iommu_state failed", __func__);
603 if (sc->sc_mode == PSYCHO_MODE_SABRE)
604 sc->sc_is->is_pmaxaddr =
605 IOMMU_MAXADDR(SABRE_IOMMU_BITS);
607 sc->sc_is->is_pmaxaddr =
608 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS);
609 sc->sc_is->is_sb[0] = 0;
610 sc->sc_is->is_sb[1] = 0;
611 if (OF_getproplen(node, "no-streaming-cache") < 0)
612 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF;
613 psycho_iommu_init(sc, 3, dvmabase);
615 /* Just copy IOMMU state, config tag and address. */
616 sc->sc_is = osc->sc_is;
617 if (OF_getproplen(node, "no-streaming-cache") < 0)
618 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF;
619 iommu_reset(sc->sc_is);
623 * Register a PCI bus error interrupt handler according to which
624 * half this is. Hummingbird/Sabre don't have a PCI bus B error
625 * interrupt but they are also only used for PCI bus A.
627 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP :
628 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL);
630 /* Allocate our tags. */
631 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE);
632 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE);
633 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE);
634 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
635 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr,
636 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
637 panic("%s: bus_dma_tag_create failed", __func__);
638 /* Customize the tag. */
639 sc->sc_pci_dmat->dt_cookie = sc->sc_is;
640 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods;
643 * Get the bus range from the firmware; it is used solely for obtaining
644 * the inital bus number, and cannot be trusted on all machines.
646 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br));
648 panic("%s: could not get bus-range", __func__);
649 if (n != sizeof(psycho_br))
650 panic("%s: broken bus-range (%d)", __func__, n);
652 /* Clear PCI status error bits. */
653 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC,
654 PCIR_STATUS, PCIM_STATUS_PERR | PCIM_STATUS_RMABORT |
655 PCIM_STATUS_RTABORT | PCIM_STATUS_STABORT |
656 PCIM_STATUS_PERRREPORT, 2);
659 * Set the latency timer register as this isn't always done by the
662 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC,
663 PCIR_LATTIMER, 64, 1);
665 sc->sc_pci_secbus = sc->sc_pci_subbus = psycho_alloc_busno(dev);
667 * Program the bus range registers.
668 * NOTE: for the Psycho, the second write changes the bus number the
669 * Psycho itself uses for it's configuration space, so these
670 * writes must be kept in this order!
671 * The Hummingbird/Sabre always uses bus 0, but there only can be one
672 * Hummingbird/Sabre per machine.
674 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SUBBUS,
675 sc->sc_pci_subbus, 1);
676 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SECBUS,
677 sc->sc_pci_secbus, 1);
679 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
681 * On E250 the interrupt map entry for the EBus bridge is wrong,
682 * causing incorrect interrupts to be assigned to some devices on
683 * the EBus. Work around it by changing our copy of the interrupt
684 * map mask to perform a full comparison of the INO. That way
685 * the interrupt map entry for the EBus bridge won't match at all
686 * and the INOs specified in the "interrupts" properties of the
687 * EBus devices will be used directly instead.
689 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 &&
690 sc->sc_pci_iinfo.opi_imapmsk != NULL)
691 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[
692 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK;
694 device_add_child(dev, "pci", sc->sc_pci_secbus);
695 return (bus_generic_attach(dev));
699 psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap,
700 driver_filter_t filt, driver_intr_t intr)
706 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ,
708 if (sc->sc_irq_res[index] == NULL ||
709 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign ||
710 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec ||
711 intr_vectors[vec].iv_ic != &psycho_ic ||
712 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], INTR_TYPE_MISC,
713 filt, intr, sc, &sc->sc_ihand[index]) != 0)
714 panic("%s: failed to set up interrupt %d", __func__, index);
718 psycho_find_intrmap(struct psycho_softc *sc, u_int ino, bus_addr_t *intrmapptr,
719 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr)
721 bus_addr_t intrclr, intrmap;
726 * XXX we only compare INOs rather than INRs since the firmware may
727 * not provide the IGN and the IGN is constant for all devices on
728 * that PCI controller.
729 * This could cause problems for the FFB/external interrupt which
730 * has a full vector that can be set arbitrarily.
733 if (ino > PSYCHO_MAX_INO) {
734 device_printf(sc->sc_dev, "out of range INO %d requested\n",
740 /* Hunt through OBIO first. */
741 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG);
742 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR;
743 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8,
745 if (sc->sc_mode == PSYCHO_MODE_SABRE &&
746 (intrmap == PSR_TIMER0_INT_MAP ||
747 intrmap == PSR_TIMER1_INT_MAP ||
748 intrmap == PSR_PCIBERR_INT_MAP ||
749 intrmap == PSR_PWRMGT_INT_MAP))
751 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) {
759 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG);
760 /* Now do PCI interrupts. */
761 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR;
762 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32,
764 if (sc->sc_mode == PSYCHO_MODE_PSYCHO &&
765 (intrmap == PSR_PCIA2_INT_MAP ||
766 intrmap == PSR_PCIA3_INT_MAP))
768 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) {
769 intrclr += 8 * (ino & 3);
770 diag = (diag >> ((ino & 3) * 2)) & 2;
776 if (intrmapptr != NULL)
777 *intrmapptr = intrmap;
778 if (intrclrptr != NULL)
779 *intrclrptr = intrclr;
780 if (intrdiagptr != NULL)
791 struct psycho_softc *sc = arg;
794 afar = PSYCHO_READ8(sc, PSR_UE_AFA);
795 afsr = PSYCHO_READ8(sc, PSR_UE_AFS);
797 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause
798 * the AFAR to be set to the physical address of the TTE entry that
799 * was invalid/write protected. Call into the iommu code to have
800 * them decoded to virtual I/O addresses.
802 if ((afsr & UEAFSR_P_DTE) != 0)
803 iommu_decode_fault(sc->sc_is, afar);
804 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx",
805 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr);
806 return (FILTER_HANDLED);
812 struct psycho_softc *sc = arg;
815 mtx_lock_spin(sc->sc_mtx);
816 afar = PSYCHO_READ8(sc, PSR_CE_AFA);
817 afsr = PSYCHO_READ8(sc, PSR_CE_AFS);
818 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx "
819 "AFSR %#lx\n", (u_long)afar, (u_long)afsr);
820 /* Clear the error bits that we caught. */
821 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr & CEAFSR_ERRMASK);
822 mtx_unlock_spin(sc->sc_mtx);
823 return (FILTER_HANDLED);
827 psycho_pci_bus(void *arg)
829 struct psycho_softc *sc = arg;
832 afar = PCICTL_READ8(sc, PCR_AFA);
833 afsr = PCICTL_READ8(sc, PCR_AFS);
834 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx",
835 device_get_name(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar,
837 return (FILTER_HANDLED);
841 psycho_powerfail(void *arg)
843 #ifdef DEBUGGER_ON_POWERFAIL
844 struct psycho_softc *sc = arg;
846 kdb_enter("powerfail");
850 /* As the interrupt is cleared we may be called multiple times. */
852 return (FILTER_HANDLED);
854 printf("Power Failure Detected: Shutting down NOW.\n");
857 return (FILTER_HANDLED);
861 psycho_overtemp(void *arg)
865 /* As the interrupt is cleared we may be called multiple times. */
869 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n");
870 shutdown_nice(RB_POWEROFF);
873 #ifdef PSYCHO_MAP_WAKEUP
875 psycho_wakeup(void *arg)
877 struct psycho_softc *sc = arg;
879 /* Gee, we don't really have a framework to deal with this properly. */
880 device_printf(sc->sc_dev, "power management wakeup\n");
881 return (FILTER_HANDLED);
883 #endif /* PSYCHO_MAP_WAKEUP */
886 psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase)
889 struct iommu_state *is = sc->sc_is;
891 /* Punch in our copies. */
892 is->is_bustag = rman_get_bustag(sc->sc_mem_res);
893 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res);
894 is->is_iommu = PSR_IOMMU;
895 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG;
896 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG;
897 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG;
898 is->is_dva = PSR_IOMMU_SVADIAG;
899 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG;
901 /* Give us a nice name... */
902 name = malloc(32, M_DEVBUF, M_NOWAIT);
904 panic("%s: could not malloc iommu name", __func__);
905 snprintf(name, 32, "%s dvma", device_get_nameunit(sc->sc_dev));
907 iommu_init(name, is, tsbsize, dvmabase, 0);
911 psycho_maxslots(device_t dev)
914 /* XXX: is this correct? */
915 return (PCI_SLOTMAX);
919 psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
922 struct psycho_softc *sc;
923 bus_space_handle_t bh;
931 sc = device_get_softc(dev);
932 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
933 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
936 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
940 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
944 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
948 panic("%s: bad width", __func__);
953 printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
954 __func__, bus, slot, func, reg);
962 psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
963 uint32_t val, int width)
965 struct psycho_softc *sc;
966 bus_space_handle_t bh;
969 sc = device_get_softc(dev);
970 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
971 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
974 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
977 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
980 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
983 panic("%s: bad width", __func__);
988 psycho_route_interrupt(device_t bridge, device_t dev, int pin)
990 struct psycho_softc *sc;
991 struct ofw_pci_register reg;
993 ofw_pci_intr_t pintr, mintr;
994 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
996 sc = device_get_softc(bridge);
998 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®,
999 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf))
1002 * If this is outside of the range for an intpin, it's likely a full
1003 * INO, and no mapping is required at all; this happens on the U30,
1004 * where there's no interrupt map at the Psycho node. Fortunately,
1005 * there seem to be no INOs in the intpin range on this boxen, so
1006 * this easy heuristics will do.
1011 * Guess the INO; we always assume that this is a non-OBIO
1012 * device, and that pin is a "real" intpin number. Determine
1013 * the mapping register to be used by the slot number.
1014 * We only need to do this on E450s, it seems; here, the slot numbers
1015 * for bus A are one-based, while those for bus B seemingly have an
1016 * offset of 2 (hence the factor of 3 below).
1018 intrmap = PSR_PCIA0_INT_MAP +
1019 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half);
1020 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1;
1021 device_printf(bridge, "guessing interrupt %d for device %d.%d pin %d\n",
1022 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin);
1027 psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1029 struct psycho_softc *sc;
1031 sc = device_get_softc(dev);
1034 *result = sc->sc_pci_secbus;
1041 psycho_dmasync(void *arg)
1043 struct psycho_dmasync *pds = arg;
1045 (void)PCIB_READ_CONFIG(pds->pds_ppb, pds->pds_bus, pds->pds_slot,
1046 pds->pds_func, PCIR_VENDOR, 2);
1047 (void)PSYCHO_READ8(pds->pds_sc, PSR_DMA_WRITE_SYNC);
1048 return (pds->pds_handler(pds->pds_arg));
1052 psycho_intr_enable(void *arg)
1054 struct intr_vector *iv = arg;
1055 struct psycho_icarg *pica = iv->iv_icarg;
1057 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map,
1058 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
1062 psycho_intr_disable(void *arg)
1064 struct intr_vector *iv = arg;
1065 struct psycho_icarg *pica = iv->iv_icarg;
1067 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec);
1071 psycho_intr_eoi(void *arg)
1073 struct intr_vector *iv = arg;
1074 struct psycho_icarg *pica = iv->iv_icarg;
1076 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, 0);
1080 psycho_setup_intr(device_t dev, device_t child, struct resource *ires,
1081 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
1088 devclass_t pci_devclass;
1089 device_t cdev, pdev, pcidev;
1090 struct psycho_softc *sc;
1091 struct psycho_dmasync *pds;
1095 sc = device_get_softc(dev);
1097 * Make sure the vector is fully specified and we registered
1098 * our interrupt controller for it.
1100 vec = rman_get_start(ires);
1101 if (INTIGN(vec) != sc->sc_ign ||
1102 intr_vectors[vec].iv_ic != &psycho_ic) {
1103 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
1108 * The Sabre-APB-combination has a bug where it does not drain
1109 * DMA write data for devices behind additional PCI-PCI bridges
1110 * underneath the APB PCI-PCI bridge. The workaround is to do
1111 * a read on the farest PCI-PCI bridge followed by a read of the
1112 * PCI DMA write sync register of the Sabre.
1113 * XXX installing the wrapper for an affected device and the
1114 * actual workaround in psycho_dmasync() should be moved to
1115 * psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync()
1116 * methods, respectively, once DMA tag creation is newbus'ified,
1117 * so the workaround isn't only applied for interrupt handlers
1118 * but also for polling(4) callbacks.
1120 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
1121 pds = malloc(sizeof(*pds), M_DEVBUF, M_NOWAIT | M_ZERO);
1125 found.apb = found.ppb = 0;
1126 pci_devclass = devclass_find("pci");
1127 for (cdev = child; cdev != dev; cdev = pdev) {
1128 pdev = device_get_parent(cdev);
1129 if (pcidev == NULL) {
1130 if (device_get_devclass(pdev) != pci_devclass)
1136 * NB: APB would also match as PCI-PCI bridges.
1138 if (pci_get_vendor(cdev) == 0x108e &&
1139 pci_get_device(cdev) == 0x5000) {
1143 if (pci_get_class(cdev) == PCIC_BRIDGE &&
1144 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI)
1147 if (found.apb && found.ppb && pcidev != NULL) {
1151 device_get_parent(device_get_parent(pcidev));
1152 pds->pds_bus = pci_get_bus(pcidev);
1153 pds->pds_slot = pci_get_slot(pcidev);
1154 pds->pds_func = pci_get_function(pcidev);
1156 device_printf(dev, "installed DMA sync "
1157 "workaround for device %d.%d on bus %d\n",
1158 pds->pds_slot, pds->pds_func,
1161 pds->pds_handler = filt;
1162 error = bus_generic_setup_intr(dev, child,
1163 ires, flags, psycho_dmasync, intr, pds,
1166 pds->pds_handler = (driver_filter_t *)intr;
1167 error = bus_generic_setup_intr(dev, child,
1169 (driver_intr_t *)psycho_dmasync, pds,
1173 error = bus_generic_setup_intr(dev, child, ires,
1174 flags, filt, intr, arg, cookiep);
1176 free(pds, M_DEVBUF);
1179 pds->pds_cookie = *cookiep;
1183 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
1188 psycho_teardown_intr(device_t dev, device_t child, struct resource *vec,
1191 struct psycho_softc *sc;
1192 struct psycho_dmasync *pds;
1195 sc = device_get_softc(dev);
1196 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
1198 error = bus_generic_teardown_intr(dev, child, vec,
1201 free(pds, M_DEVBUF);
1204 return (bus_generic_teardown_intr(dev, child, vec, cookie));
1207 static struct resource *
1208 psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
1209 u_long start, u_long end, u_long count, u_int flags)
1211 struct psycho_softc *sc;
1212 struct resource *rv;
1215 bus_space_handle_t bh;
1216 int needactivate = flags & RF_ACTIVE;
1218 flags &= ~RF_ACTIVE;
1220 sc = device_get_softc(bus);
1221 if (type == SYS_RES_IRQ) {
1223 * XXX: Don't accept blank ranges for now, only single
1224 * interrupts. The other case should not happen with the
1226 * XXX: This may return a resource that is out of the
1227 * range that was specified. Is this correct...?
1230 panic("%s: XXX: interrupt range", __func__);
1231 start = end = INTMAP_VEC(sc->sc_ign, end);
1232 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type,
1233 rid, start, end, count, flags));
1236 case SYS_RES_MEMORY:
1237 rm = &sc->sc_pci_mem_rman;
1238 bt = sc->sc_pci_memt;
1239 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32];
1241 case SYS_RES_IOPORT:
1242 rm = &sc->sc_pci_io_rman;
1243 bt = sc->sc_pci_iot;
1244 bh = sc->sc_pci_bh[OFW_PCI_CS_IO];
1250 rv = rman_reserve_resource(rm, start, end, count, flags, child);
1253 rman_set_rid(rv, *rid);
1254 bh += rman_get_start(rv);
1255 rman_set_bustag(rv, bt);
1256 rman_set_bushandle(rv, bh);
1259 if (bus_activate_resource(child, type, *rid, rv)) {
1260 rman_release_resource(rv);
1269 psycho_activate_resource(device_t bus, device_t child, int type, int rid,
1275 if (type == SYS_RES_IRQ)
1276 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child,
1278 if (type == SYS_RES_MEMORY) {
1280 * Need to memory-map the device space, as some drivers depend
1281 * on the virtual address being set and useable.
1283 error = sparc64_bus_mem_map(rman_get_bustag(r),
1284 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p);
1287 rman_set_virtual(r, p);
1289 return (rman_activate_resource(r));
1293 psycho_deactivate_resource(device_t bus, device_t child, int type, int rid,
1297 if (type == SYS_RES_IRQ)
1298 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child,
1300 if (type == SYS_RES_MEMORY) {
1301 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r));
1302 rman_set_virtual(r, NULL);
1304 return (rman_deactivate_resource(r));
1308 psycho_release_resource(device_t bus, device_t child, int type, int rid,
1313 if (type == SYS_RES_IRQ)
1314 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child,
1316 if (rman_get_flags(r) & RF_ACTIVE) {
1317 error = bus_deactivate_resource(child, type, rid, r);
1321 return (rman_release_resource(r));
1324 static bus_dma_tag_t
1325 psycho_get_dma_tag(device_t bus, device_t child)
1327 struct psycho_softc *sc;
1329 sc = device_get_softc(bus);
1330 return (sc->sc_pci_dmat);
1334 psycho_intr_pending(device_t dev, ofw_pci_intr_t intr)
1336 struct psycho_softc *sc;
1339 sc = device_get_softc(dev);
1340 if (psycho_find_intrmap(sc, intr, NULL, NULL, &diag) == 0) {
1341 device_printf(dev, "%s: mapping not found for %d\n", __func__,
1349 psycho_get_node(device_t bus, device_t dev)
1351 struct psycho_softc *sc;
1353 sc = device_get_softc(bus);
1354 /* We only have one child, the PCI bus, which needs our own node. */
1355 return (sc->sc_node);
1359 psycho_alloc_busno(device_t dev)
1362 if (psycho_pci_bus_cnt == PCI_BUSMAX)
1363 panic("%s: out of PCI bus numbers", __func__);
1364 return (psycho_pci_bus_cnt++);
1368 psycho_adjust_busrange(device_t dev, u_int subbus)
1370 struct psycho_softc *sc;
1372 sc = device_get_softc(dev);
1373 /* If necessary, adjust the subordinate bus number register. */
1374 if (subbus > sc->sc_pci_subbus) {
1377 "adjusting subordinate bus number from %d to %d\n",
1378 sc->sc_pci_subbus, subbus);
1380 sc->sc_pci_subbus = subbus;
1381 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
1382 PCSR_SUBBUS, subbus, 1);
1386 static bus_space_tag_t
1387 psycho_alloc_bus_tag(struct psycho_softc *sc, int type)
1391 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, M_NOWAIT | M_ZERO);
1393 panic("%s: out of memory", __func__);
1395 bt->bst_cookie = sc;
1396 bt->bst_parent = rman_get_bustag(sc->sc_mem_res);
1397 bt->bst_type = type;