2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2011 by Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1, `Tomatillo' JBus to
39 * PCI 2.2 and `XMITS' Fireplane/Safari to PCI-X bridges
42 #include "opt_ofw_pci.h"
43 #include "opt_schizo.h"
45 #include <sys/param.h>
46 #include <sys/systm.h>
48 #include <sys/kernel.h>
50 #include <sys/malloc.h>
51 #include <sys/module.h>
52 #include <sys/mutex.h>
55 #include <sys/sysctl.h>
57 #include <sys/timetc.h>
59 #include <dev/ofw/ofw_bus.h>
60 #include <dev/ofw/ofw_pci.h>
61 #include <dev/ofw/openfirm.h>
63 #include <machine/bus.h>
64 #include <machine/bus_common.h>
65 #include <machine/bus_private.h>
66 #include <machine/fsr.h>
67 #include <machine/iommureg.h>
68 #include <machine/iommuvar.h>
69 #include <machine/resource.h>
71 #include <dev/pci/pcireg.h>
72 #include <dev/pci/pcivar.h>
74 #include <sparc64/pci/ofw_pci.h>
75 #include <sparc64/pci/schizoreg.h>
76 #include <sparc64/pci/schizovar.h>
80 static const struct schizo_desc *schizo_get_desc(device_t);
81 static void schizo_set_intr(struct schizo_softc *, u_int, u_int,
83 static void schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map,
85 static void ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map,
87 static void schizo_intr_enable(void *);
88 static void schizo_intr_disable(void *);
89 static void schizo_intr_assign(void *);
90 static void schizo_intr_clear(void *);
91 static int schizo_intr_register(struct schizo_softc *sc, u_int ino);
92 static int schizo_get_intrmap(struct schizo_softc *, u_int,
93 bus_addr_t *, bus_addr_t *);
94 static timecounter_get_t schizo_get_timecount;
96 /* Interrupt handlers */
97 static driver_filter_t schizo_pci_bus;
98 static driver_filter_t schizo_ue;
99 static driver_filter_t schizo_ce;
100 static driver_filter_t schizo_host_bus;
101 static driver_filter_t schizo_cdma;
104 static void schizo_iommu_init(struct schizo_softc *, int, uint32_t);
109 static device_probe_t schizo_probe;
110 static device_attach_t schizo_attach;
111 static bus_read_ivar_t schizo_read_ivar;
112 static bus_setup_intr_t schizo_setup_intr;
113 static bus_alloc_resource_t schizo_alloc_resource;
114 static bus_activate_resource_t schizo_activate_resource;
115 static bus_adjust_resource_t schizo_adjust_resource;
116 static bus_get_dma_tag_t schizo_get_dma_tag;
117 static pcib_maxslots_t schizo_maxslots;
118 static pcib_read_config_t schizo_read_config;
119 static pcib_write_config_t schizo_write_config;
120 static pcib_route_interrupt_t schizo_route_interrupt;
121 static ofw_bus_get_node_t schizo_get_node;
122 static ofw_pci_setup_device_t schizo_setup_device;
124 static device_method_t schizo_methods[] = {
125 /* Device interface */
126 DEVMETHOD(device_probe, schizo_probe),
127 DEVMETHOD(device_attach, schizo_attach),
128 DEVMETHOD(device_shutdown, bus_generic_shutdown),
129 DEVMETHOD(device_suspend, bus_generic_suspend),
130 DEVMETHOD(device_resume, bus_generic_resume),
133 DEVMETHOD(bus_read_ivar, schizo_read_ivar),
134 DEVMETHOD(bus_setup_intr, schizo_setup_intr),
135 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
136 DEVMETHOD(bus_alloc_resource, schizo_alloc_resource),
137 DEVMETHOD(bus_activate_resource, schizo_activate_resource),
138 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
139 DEVMETHOD(bus_adjust_resource, schizo_adjust_resource),
140 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
141 DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag),
144 DEVMETHOD(pcib_maxslots, schizo_maxslots),
145 DEVMETHOD(pcib_read_config, schizo_read_config),
146 DEVMETHOD(pcib_write_config, schizo_write_config),
147 DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt),
149 /* ofw_bus interface */
150 DEVMETHOD(ofw_bus_get_node, schizo_get_node),
152 /* ofw_pci interface */
153 DEVMETHOD(ofw_pci_setup_device, schizo_setup_device),
158 static devclass_t schizo_devclass;
160 DEFINE_CLASS_0(pcib, schizo_driver, schizo_methods,
161 sizeof(struct schizo_softc));
162 EARLY_DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0,
165 static SLIST_HEAD(, schizo_softc) schizo_softcs =
166 SLIST_HEAD_INITIALIZER(schizo_softcs);
168 static const struct intr_controller schizo_ic = {
175 struct schizo_icarg {
176 struct schizo_softc *sica_sc;
181 #define SCHIZO_CDMA_TIMEOUT 1 /* 1 second per try */
182 #define SCHIZO_CDMA_TRIES 15
183 #define SCHIZO_PERF_CNT_QLTY 100
185 #define SCHIZO_SPC_BARRIER(spc, sc, offs, len, flags) \
186 bus_barrier((sc)->sc_mem_res[(spc)], (offs), (len), (flags))
187 #define SCHIZO_SPC_READ_8(spc, sc, offs) \
188 bus_read_8((sc)->sc_mem_res[(spc)], (offs))
189 #define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \
190 bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v))
193 #define SCHIZO_SPC_SET(spc, sc, offs, reg, v) \
194 SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v))
196 #define SCHIZO_SPC_SET(spc, sc, offs, reg, v) do { \
197 device_printf((sc)->sc_dev, reg " 0x%016llx -> 0x%016llx\n", \
198 (unsigned long long)SCHIZO_SPC_READ_8((spc), (sc), (offs)), \
199 (unsigned long long)(v)); \
200 SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)); \
204 #define SCHIZO_PCI_READ_8(sc, offs) \
205 SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs))
206 #define SCHIZO_PCI_WRITE_8(sc, offs, v) \
207 SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v))
208 #define SCHIZO_CTRL_READ_8(sc, offs) \
209 SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs))
210 #define SCHIZO_CTRL_WRITE_8(sc, offs, v) \
211 SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v))
212 #define SCHIZO_PCICFG_READ_8(sc, offs) \
213 SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs))
214 #define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \
215 SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v))
216 #define SCHIZO_ICON_READ_8(sc, offs) \
217 SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs))
218 #define SCHIZO_ICON_WRITE_8(sc, offs, v) \
219 SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v))
221 #define SCHIZO_PCI_SET(sc, offs, v) \
222 SCHIZO_SPC_SET(STX_PCI, (sc), (offs), # offs, (v))
223 #define SCHIZO_CTRL_SET(sc, offs, v) \
224 SCHIZO_SPC_SET(STX_CTRL, (sc), (offs), # offs, (v))
227 const char *sd_string;
232 static const struct schizo_desc schizo_compats[] = {
233 { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" },
235 { "pci108e,8002", SCHIZO_MODE_XMS, "XMITS" },
237 { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" },
241 static const struct schizo_desc *
242 schizo_get_desc(device_t dev)
244 const struct schizo_desc *desc;
247 compat = ofw_bus_get_compat(dev);
250 for (desc = schizo_compats; desc->sd_string != NULL; desc++)
251 if (strcmp(desc->sd_string, compat) == 0)
257 schizo_probe(device_t dev)
261 dtype = ofw_bus_get_type(dev);
262 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 &&
263 schizo_get_desc(dev) != NULL) {
264 device_set_desc(dev, "Sun Host-PCI bridge");
271 schizo_attach(device_t dev)
273 struct ofw_pci_ranges *range;
274 const struct schizo_desc *desc;
275 struct schizo_softc *asc, *sc, *osc;
276 struct timecounter *tc;
277 uint64_t ino_bitmap, reg;
279 uint32_t prop, prop_array[2];
280 int i, j, mode, rid, tsbsize;
282 sc = device_get_softc(dev);
283 node = ofw_bus_get_node(dev);
284 desc = schizo_get_desc(dev);
285 mode = desc->sd_mode;
293 * The Schizo has three register banks:
294 * (0) per-PBM PCI configuration and status registers, but for bus B
295 * shared with the UPA64s interrupt mapping register banks
296 * (1) shared Schizo controller configuration and status registers
297 * (2) per-PBM PCI configuration space
299 * The Tomatillo has four register banks:
300 * (0) per-PBM PCI configuration and status registers
301 * (1) per-PBM Tomatillo controller configuration registers, but on
302 * machines having the `jbusppm' device shared with its Estar
303 * register bank for bus A
304 * (2) per-PBM PCI configuration space
305 * (3) per-PBM interrupt concentrator registers
307 sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >>
309 for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG);
312 sc->sc_mem_res[i] = bus_alloc_resource_any(dev,
313 SYS_RES_MEMORY, &rid,
314 (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 &&
315 i == STX_PCI) || i == STX_CTRL)) ||
316 (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 &&
317 i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE);
318 if (sc->sc_mem_res[i] == NULL)
319 panic("%s: could not allocate register bank %d",
324 * Match other Schizos that are already configured against
325 * the controller base physical address. This will be the
326 * same for a pair of devices that share register space.
329 SLIST_FOREACH(asc, &schizo_softcs, sc_link) {
330 if (rman_get_start(asc->sc_mem_res[STX_CTRL]) ==
331 rman_get_start(sc->sc_mem_res[STX_CTRL])) {
338 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF,
340 if (sc->sc_mtx == NULL)
341 panic("%s: could not malloc mutex", __func__);
342 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
344 if (sc->sc_mode != SCHIZO_MODE_SCZ)
345 panic("%s: no partner expected", __func__);
346 if (mtx_initialized(osc->sc_mtx) == 0)
347 panic("%s: mutex not initialized", __func__);
348 sc->sc_mtx = osc->sc_mtx;
351 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1)
352 panic("%s: could not determine IGN", __func__);
353 if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) ==
355 panic("%s: could not determine version", __func__);
356 if (mode == SCHIZO_MODE_XMS && OF_getprop(node, "module-revision#",
357 &sc->sc_mrev, sizeof(sc->sc_mrev)) == -1)
358 panic("%s: could not determine module-revision", __func__);
359 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
362 if (mode == SCHIZO_MODE_XMS && (SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL) &
363 XMS_PCI_CTRL_X_MODE) != 0) {
365 panic("PCI-X mode unsupported");
366 sc->sc_flags |= SCHIZO_FLAGS_XMODE;
369 device_printf(dev, "%s, version %d, ", desc->sd_name, sc->sc_ver);
370 if (mode == SCHIZO_MODE_XMS)
371 printf("module-revision %d, ", sc->sc_mrev);
372 printf("IGN %#x, bus %c, PCI%s mode, %dMHz\n", sc->sc_ign,
373 'A' + sc->sc_half, (sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ?
374 "-X" : "", prop / 1000 / 1000);
376 /* Set up the PCI interrupt retry timer. */
377 SCHIZO_PCI_SET(sc, STX_PCI_INTR_RETRY_TIM, 5);
379 /* Set up the PCI control register. */
380 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL);
381 reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK |
382 STX_PCI_CTRL_ARB_MASK);
383 reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN |
384 STX_PCI_CTRL_ERR_IEN;
385 if (OF_getproplen(node, "no-bus-parking") < 0)
386 reg |= STX_PCI_CTRL_ARB_PARK;
387 if (mode == SCHIZO_MODE_XMS && sc->sc_mrev == 1)
388 reg |= XMS_PCI_CTRL_XMITS10_ARB_MASK;
390 reg |= STX_PCI_CTRL_ARB_MASK;
391 if (mode == SCHIZO_MODE_TOM) {
392 reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL;
393 if (sc->sc_ver <= 1) /* revision <= 2.0 */
394 reg |= TOM_PCI_CTRL_DTO_IEN;
396 reg |= STX_PCI_CTRL_PTO;
397 } else if (mode == SCHIZO_MODE_XMS) {
398 SCHIZO_PCI_SET(sc, XMS_PCI_PARITY_DETECT, 0x3fff);
399 SCHIZO_PCI_SET(sc, XMS_PCI_UPPER_RETRY_COUNTER, 0x3e8);
400 reg |= XMS_PCI_CTRL_X_ERRINT_EN;
402 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, reg);
404 /* Set up the PCI diagnostic register. */
405 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG);
406 reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS |
407 STX_PCI_DIAG_INTRSYNC_DIS);
408 SCHIZO_PCI_SET(sc, STX_PCI_DIAG, reg);
411 * Enable DMA write parity error interrupts of version >= 7 (i.e.
412 * revision >= 2.5) Schizo and XMITS (enabling it on XMITS < 3.0 has
415 if ((mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 7) ||
416 mode == SCHIZO_MODE_XMS) {
417 reg = SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD);
418 reg |= SX_PCI_CFG_ICD_DMAW_PERR_IEN;
419 SCHIZO_PCI_SET(sc, SX_PCI_CFG_ICD, reg);
423 * On Tomatillo clear the I/O prefetch lengths (workaround for a
426 if (mode == SCHIZO_MODE_TOM)
427 SCHIZO_PCI_SET(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW |
428 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM |
429 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL);
432 * Hunt through all the interrupt mapping regs and register
433 * the interrupt controller for our interrupt vectors. We do
434 * this early in order to be able to catch stray interrupts.
435 * This is complicated by the fact that a pair of Schizo PBMs
438 i = OF_getprop(node, "ino-bitmap", (void *)prop_array,
441 ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0];
444 * If the ino-bitmap property is missing, just provide the
445 * default set of interrupts for this controller and let
446 * schizo_setup_intr() take care of child interrupts.
448 if (sc->sc_half == 0)
449 ino_bitmap = (1ULL << STX_UE_INO) |
450 (1ULL << STX_CE_INO) |
451 (1ULL << STX_PCIERR_A_INO) |
452 (1ULL << STX_BUS_INO);
454 ino_bitmap = 1ULL << STX_PCIERR_B_INO;
456 for (i = 0; i <= STX_MAX_INO; i++) {
457 if ((ino_bitmap & (1ULL << i)) == 0)
459 if (i == STX_FB0_INO || i == STX_FB1_INO)
460 /* Leave for upa(4). */
462 j = schizo_intr_register(sc, i);
464 device_printf(dev, "could not register interrupt "
465 "controller for INO %d (%d)\n", i, j);
469 * Setup Safari/JBus performance counter 0 in bus cycle counting
470 * mode as timecounter. Unfortunately, this is broken with at
471 * least the version 4 Tomatillos found in Fire V120 and Blade
472 * 1500, which apparently actually count some different event at
473 * ~0.5 and 3MHz respectively instead (also when running in full
474 * power mode). Besides, one counter seems to be shared by a
475 * "pair" of Tomatillos, too.
477 if (sc->sc_half == 0) {
478 SCHIZO_CTRL_SET(sc, STX_CTRL_PERF,
479 (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) |
480 (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT));
481 tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO);
483 panic("%s: could not malloc timecounter", __func__);
484 tc->tc_get_timecount = schizo_get_timecount;
485 tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK;
486 if (OF_getprop(OF_peer(0), "clock-frequency", &prop,
488 panic("%s: could not determine clock frequency",
490 tc->tc_frequency = prop;
491 tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF);
492 if (mode == SCHIZO_MODE_SCZ)
493 tc->tc_quality = SCHIZO_PERF_CNT_QLTY;
495 tc->tc_quality = -SCHIZO_PERF_CNT_QLTY;
501 * Set up the IOMMU. Schizo, Tomatillo and XMITS all have
502 * one per PBM. Schizo and XMITS additionally have a streaming
503 * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's
504 * affected by several errata though. However, except for context
505 * flushes, taking advantage of it should be okay even with those.
507 memcpy(&sc->sc_dma_methods, &iommu_dma_methods,
508 sizeof(sc->sc_dma_methods));
509 sc->sc_is.sis_sc = sc;
510 sc->sc_is.sis_is.is_flags = IOMMU_PRESERVE_PROM;
511 sc->sc_is.sis_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS);
512 sc->sc_is.sis_is.is_sb[0] = sc->sc_is.sis_is.is_sb[1] = 0;
513 if (OF_getproplen(node, "no-streaming-cache") < 0)
514 sc->sc_is.sis_is.is_sb[0] = STX_PCI_STRBUF;
517 case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \
521 i = OF_getprop(node, "virtual-dma", (void *)prop_array,
523 if (i == -1 || i != sizeof(prop_array))
524 schizo_iommu_init(sc, 7, -1);
526 switch (prop_array[1]) {
536 panic("%s: unsupported DVMA size 0x%x",
537 __func__, prop_array[1]);
540 schizo_iommu_init(sc, tsbsize, prop_array[0]);
545 /* Initialize memory and I/O rmans. */
546 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
547 sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports";
548 if (rman_init(&sc->sc_pci_io_rman) != 0 ||
549 rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0)
550 panic("%s: failed to set up I/O rman", __func__);
551 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
552 sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory";
553 if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
554 rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0)
555 panic("%s: failed to set up memory rman", __func__);
557 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range);
559 * Make sure that the expected ranges are present. The
560 * OFW_PCI_CS_MEM64 one is not currently used though.
563 panic("%s: unsupported number of ranges", __func__);
565 * Find the addresses of the various bus spaces.
566 * There should not be multiple ones of one kind.
567 * The physical start addresses of the ranges are the configuration,
568 * memory and I/O handles.
570 for (i = 0; i < STX_NRANGE; i++) {
571 j = OFW_PCI_RANGE_CS(&range[i]);
572 if (sc->sc_pci_bh[j] != 0)
573 panic("%s: duplicate range for space %d",
575 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]);
577 free(range, M_OFWPROP);
579 /* Register the softc, this is needed for paired Schizos. */
580 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link);
582 /* Allocate our tags. */
583 sc->sc_pci_iot = sparc64_alloc_bus_tag(NULL, PCI_IO_BUS_SPACE);
584 if (sc->sc_pci_iot == NULL)
585 panic("%s: could not allocate PCI I/O tag", __func__);
586 sc->sc_pci_cfgt = sparc64_alloc_bus_tag(NULL, PCI_CONFIG_BUS_SPACE);
587 if (sc->sc_pci_cfgt == NULL)
588 panic("%s: could not allocate PCI configuration space tag",
590 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
591 sc->sc_is.sis_is.is_pmaxaddr, ~0, NULL, NULL,
592 sc->sc_is.sis_is.is_pmaxaddr, 0xff, 0xffffffff, 0, NULL, NULL,
593 &sc->sc_pci_dmat) != 0)
594 panic("%s: could not create PCI DMA tag", __func__);
595 /* Customize the tag. */
596 sc->sc_pci_dmat->dt_cookie = &sc->sc_is;
597 sc->sc_pci_dmat->dt_mt = &sc->sc_dma_methods;
600 * Get the bus range from the firmware.
601 * NB: Tomatillos don't support PCI bus reenumeration.
603 i = OF_getprop(node, "bus-range", (void *)prop_array,
606 panic("%s: could not get bus-range", __func__);
607 if (i != sizeof(prop_array))
608 panic("%s: broken bus-range (%d)", __func__, i);
609 sc->sc_pci_secbus = prop_array[0];
610 sc->sc_pci_subbus = prop_array[1];
612 device_printf(dev, "bus range %u to %u; PCI bus %d\n",
613 sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus);
615 /* Clear any pending PCI error bits. */
616 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC,
617 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus,
618 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2);
619 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL));
620 SCHIZO_PCI_SET(sc, STX_PCI_AFSR, SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR));
623 * Establish handlers for interesting interrupts...
624 * Someone at Sun clearly was smoking crack; with Schizos PCI
625 * bus error interrupts for one PBM can be routed to the other
626 * PBM though we obviously need to use the softc of the former
627 * as the argument for the interrupt handler and the softc of
628 * the latter as the argument for the interrupt controller.
630 if (sc->sc_half == 0) {
631 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 ||
632 (osc != NULL && ((struct schizo_icarg *)intr_vectors[
633 INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)->
636 * We are the driver for PBM A and either also
637 * registered the interrupt controller for us or
638 * the driver for PBM B has probed first and
639 * registered it for us.
641 schizo_set_intr(sc, 0, STX_PCIERR_A_INO,
643 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 &&
646 * We are the driver for PBM A but registered
647 * the interrupt controller for PBM B, i.e. the
648 * driver for PBM B attached first but couldn't
649 * set up a handler for PBM B.
651 schizo_set_intr(osc, 0, STX_PCIERR_B_INO,
654 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 ||
655 (osc != NULL && ((struct schizo_icarg *)intr_vectors[
656 INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)->
659 * We are the driver for PBM B and either also
660 * registered the interrupt controller for us or
661 * the driver for PBM A has probed first and
662 * registered it for us.
664 schizo_set_intr(sc, 0, STX_PCIERR_B_INO,
666 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 &&
669 * We are the driver for PBM B but registered
670 * the interrupt controller for PBM A, i.e. the
671 * driver for PBM A attached first but couldn't
672 * set up a handler for PBM A.
674 schizo_set_intr(osc, 0, STX_PCIERR_A_INO,
677 if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0)
678 schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue);
679 if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0)
680 schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce);
681 if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0)
682 schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus);
685 * According to the Schizo Errata I-13, consistent DMA flushing/
686 * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges,
687 * so we can't use it and need to live with the consequences. With
688 * Schizo version >= 5, CDMA flushing/syncing is usable but requires
689 * the workaround described in Schizo Errata I-23. With Tomatillo
690 * and XMITS, CDMA flushing/syncing works as expected, Tomatillo
691 * version <= 4 (i.e. revision <= 2.3) bridges additionally require
692 * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though.
694 if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) ||
695 sc->sc_mode == SCHIZO_MODE_TOM ||
696 sc->sc_mode == SCHIZO_MODE_XMS) {
697 if (sc->sc_mode == SCHIZO_MODE_SCZ) {
698 sc->sc_dma_methods.dm_dmamap_sync =
700 sc->sc_cdma_state = SCHIZO_CDMA_STATE_IDLE;
702 * Some firmware versions include the CDMA interrupt
703 * at RID 4 but most don't. With the latter we add
704 * it ourselves at the spare RID 5.
706 i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ,
708 if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) {
709 sc->sc_cdma_vec = INTMAP_VEC(sc->sc_ign, i);
710 (void)schizo_get_intrmap(sc, i,
711 &sc->sc_cdma_map, &sc->sc_cdma_clr);
712 schizo_set_intr(sc, 4, i, schizo_cdma);
714 i = STX_CDMA_A_INO + sc->sc_half;
715 sc->sc_cdma_vec = INTMAP_VEC(sc->sc_ign, i);
716 if (bus_set_resource(dev, SYS_RES_IRQ, 5,
717 sc->sc_cdma_vec, 1) != 0)
718 panic("%s: failed to add CDMA "
719 "interrupt", __func__);
720 j = schizo_intr_register(sc, i);
722 panic("%s: could not register "
723 "interrupt controller for CDMA "
724 "(%d)", __func__, j);
725 (void)schizo_get_intrmap(sc, i,
726 &sc->sc_cdma_map, &sc->sc_cdma_clr);
727 schizo_set_intr(sc, 5, i, schizo_cdma);
730 if (sc->sc_mode == SCHIZO_MODE_XMS)
731 mtx_init(&sc->sc_sync_mtx, "pcib_sync_mtx",
733 sc->sc_sync_val = 1ULL << (STX_PCIERR_A_INO +
735 sc->sc_dma_methods.dm_dmamap_sync =
738 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4)
739 sc->sc_flags |= SCHIZO_FLAGS_BSWAR;
743 * Set the latency timer register as this isn't always done by the
746 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC,
747 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
749 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
751 #define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \
752 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \
753 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \
754 (name), CTLFLAG_RD, (arg), 0, (desc))
756 SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce,
757 "DMA correctable errors");
758 SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal,
759 "PCI bus non-fatal errors");
761 #undef SCHIZO_SYSCTL_ADD_UINT
763 device_add_child(dev, "pci", -1);
764 return (bus_generic_attach(dev));
768 schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino,
769 driver_filter_t handler)
775 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev,
776 SYS_RES_IRQ, &rid, RF_ACTIVE);
777 if (sc->sc_irq_res[index] == NULL ||
778 INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino ||
779 INTIGN(vec) != sc->sc_ign ||
780 intr_vectors[vec].iv_ic != &schizo_ic ||
781 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index],
782 INTR_TYPE_MISC | INTR_BRIDGE, handler, NULL, sc,
783 &sc->sc_ihand[index]) != 0)
784 panic("%s: failed to set up interrupt %d", __func__, index);
788 schizo_intr_register(struct schizo_softc *sc, u_int ino)
790 struct schizo_icarg *sica;
791 bus_addr_t intrclr, intrmap;
794 if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0)
796 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT);
800 sica->sica_map = intrmap;
801 sica->sica_clr = intrclr;
803 device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n",
804 ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap),
807 error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino),
810 free(sica, M_DEVBUF);
815 schizo_get_intrmap(struct schizo_softc *sc, u_int ino,
816 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr)
818 bus_addr_t intrclr, intrmap;
822 * XXX we only look for INOs rather than INRs since the firmware
823 * may not provide the IGN and the IGN is constant for all devices
824 * on that PCI controller.
827 if (ino > STX_MAX_INO) {
828 device_printf(sc->sc_dev, "out of range INO %d requested\n",
833 intrmap = STX_PCI_IMAP_BASE + (ino << 3);
834 intrclr = STX_PCI_ICLR_BASE + (ino << 3);
835 mr = SCHIZO_PCI_READ_8(sc, intrmap);
836 if (INTINO(mr) != ino) {
837 device_printf(sc->sc_dev,
838 "interrupt map entry does not match INO (%d != %d)\n",
839 (int)INTINO(mr), ino);
843 if (intrmapptr != NULL)
844 *intrmapptr = intrmap;
845 if (intrclrptr != NULL)
846 *intrclrptr = intrclr;
854 schizo_pci_bus(void *arg)
856 struct schizo_softc *sc = arg;
857 uint64_t afar, afsr, csr, iommu, xstat;
863 mtx_lock_spin(sc->sc_mtx);
865 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR);
866 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR);
867 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL);
868 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU);
869 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0)
870 xstat = SCHIZO_PCI_READ_8(sc, XMS_PCI_X_ERR_STAT);
873 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus,
874 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2);
877 * IOMMU errors are only fatal on Tomatillo and there also only if
878 * target abort was not signaled.
880 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 &&
881 (iommu & TOM_PCI_IOMMU_ERR) != 0 &&
882 ((status & PCIM_STATUS_STABORT) == 0 ||
883 ((iommu & TOM_PCI_IOMMU_ERRMASK) != TOM_PCI_IOMMU_INVALID_ERR &&
884 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) == 0 &&
885 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) == 0)))
887 else if ((status & PCIM_STATUS_STABORT) != 0)
889 if ((status & (PCIM_STATUS_PERR | PCIM_STATUS_SERR |
890 PCIM_STATUS_RMABORT | PCIM_STATUS_RTABORT |
891 PCIM_STATUS_MDPERR)) != 0 ||
892 (csr & (SCZ_PCI_CTRL_BUS_UNUS | TOM_PCI_CTRL_DTO_ERR |
893 STX_PCI_CTRL_TTO_ERR | STX_PCI_CTRL_RTRY_ERR |
894 SCZ_PCI_CTRL_SBH_ERR | STX_PCI_CTRL_SERR)) != 0 ||
895 (afsr & (STX_PCI_AFSR_P_MA | STX_PCI_AFSR_P_TA |
896 STX_PCI_AFSR_P_RTRY | STX_PCI_AFSR_P_PERR | STX_PCI_AFSR_P_TTO |
897 STX_PCI_AFSR_P_UNUS)) != 0)
899 if (xstat & (XMS_PCI_X_ERR_STAT_P_SC_DSCRD |
900 XMS_PCI_X_ERR_STAT_P_SC_TTO | XMS_PCI_X_ERR_STAT_P_SDSTAT |
901 XMS_PCI_X_ERR_STAT_P_SMMU | XMS_PCI_X_ERR_STAT_P_CDSTAT |
902 XMS_PCI_X_ERR_STAT_P_CMMU | XMS_PCI_X_ERR_STAT_PERR_RCV))
905 sc->sc_stats_pci_non_fatal++;
907 device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx "
908 "PCI CSR %#llx IOMMU %#llx PCI-X %#llx STATUS %#x\n",
909 'A' + sc->sc_half, (unsigned long long)afar,
910 (unsigned long long)afsr, (unsigned long long)csr,
911 (unsigned long long)iommu, (unsigned long long)xstat, status);
913 /* Clear the error bits that we caught. */
914 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE,
915 STX_CS_FUNC, PCIR_STATUS, status, 2);
916 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr);
917 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr);
918 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu);
919 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0)
920 SCHIZO_PCI_WRITE_8(sc, XMS_PCI_X_ERR_STAT, xstat);
922 mtx_unlock_spin(sc->sc_mtx);
925 panic("%s: fatal PCI bus error",
926 device_get_nameunit(sc->sc_dev));
927 return (FILTER_HANDLED);
933 struct schizo_softc *sc = arg;
937 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR);
938 for (i = 0; i < 1000; i++)
939 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) &
940 STX_CTRL_CE_AFSR_ERRPNDG) == 0)
942 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx",
943 device_get_nameunit(sc->sc_dev), (unsigned long long)afar,
944 (unsigned long long)afsr);
945 return (FILTER_HANDLED);
951 struct schizo_softc *sc = arg;
955 mtx_lock_spin(sc->sc_mtx);
957 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR);
958 for (i = 0; i < 1000; i++)
959 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) &
960 STX_CTRL_CE_AFSR_ERRPNDG) == 0)
962 sc->sc_stats_dma_ce++;
963 device_printf(sc->sc_dev,
964 "correctable DMA error AFAR %#llx AFSR %#llx\n",
965 (unsigned long long)afar, (unsigned long long)afsr);
967 /* Clear the error bits that we caught. */
968 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr);
970 mtx_unlock_spin(sc->sc_mtx);
972 return (FILTER_HANDLED);
976 schizo_host_bus(void *arg)
978 struct schizo_softc *sc = arg;
981 errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG);
982 panic("%s: %s error %#llx", device_get_nameunit(sc->sc_dev),
983 sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari",
984 (unsigned long long)errlog);
985 return (FILTER_HANDLED);
989 schizo_cdma(void *arg)
991 struct schizo_softc *sc = arg;
993 atomic_cmpset_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_PENDING,
994 SCHIZO_CDMA_STATE_RECEIVED);
995 return (FILTER_HANDLED);
999 schizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase)
1002 /* Punch in our copies. */
1003 sc->sc_is.sis_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]);
1004 sc->sc_is.sis_is.is_bushandle =
1005 rman_get_bushandle(sc->sc_mem_res[STX_PCI]);
1006 sc->sc_is.sis_is.is_iommu = STX_PCI_IOMMU;
1007 sc->sc_is.sis_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG;
1008 sc->sc_is.sis_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG;
1009 sc->sc_is.sis_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG;
1010 sc->sc_is.sis_is.is_dva = STX_PCI_IOMMU_SVADIAG;
1011 sc->sc_is.sis_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG;
1013 iommu_init(device_get_nameunit(sc->sc_dev),
1014 (struct iommu_state *)&sc->sc_is, tsbsize, dvmabase, 0);
1018 schizo_maxslots(device_t dev)
1020 struct schizo_softc *sc;
1022 sc = device_get_softc(dev);
1023 if (sc->sc_mode == SCHIZO_MODE_SCZ)
1024 return (sc->sc_half == 0 ? 4 : 6);
1026 /* XXX: is this correct? */
1027 return (PCI_SLOTMAX);
1031 schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
1034 struct schizo_softc *sc;
1035 bus_space_handle_t bh;
1042 sc = device_get_softc(dev);
1043 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
1044 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
1048 * The Schizo bridges contain a dupe of their header at 0x80.
1050 if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus &&
1051 slot == STX_CS_DEVICE && func == STX_CS_FUNC &&
1055 offset = STX_CONF_OFF(bus, slot, func, reg);
1056 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
1059 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
1063 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
1067 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
1071 panic("%s: bad width", __func__);
1077 printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
1078 __func__, bus, slot, func, reg);
1086 schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func,
1087 u_int reg, uint32_t val, int width)
1089 struct schizo_softc *sc;
1090 bus_space_handle_t bh;
1093 sc = device_get_softc(dev);
1094 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
1095 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
1098 offset = STX_CONF_OFF(bus, slot, func, reg);
1099 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
1102 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
1105 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
1108 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
1111 panic("%s: bad width", __func__);
1117 schizo_route_interrupt(device_t bridge, device_t dev, int pin)
1119 struct schizo_softc *sc;
1120 struct ofw_pci_register reg;
1121 ofw_pci_intr_t pintr, mintr;
1123 sc = device_get_softc(bridge);
1125 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
1126 ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
1130 device_printf(bridge, "could not route pin %d for device %d.%d\n",
1131 pin, pci_get_slot(dev), pci_get_function(dev));
1132 return (PCI_INVALID_IRQ);
1136 schizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1138 struct schizo_softc *sc;
1140 sc = device_get_softc(dev);
1142 case PCIB_IVAR_DOMAIN:
1143 *result = device_get_unit(dev);
1146 *result = sc->sc_pci_secbus;
1153 schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
1155 struct timeval cur, end;
1156 struct schizo_iommu_state *sis = dt->dt_cookie;
1157 struct schizo_softc *sc = sis->sis_sc;
1163 if ((map->dm_flags & DMF_STREAMED) != 0) {
1164 iommu_dma_methods.dm_dmamap_sync(dt, map, op);
1168 if ((map->dm_flags & DMF_LOADED) == 0)
1171 if ((op & BUS_DMASYNC_POSTREAD) != 0) {
1173 * Note that in order to allow this function to be called from
1174 * filters we would need to use a spin mutex for serialization
1175 * but given that these disable interrupts we have to emulate
1179 KASSERT((rdpr(pstate) & PSTATE_IE) != 0,
1180 ("%s: interrupts disabled", __func__));
1181 KASSERT((pil = rdpr(pil)) <= PIL_BRIDGE,
1182 ("%s: PIL too low (%ld)", __func__, pil));
1183 for (; atomic_cmpset_acq_32(&sc->sc_cdma_state,
1184 SCHIZO_CDMA_STATE_IDLE, SCHIZO_CDMA_STATE_PENDING) == 0;)
1186 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_map,
1187 INTMAP_ENABLE(sc->sc_cdma_vec, PCPU_GET(mid)));
1188 for (i = 0; i < SCHIZO_CDMA_TRIES; i++) {
1190 printf("%s: try %d\n", __func__, i);
1191 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr,
1194 end.tv_sec = SCHIZO_CDMA_TIMEOUT;
1196 timevaladd(&end, &cur);
1197 for (; (res = atomic_cmpset_rel_32(&sc->sc_cdma_state,
1198 SCHIZO_CDMA_STATE_RECEIVED,
1199 SCHIZO_CDMA_STATE_IDLE)) == 0 &&
1200 timevalcmp(&cur, &end, <=);)
1206 panic("%s: DMA does not sync", __func__);
1210 if ((op & BUS_DMASYNC_PREWRITE) != 0)
1215 ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
1217 static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE);
1218 struct timeval cur, end;
1219 struct schizo_iommu_state *sis = dt->dt_cookie;
1220 struct schizo_softc *sc = sis->sis_sc;
1223 if ((map->dm_flags & DMF_STREAMED) != 0) {
1224 iommu_dma_methods.dm_dmamap_sync(dt, map, op);
1228 if ((map->dm_flags & DMF_LOADED) == 0)
1231 if ((op & BUS_DMASYNC_POSTREAD) != 0) {
1232 if (sc->sc_mode == SCHIZO_MODE_XMS)
1233 mtx_lock_spin(&sc->sc_sync_mtx);
1234 SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND,
1239 timevaladd(&end, &cur);
1240 for (; ((reg = SCHIZO_PCI_READ_8(sc,
1241 TOMXMS_PCI_DMA_SYNC_PEND)) & sc->sc_sync_val) != 0 &&
1242 timevalcmp(&cur, &end, <=);)
1244 if ((reg & sc->sc_sync_val) != 0)
1245 panic("%s: DMA does not sync", __func__);
1246 if (sc->sc_mode == SCHIZO_MODE_XMS)
1247 mtx_unlock_spin(&sc->sc_sync_mtx);
1248 else if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) {
1251 wr(fprs, reg | FPRS_FEF, 0);
1252 __asm __volatile("stda %%f0, [%0] %1"
1253 : : "r" (buf), "n" (ASI_BLK_COMMIT_S));
1261 if ((op & BUS_DMASYNC_PREWRITE) != 0)
1266 schizo_intr_enable(void *arg)
1268 struct intr_vector *iv = arg;
1269 struct schizo_icarg *sica = iv->iv_icarg;
1271 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map,
1272 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
1276 schizo_intr_disable(void *arg)
1278 struct intr_vector *iv = arg;
1279 struct schizo_icarg *sica = iv->iv_icarg;
1281 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec);
1285 schizo_intr_assign(void *arg)
1287 struct intr_vector *iv = arg;
1288 struct schizo_icarg *sica = iv->iv_icarg;
1290 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID(
1291 SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid));
1295 schizo_intr_clear(void *arg)
1297 struct intr_vector *iv = arg;
1298 struct schizo_icarg *sica = iv->iv_icarg;
1300 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE);
1304 schizo_setup_intr(device_t dev, device_t child, struct resource *ires,
1305 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
1308 struct schizo_softc *sc;
1312 sc = device_get_softc(dev);
1314 * Make sure the vector is fully specified.
1316 vec = rman_get_start(ires);
1317 if (INTIGN(vec) != sc->sc_ign) {
1318 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
1322 if (intr_vectors[vec].iv_ic == &schizo_ic) {
1324 * Ensure we use the right softc in case the interrupt
1325 * is routed to our companion PBM for some odd reason.
1327 sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)->
1329 } else if (intr_vectors[vec].iv_ic == NULL) {
1331 * Work around broken firmware which misses entries in
1334 error = schizo_intr_register(sc, INTINO(vec));
1336 device_printf(dev, "could not register interrupt "
1337 "controller for vector 0x%lx (%d)\n", vec, error);
1341 device_printf(dev, "belatedly registered as "
1342 "interrupt controller for vector 0x%lx\n", vec);
1345 "invalid interrupt controller for vector 0x%lx\n", vec);
1348 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
1352 static struct resource *
1353 schizo_alloc_resource(device_t bus, device_t child, int type, int *rid,
1354 u_long start, u_long end, u_long count, u_int flags)
1356 struct schizo_softc *sc;
1357 struct resource *rv;
1360 sc = device_get_softc(bus);
1364 * XXX: Don't accept blank ranges for now, only single
1365 * interrupts. The other case should not happen with
1366 * the MI PCI code...
1367 * XXX: This may return a resource that is out of the
1368 * range that was specified. Is this correct...?
1371 panic("%s: XXX: interrupt range", __func__);
1372 start = end = INTMAP_VEC(sc->sc_ign, end);
1373 return (bus_generic_alloc_resource(bus, child, type, rid,
1374 start, end, count, flags));
1375 case SYS_RES_MEMORY:
1376 rm = &sc->sc_pci_mem_rman;
1378 case SYS_RES_IOPORT:
1379 rm = &sc->sc_pci_io_rman;
1385 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE,
1389 rman_set_rid(rv, *rid);
1391 if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child, type,
1393 rman_release_resource(rv);
1400 schizo_activate_resource(device_t bus, device_t child, int type, int rid,
1403 struct schizo_softc *sc;
1404 struct bus_space_tag *tag;
1406 sc = device_get_softc(bus);
1409 return (bus_generic_activate_resource(bus, child, type, rid,
1411 case SYS_RES_MEMORY:
1412 tag = sparc64_alloc_bus_tag(r, PCI_MEMORY_BUS_SPACE);
1415 rman_set_bustag(r, tag);
1416 rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_MEM32] +
1419 case SYS_RES_IOPORT:
1420 rman_set_bustag(r, sc->sc_pci_iot);
1421 rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_IO] +
1425 return (rman_activate_resource(r));
1429 schizo_adjust_resource(device_t bus, device_t child, int type,
1430 struct resource *r, u_long start, u_long end)
1432 struct schizo_softc *sc;
1435 sc = device_get_softc(bus);
1438 return (bus_generic_adjust_resource(bus, child, type, r,
1440 case SYS_RES_MEMORY:
1441 rm = &sc->sc_pci_mem_rman;
1443 case SYS_RES_IOPORT:
1444 rm = &sc->sc_pci_io_rman;
1449 if (rman_is_region_manager(r, rm) == 0)
1451 return (rman_adjust_resource(r, start, end));
1454 static bus_dma_tag_t
1455 schizo_get_dma_tag(device_t bus, device_t child __unused)
1457 struct schizo_softc *sc;
1459 sc = device_get_softc(bus);
1460 return (sc->sc_pci_dmat);
1464 schizo_get_node(device_t bus, device_t child __unused)
1466 struct schizo_softc *sc;
1468 sc = device_get_softc(bus);
1469 /* We only have one child, the PCI bus, which needs our own node. */
1470 return (sc->sc_node);
1474 schizo_setup_device(device_t bus, device_t child)
1476 struct schizo_softc *sc;
1480 sc = device_get_softc(bus);
1482 * Disable bus parking in order to work around a bus hang caused by
1483 * Casinni/Skyhawk combinations.
1485 if (OF_getproplen(ofw_bus_get_node(child), "pci-req-removal") >= 0)
1486 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc,
1487 STX_PCI_CTRL) & ~STX_PCI_CTRL_ARB_PARK);
1489 if (sc->sc_mode == SCHIZO_MODE_XMS) {
1490 /* XMITS NCPQ WAR: set outstanding split transactions to 1. */
1491 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 &&
1492 (pci_read_config(child, PCIR_HDRTYPE, 1) &
1493 PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE &&
1494 pci_find_cap(child, PCIY_PCIX, &capreg) == 0)
1495 pci_write_config(child, capreg + PCIXR_COMMAND,
1496 pci_read_config(child, capreg + PCIXR_COMMAND,
1498 /* XMITS 3.x WAR: set BUGCNTL iff value is unexpected. */
1499 if (sc->sc_mrev >= 4) {
1500 reg = ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ?
1501 0xa0UL : 0xffUL) << XMS_PCI_X_DIAG_BUGCNTL_SHIFT;
1502 if ((SCHIZO_PCI_READ_8(sc, XMS_PCI_X_DIAG) &
1503 XMS_PCI_X_DIAG_BUGCNTL_MASK) != reg)
1504 SCHIZO_PCI_SET(sc, XMS_PCI_X_DIAG, reg);
1510 schizo_get_timecount(struct timecounter *tc)
1512 struct schizo_softc *sc;
1515 return ((SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) &
1516 (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)) >>
1517 STX_CTRL_PERF_CNT_CNT0_SHIFT);