2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2011 by Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1, `Tomatillo' JBus to
39 * PCI 2.2 and `XMITS' Fireplane/Safari to PCI-X bridges
42 #include "opt_ofw_pci.h"
43 #include "opt_schizo.h"
45 #include <sys/param.h>
46 #include <sys/systm.h>
48 #include <sys/kernel.h>
50 #include <sys/malloc.h>
51 #include <sys/module.h>
52 #include <sys/mutex.h>
55 #include <sys/sysctl.h>
57 #include <sys/timetc.h>
59 #include <dev/ofw/ofw_bus.h>
60 #include <dev/ofw/openfirm.h>
62 #include <machine/bus.h>
63 #include <machine/bus_common.h>
64 #include <machine/bus_private.h>
65 #include <machine/iommureg.h>
66 #include <machine/iommuvar.h>
67 #include <machine/resource.h>
69 #include <dev/pci/pcireg.h>
70 #include <dev/pci/pcivar.h>
71 #include <dev/pci/pcib_private.h>
73 #include <sparc64/pci/ofw_pci.h>
74 #include <sparc64/pci/schizoreg.h>
75 #include <sparc64/pci/schizovar.h>
79 static const struct schizo_desc *schizo_get_desc(device_t);
80 static void schizo_set_intr(struct schizo_softc *, u_int, u_int,
82 static void schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map,
84 static void ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map,
86 static void schizo_intr_enable(void *);
87 static void schizo_intr_disable(void *);
88 static void schizo_intr_assign(void *);
89 static void schizo_intr_clear(void *);
90 static int schizo_intr_register(struct schizo_softc *sc, u_int ino);
91 static int schizo_get_intrmap(struct schizo_softc *, u_int,
92 bus_addr_t *, bus_addr_t *);
93 static timecounter_get_t schizo_get_timecount;
95 /* Interrupt handlers */
96 static driver_filter_t schizo_pci_bus;
97 static driver_filter_t schizo_ue;
98 static driver_filter_t schizo_ce;
99 static driver_filter_t schizo_host_bus;
100 static driver_filter_t schizo_cdma;
103 static void schizo_iommu_init(struct schizo_softc *, int, uint32_t);
108 static device_probe_t schizo_probe;
109 static device_attach_t schizo_attach;
110 static bus_setup_intr_t schizo_setup_intr;
111 static bus_alloc_resource_t schizo_alloc_resource;
112 static pcib_maxslots_t schizo_maxslots;
113 static pcib_read_config_t schizo_read_config;
114 static pcib_write_config_t schizo_write_config;
115 static pcib_route_interrupt_t schizo_route_interrupt;
116 static ofw_pci_setup_device_t schizo_setup_device;
118 static device_method_t schizo_methods[] = {
119 /* Device interface */
120 DEVMETHOD(device_probe, schizo_probe),
121 DEVMETHOD(device_attach, schizo_attach),
122 DEVMETHOD(device_shutdown, bus_generic_shutdown),
123 DEVMETHOD(device_suspend, bus_generic_suspend),
124 DEVMETHOD(device_resume, bus_generic_resume),
127 DEVMETHOD(bus_read_ivar, ofw_pci_read_ivar),
128 DEVMETHOD(bus_setup_intr, schizo_setup_intr),
129 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
130 DEVMETHOD(bus_alloc_resource, schizo_alloc_resource),
131 DEVMETHOD(bus_activate_resource, ofw_pci_activate_resource),
132 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
133 DEVMETHOD(bus_adjust_resource, ofw_pci_adjust_resource),
134 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
135 DEVMETHOD(bus_get_dma_tag, ofw_pci_get_dma_tag),
138 DEVMETHOD(pcib_maxslots, schizo_maxslots),
139 DEVMETHOD(pcib_read_config, schizo_read_config),
140 DEVMETHOD(pcib_write_config, schizo_write_config),
141 DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt),
142 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
144 /* ofw_bus interface */
145 DEVMETHOD(ofw_bus_get_node, ofw_pci_get_node),
147 /* ofw_pci interface */
148 DEVMETHOD(ofw_pci_setup_device, schizo_setup_device),
153 static devclass_t schizo_devclass;
155 DEFINE_CLASS_0(pcib, schizo_driver, schizo_methods,
156 sizeof(struct schizo_softc));
157 EARLY_DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0,
160 static SLIST_HEAD(, schizo_softc) schizo_softcs =
161 SLIST_HEAD_INITIALIZER(schizo_softcs);
163 static const struct intr_controller schizo_ic = {
170 struct schizo_icarg {
171 struct schizo_softc *sica_sc;
176 #define SCHIZO_CDMA_TIMEOUT 1 /* 1 second per try */
177 #define SCHIZO_CDMA_TRIES 15
178 #define SCHIZO_PERF_CNT_QLTY 100
180 #define SCHIZO_SPC_BARRIER(spc, sc, offs, len, flags) \
181 bus_barrier((sc)->sc_mem_res[(spc)], (offs), (len), (flags))
182 #define SCHIZO_SPC_READ_8(spc, sc, offs) \
183 bus_read_8((sc)->sc_mem_res[(spc)], (offs))
184 #define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \
185 bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v))
188 #define SCHIZO_SPC_SET(spc, sc, offs, reg, v) \
189 SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v))
191 #define SCHIZO_SPC_SET(spc, sc, offs, reg, v) do { \
192 device_printf((sc)->sc_dev, reg " 0x%016llx -> 0x%016llx\n", \
193 (unsigned long long)SCHIZO_SPC_READ_8((spc), (sc), (offs)), \
194 (unsigned long long)(v)); \
195 SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)); \
199 #define SCHIZO_PCI_READ_8(sc, offs) \
200 SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs))
201 #define SCHIZO_PCI_WRITE_8(sc, offs, v) \
202 SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v))
203 #define SCHIZO_CTRL_READ_8(sc, offs) \
204 SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs))
205 #define SCHIZO_CTRL_WRITE_8(sc, offs, v) \
206 SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v))
207 #define SCHIZO_PCICFG_READ_8(sc, offs) \
208 SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs))
209 #define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \
210 SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v))
211 #define SCHIZO_ICON_READ_8(sc, offs) \
212 SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs))
213 #define SCHIZO_ICON_WRITE_8(sc, offs, v) \
214 SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v))
216 #define SCHIZO_PCI_SET(sc, offs, v) \
217 SCHIZO_SPC_SET(STX_PCI, (sc), (offs), # offs, (v))
218 #define SCHIZO_CTRL_SET(sc, offs, v) \
219 SCHIZO_SPC_SET(STX_CTRL, (sc), (offs), # offs, (v))
222 const char *sd_string;
227 static const struct schizo_desc schizo_compats[] = {
228 { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" },
230 { "pci108e,8002", SCHIZO_MODE_XMS, "XMITS" },
232 { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" },
236 static const struct schizo_desc *
237 schizo_get_desc(device_t dev)
239 const struct schizo_desc *desc;
242 compat = ofw_bus_get_compat(dev);
245 for (desc = schizo_compats; desc->sd_string != NULL; desc++)
246 if (strcmp(desc->sd_string, compat) == 0)
252 schizo_probe(device_t dev)
256 dtype = ofw_bus_get_type(dev);
257 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 &&
258 schizo_get_desc(dev) != NULL) {
259 device_set_desc(dev, "Sun Host-PCI bridge");
266 schizo_attach(device_t dev)
268 const struct schizo_desc *desc;
269 struct schizo_softc *asc, *sc, *osc;
270 struct timecounter *tc;
272 uint64_t ino_bitmap, reg;
274 uint32_t prop, prop_array[2];
275 int i, j, mode, rid, tsbsize;
277 sc = device_get_softc(dev);
278 node = ofw_bus_get_node(dev);
279 desc = schizo_get_desc(dev);
280 mode = desc->sd_mode;
287 * The Schizo has three register banks:
288 * (0) per-PBM PCI configuration and status registers, but for bus B
289 * shared with the UPA64s interrupt mapping register banks
290 * (1) shared Schizo controller configuration and status registers
291 * (2) per-PBM PCI configuration space
293 * The Tomatillo has four register banks:
294 * (0) per-PBM PCI configuration and status registers
295 * (1) per-PBM Tomatillo controller configuration registers, but on
296 * machines having the `jbusppm' device shared with its Estar
297 * register bank for bus A
298 * (2) per-PBM PCI configuration space
299 * (3) per-PBM interrupt concentrator registers
301 sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >>
303 for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG);
306 sc->sc_mem_res[i] = bus_alloc_resource_any(dev,
307 SYS_RES_MEMORY, &rid,
308 (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 &&
309 i == STX_PCI) || i == STX_CTRL)) ||
310 (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 &&
311 i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE);
312 if (sc->sc_mem_res[i] == NULL)
313 panic("%s: could not allocate register bank %d",
318 * Match other Schizos that are already configured against
319 * the controller base physical address. This will be the
320 * same for a pair of devices that share register space.
323 SLIST_FOREACH(asc, &schizo_softcs, sc_link) {
324 if (rman_get_start(asc->sc_mem_res[STX_CTRL]) ==
325 rman_get_start(sc->sc_mem_res[STX_CTRL])) {
332 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF,
334 if (sc->sc_mtx == NULL)
335 panic("%s: could not malloc mutex", __func__);
336 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
338 if (sc->sc_mode != SCHIZO_MODE_SCZ)
339 panic("%s: no partner expected", __func__);
340 if (mtx_initialized(osc->sc_mtx) == 0)
341 panic("%s: mutex not initialized", __func__);
342 sc->sc_mtx = osc->sc_mtx;
344 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link);
346 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1)
347 panic("%s: could not determine IGN", __func__);
348 if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) ==
350 panic("%s: could not determine version", __func__);
351 if (mode == SCHIZO_MODE_XMS && OF_getprop(node, "module-revision#",
352 &sc->sc_mrev, sizeof(sc->sc_mrev)) == -1)
353 panic("%s: could not determine module-revision", __func__);
354 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
357 if (mode == SCHIZO_MODE_XMS && (SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL) &
358 XMS_PCI_CTRL_X_MODE) != 0) {
360 panic("PCI-X mode unsupported");
361 sc->sc_flags |= SCHIZO_FLAGS_XMODE;
364 device_printf(dev, "%s, version %d, ", desc->sd_name, sc->sc_ver);
365 if (mode == SCHIZO_MODE_XMS)
366 printf("module-revision %d, ", sc->sc_mrev);
367 printf("IGN %#x, bus %c, PCI%s mode, %dMHz\n", sc->sc_ign,
368 'A' + sc->sc_half, (sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ?
369 "-X" : "", prop / 1000 / 1000);
371 /* Set up the PCI interrupt retry timer. */
372 SCHIZO_PCI_SET(sc, STX_PCI_INTR_RETRY_TIM, 5);
374 /* Set up the PCI control register. */
375 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL);
376 reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK |
377 STX_PCI_CTRL_ARB_MASK);
378 reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN |
379 STX_PCI_CTRL_ERR_IEN;
380 if (OF_getproplen(node, "no-bus-parking") < 0)
381 reg |= STX_PCI_CTRL_ARB_PARK;
382 if (mode == SCHIZO_MODE_XMS && sc->sc_mrev == 1)
383 reg |= XMS_PCI_CTRL_XMITS10_ARB_MASK;
385 reg |= STX_PCI_CTRL_ARB_MASK;
386 if (mode == SCHIZO_MODE_TOM) {
387 reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL;
388 if (sc->sc_ver <= 1) /* revision <= 2.0 */
389 reg |= TOM_PCI_CTRL_DTO_IEN;
391 reg |= STX_PCI_CTRL_PTO;
392 } else if (mode == SCHIZO_MODE_XMS) {
393 SCHIZO_PCI_SET(sc, XMS_PCI_PARITY_DETECT, 0x3fff);
394 SCHIZO_PCI_SET(sc, XMS_PCI_UPPER_RETRY_COUNTER, 0x3e8);
395 reg |= XMS_PCI_CTRL_X_ERRINT_EN;
397 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, reg);
399 /* Set up the PCI diagnostic register. */
400 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG);
401 reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS |
402 STX_PCI_DIAG_INTRSYNC_DIS);
403 SCHIZO_PCI_SET(sc, STX_PCI_DIAG, reg);
406 * Enable DMA write parity error interrupts of version >= 7 (i.e.
407 * revision >= 2.5) Schizo and XMITS (enabling it on XMITS < 3.0 has
410 if ((mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 7) ||
411 mode == SCHIZO_MODE_XMS) {
412 reg = SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD);
413 reg |= SX_PCI_CFG_ICD_DMAW_PERR_IEN;
414 SCHIZO_PCI_SET(sc, SX_PCI_CFG_ICD, reg);
418 * On Tomatillo clear the I/O prefetch lengths (workaround for a
421 if (mode == SCHIZO_MODE_TOM)
422 SCHIZO_PCI_SET(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW |
423 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM |
424 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL);
427 * Hunt through all the interrupt mapping regs and register
428 * the interrupt controller for our interrupt vectors. We do
429 * this early in order to be able to catch stray interrupts.
430 * This is complicated by the fact that a pair of Schizo PBMs
433 i = OF_getprop(node, "ino-bitmap", (void *)prop_array,
436 ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0];
439 * If the ino-bitmap property is missing, just provide the
440 * default set of interrupts for this controller and let
441 * schizo_setup_intr() take care of child interrupts.
443 if (sc->sc_half == 0)
444 ino_bitmap = (1ULL << STX_UE_INO) |
445 (1ULL << STX_CE_INO) |
446 (1ULL << STX_PCIERR_A_INO) |
447 (1ULL << STX_BUS_INO);
449 ino_bitmap = 1ULL << STX_PCIERR_B_INO;
451 for (i = 0; i <= STX_MAX_INO; i++) {
452 if ((ino_bitmap & (1ULL << i)) == 0)
454 if (i == STX_FB0_INO || i == STX_FB1_INO)
455 /* Leave for upa(4). */
457 j = schizo_intr_register(sc, i);
459 device_printf(dev, "could not register interrupt "
460 "controller for INO %d (%d)\n", i, j);
464 * Setup Safari/JBus performance counter 0 in bus cycle counting
465 * mode as timecounter. Unfortunately, this is broken with at
466 * least the version 4 Tomatillos found in Fire V120 and Blade
467 * 1500, which apparently actually count some different event at
468 * ~0.5 and 3MHz respectively instead (also when running in full
469 * power mode). Besides, one counter seems to be shared by a
470 * "pair" of Tomatillos, too.
472 if (sc->sc_half == 0) {
473 SCHIZO_CTRL_SET(sc, STX_CTRL_PERF,
474 (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) |
475 (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT));
476 tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO);
478 panic("%s: could not malloc timecounter", __func__);
479 tc->tc_get_timecount = schizo_get_timecount;
480 tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK;
481 if (OF_getprop(OF_peer(0), "clock-frequency", &prop,
483 panic("%s: could not determine clock frequency",
485 tc->tc_frequency = prop;
486 tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF);
487 if (mode == SCHIZO_MODE_SCZ)
488 tc->tc_quality = SCHIZO_PERF_CNT_QLTY;
490 tc->tc_quality = -SCHIZO_PERF_CNT_QLTY;
496 * Set up the IOMMU. Schizo, Tomatillo and XMITS all have
497 * one per PBM. Schizo and XMITS additionally have a streaming
498 * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's
499 * affected by several errata though. However, except for context
500 * flushes, taking advantage of it should be okay even with those.
502 memcpy(&sc->sc_dma_methods, &iommu_dma_methods,
503 sizeof(sc->sc_dma_methods));
504 sc->sc_is.sis_sc = sc;
505 sc->sc_is.sis_is.is_flags = IOMMU_PRESERVE_PROM;
506 sc->sc_is.sis_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS);
507 sc->sc_is.sis_is.is_sb[0] = sc->sc_is.sis_is.is_sb[1] = 0;
508 if (OF_getproplen(node, "no-streaming-cache") < 0)
509 sc->sc_is.sis_is.is_sb[0] = STX_PCI_STRBUF;
512 case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \
516 i = OF_getprop(node, "virtual-dma", (void *)prop_array,
518 if (i == -1 || i != sizeof(prop_array))
519 schizo_iommu_init(sc, 7, -1);
521 switch (prop_array[1]) {
531 panic("%s: unsupported DVMA size 0x%x",
532 __func__, prop_array[1]);
535 schizo_iommu_init(sc, tsbsize, prop_array[0]);
540 /* Create our DMA tag. */
541 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
542 sc->sc_is.sis_is.is_pmaxaddr, ~0, NULL, NULL,
543 sc->sc_is.sis_is.is_pmaxaddr, 0xff, 0xffffffff, 0, NULL, NULL,
545 panic("%s: could not create PCI DMA tag", __func__);
546 dmat->dt_cookie = &sc->sc_is;
547 dmat->dt_mt = &sc->sc_dma_methods;
549 if (ofw_pci_attach_common(dev, dmat, STX_IO_SIZE, STX_MEM_SIZE) != 0)
550 panic("%s: ofw_pci_attach_common() failed", __func__);
552 /* Clear any pending PCI error bits. */
553 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE,
554 STX_CS_FUNC, PCIR_STATUS, PCIB_READ_CONFIG(dev,
555 sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS,
557 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL));
558 SCHIZO_PCI_SET(sc, STX_PCI_AFSR, SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR));
561 * Establish handlers for interesting interrupts...
562 * Someone at Sun clearly was smoking crack; with Schizos PCI
563 * bus error interrupts for one PBM can be routed to the other
564 * PBM though we obviously need to use the softc of the former
565 * as the argument for the interrupt handler and the softc of
566 * the latter as the argument for the interrupt controller.
568 if (sc->sc_half == 0) {
569 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 ||
570 (osc != NULL && ((struct schizo_icarg *)intr_vectors[
571 INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)->
574 * We are the driver for PBM A and either also
575 * registered the interrupt controller for us or
576 * the driver for PBM B has probed first and
577 * registered it for us.
579 schizo_set_intr(sc, 0, STX_PCIERR_A_INO,
581 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 &&
584 * We are the driver for PBM A but registered
585 * the interrupt controller for PBM B, i.e. the
586 * driver for PBM B attached first but couldn't
587 * set up a handler for PBM B.
589 schizo_set_intr(osc, 0, STX_PCIERR_B_INO,
592 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 ||
593 (osc != NULL && ((struct schizo_icarg *)intr_vectors[
594 INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)->
597 * We are the driver for PBM B and either also
598 * registered the interrupt controller for us or
599 * the driver for PBM A has probed first and
600 * registered it for us.
602 schizo_set_intr(sc, 0, STX_PCIERR_B_INO,
604 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 &&
607 * We are the driver for PBM B but registered
608 * the interrupt controller for PBM A, i.e. the
609 * driver for PBM A attached first but couldn't
610 * set up a handler for PBM A.
612 schizo_set_intr(osc, 0, STX_PCIERR_A_INO,
615 if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0)
616 schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue);
617 if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0)
618 schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce);
619 if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0)
620 schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus);
623 * According to the Schizo Errata I-13, consistent DMA flushing/
624 * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges,
625 * so we can't use it and need to live with the consequences. With
626 * Schizo version >= 5, CDMA flushing/syncing is usable but requires
627 * the workaround described in Schizo Errata I-23. With Tomatillo
628 * and XMITS, CDMA flushing/syncing works as expected, Tomatillo
629 * version <= 4 (i.e. revision <= 2.3) bridges additionally require
630 * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though.
632 if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) ||
633 sc->sc_mode == SCHIZO_MODE_TOM ||
634 sc->sc_mode == SCHIZO_MODE_XMS) {
635 if (sc->sc_mode == SCHIZO_MODE_SCZ) {
636 sc->sc_dma_methods.dm_dmamap_sync =
638 sc->sc_cdma_state = SCHIZO_CDMA_STATE_IDLE;
640 * Some firmware versions include the CDMA interrupt
641 * at RID 4 but most don't. With the latter we add
642 * it ourselves at the spare RID 5.
644 i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ,
646 if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) {
647 sc->sc_cdma_vec = INTMAP_VEC(sc->sc_ign, i);
648 (void)schizo_get_intrmap(sc, i,
649 &sc->sc_cdma_map, &sc->sc_cdma_clr);
650 schizo_set_intr(sc, 4, i, schizo_cdma);
652 i = STX_CDMA_A_INO + sc->sc_half;
653 sc->sc_cdma_vec = INTMAP_VEC(sc->sc_ign, i);
654 if (bus_set_resource(dev, SYS_RES_IRQ, 5,
655 sc->sc_cdma_vec, 1) != 0)
656 panic("%s: failed to add CDMA "
657 "interrupt", __func__);
658 j = schizo_intr_register(sc, i);
660 panic("%s: could not register "
661 "interrupt controller for CDMA "
662 "(%d)", __func__, j);
663 (void)schizo_get_intrmap(sc, i,
664 &sc->sc_cdma_map, &sc->sc_cdma_clr);
665 schizo_set_intr(sc, 5, i, schizo_cdma);
668 if (sc->sc_mode == SCHIZO_MODE_XMS)
669 mtx_init(&sc->sc_sync_mtx, "pcib_sync_mtx",
671 sc->sc_sync_val = 1ULL << (STX_PCIERR_A_INO +
673 sc->sc_dma_methods.dm_dmamap_sync =
676 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4)
677 sc->sc_flags |= SCHIZO_FLAGS_BSWAR;
681 * Set the latency timer register as this isn't always done by the
684 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE,
685 STX_CS_FUNC, PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
687 #define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \
688 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \
689 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \
690 (name), CTLFLAG_RD, (arg), 0, (desc))
692 SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce,
693 "DMA correctable errors");
694 SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal,
695 "PCI bus non-fatal errors");
697 #undef SCHIZO_SYSCTL_ADD_UINT
699 device_add_child(dev, "pci", -1);
700 return (bus_generic_attach(dev));
704 schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino,
705 driver_filter_t handler)
711 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev,
712 SYS_RES_IRQ, &rid, RF_ACTIVE);
713 if (sc->sc_irq_res[index] == NULL ||
714 INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino ||
715 INTIGN(vec) != sc->sc_ign ||
716 intr_vectors[vec].iv_ic != &schizo_ic ||
717 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index],
718 INTR_TYPE_MISC | INTR_BRIDGE, handler, NULL, sc,
719 &sc->sc_ihand[index]) != 0)
720 panic("%s: failed to set up interrupt %d", __func__, index);
724 schizo_intr_register(struct schizo_softc *sc, u_int ino)
726 struct schizo_icarg *sica;
727 bus_addr_t intrclr, intrmap;
730 if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0)
732 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT);
736 sica->sica_map = intrmap;
737 sica->sica_clr = intrclr;
739 device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n",
740 ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap),
743 error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino),
746 free(sica, M_DEVBUF);
751 schizo_get_intrmap(struct schizo_softc *sc, u_int ino,
752 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr)
754 bus_addr_t intrclr, intrmap;
758 * XXX we only look for INOs rather than INRs since the firmware
759 * may not provide the IGN and the IGN is constant for all devices
760 * on that PCI controller.
763 if (ino > STX_MAX_INO) {
764 device_printf(sc->sc_dev, "out of range INO %d requested\n",
769 intrmap = STX_PCI_IMAP_BASE + (ino << 3);
770 intrclr = STX_PCI_ICLR_BASE + (ino << 3);
771 mr = SCHIZO_PCI_READ_8(sc, intrmap);
772 if (INTINO(mr) != ino) {
773 device_printf(sc->sc_dev,
774 "interrupt map entry does not match INO (%d != %d)\n",
775 (int)INTINO(mr), ino);
779 if (intrmapptr != NULL)
780 *intrmapptr = intrmap;
781 if (intrclrptr != NULL)
782 *intrclrptr = intrclr;
790 schizo_pci_bus(void *arg)
792 struct schizo_softc *sc = arg;
793 uint64_t afar, afsr, csr, iommu, xstat;
799 mtx_lock_spin(sc->sc_mtx);
801 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR);
802 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR);
803 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL);
804 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU);
805 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0)
806 xstat = SCHIZO_PCI_READ_8(sc, XMS_PCI_X_ERR_STAT);
809 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_ops.sc_pci_secbus,
810 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2);
813 * IOMMU errors are only fatal on Tomatillo and there also only if
814 * target abort was not signaled.
816 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 &&
817 (iommu & TOM_PCI_IOMMU_ERR) != 0 &&
818 ((status & PCIM_STATUS_STABORT) == 0 ||
819 ((iommu & TOM_PCI_IOMMU_ERRMASK) != TOM_PCI_IOMMU_INVALID_ERR &&
820 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) == 0 &&
821 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) == 0)))
823 else if ((status & PCIM_STATUS_STABORT) != 0)
825 if ((status & (PCIM_STATUS_PERR | PCIM_STATUS_SERR |
826 PCIM_STATUS_RMABORT | PCIM_STATUS_RTABORT |
827 PCIM_STATUS_MDPERR)) != 0 ||
828 (csr & (SCZ_PCI_CTRL_BUS_UNUS | TOM_PCI_CTRL_DTO_ERR |
829 STX_PCI_CTRL_TTO_ERR | STX_PCI_CTRL_RTRY_ERR |
830 SCZ_PCI_CTRL_SBH_ERR | STX_PCI_CTRL_SERR)) != 0 ||
831 (afsr & (STX_PCI_AFSR_P_MA | STX_PCI_AFSR_P_TA |
832 STX_PCI_AFSR_P_RTRY | STX_PCI_AFSR_P_PERR | STX_PCI_AFSR_P_TTO |
833 STX_PCI_AFSR_P_UNUS)) != 0)
835 if (xstat & (XMS_PCI_X_ERR_STAT_P_SC_DSCRD |
836 XMS_PCI_X_ERR_STAT_P_SC_TTO | XMS_PCI_X_ERR_STAT_P_SDSTAT |
837 XMS_PCI_X_ERR_STAT_P_SMMU | XMS_PCI_X_ERR_STAT_P_CDSTAT |
838 XMS_PCI_X_ERR_STAT_P_CMMU | XMS_PCI_X_ERR_STAT_PERR_RCV))
841 sc->sc_stats_pci_non_fatal++;
843 device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx "
844 "PCI CSR %#llx IOMMU %#llx PCI-X %#llx STATUS %#x\n",
845 'A' + sc->sc_half, (unsigned long long)afar,
846 (unsigned long long)afsr, (unsigned long long)csr,
847 (unsigned long long)iommu, (unsigned long long)xstat, status);
849 /* Clear the error bits that we caught. */
850 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE,
851 STX_CS_FUNC, PCIR_STATUS, status, 2);
852 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr);
853 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr);
854 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu);
855 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0)
856 SCHIZO_PCI_WRITE_8(sc, XMS_PCI_X_ERR_STAT, xstat);
858 mtx_unlock_spin(sc->sc_mtx);
861 panic("%s: fatal PCI bus error",
862 device_get_nameunit(sc->sc_dev));
863 return (FILTER_HANDLED);
869 struct schizo_softc *sc = arg;
873 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR);
874 for (i = 0; i < 1000; i++)
875 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) &
876 STX_CTRL_CE_AFSR_ERRPNDG) == 0)
878 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx",
879 device_get_nameunit(sc->sc_dev), (unsigned long long)afar,
880 (unsigned long long)afsr);
881 return (FILTER_HANDLED);
887 struct schizo_softc *sc = arg;
891 mtx_lock_spin(sc->sc_mtx);
893 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR);
894 for (i = 0; i < 1000; i++)
895 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) &
896 STX_CTRL_CE_AFSR_ERRPNDG) == 0)
898 sc->sc_stats_dma_ce++;
899 device_printf(sc->sc_dev,
900 "correctable DMA error AFAR %#llx AFSR %#llx\n",
901 (unsigned long long)afar, (unsigned long long)afsr);
903 /* Clear the error bits that we caught. */
904 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr);
906 mtx_unlock_spin(sc->sc_mtx);
908 return (FILTER_HANDLED);
912 schizo_host_bus(void *arg)
914 struct schizo_softc *sc = arg;
917 errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG);
918 panic("%s: %s error %#llx", device_get_nameunit(sc->sc_dev),
919 sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari",
920 (unsigned long long)errlog);
921 return (FILTER_HANDLED);
925 schizo_cdma(void *arg)
927 struct schizo_softc *sc = arg;
929 atomic_cmpset_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_PENDING,
930 SCHIZO_CDMA_STATE_RECEIVED);
931 return (FILTER_HANDLED);
935 schizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase)
938 /* Punch in our copies. */
939 sc->sc_is.sis_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]);
940 sc->sc_is.sis_is.is_bushandle =
941 rman_get_bushandle(sc->sc_mem_res[STX_PCI]);
942 sc->sc_is.sis_is.is_iommu = STX_PCI_IOMMU;
943 sc->sc_is.sis_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG;
944 sc->sc_is.sis_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG;
945 sc->sc_is.sis_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG;
946 sc->sc_is.sis_is.is_dva = STX_PCI_IOMMU_SVADIAG;
947 sc->sc_is.sis_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG;
949 iommu_init(device_get_nameunit(sc->sc_dev),
950 (struct iommu_state *)&sc->sc_is, tsbsize, dvmabase, 0);
954 schizo_maxslots(device_t dev)
956 struct schizo_softc *sc;
958 sc = device_get_softc(dev);
959 if (sc->sc_mode == SCHIZO_MODE_SCZ)
960 return (sc->sc_half == 0 ? 4 : 6);
962 /* XXX: is this correct? */
963 return (PCI_SLOTMAX);
967 schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
970 struct schizo_softc *sc;
972 sc = device_get_softc(dev);
974 * The Schizo bridges contain a dupe of their header at 0x80.
976 if (sc->sc_mode == SCHIZO_MODE_SCZ &&
977 bus == sc->sc_ops.sc_pci_secbus && slot == STX_CS_DEVICE &&
978 func == STX_CS_FUNC && reg + width > 0x80)
981 return (ofw_pci_read_config_common(dev, PCI_REGMAX, STX_CONF_OFF(bus,
982 slot, func, reg), bus, slot, func, reg, width));
986 schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func,
987 u_int reg, uint32_t val, int width)
990 ofw_pci_write_config_common(dev, PCI_REGMAX, STX_CONF_OFF(bus, slot,
991 func, reg), bus, slot, func, reg, val, width);
995 schizo_route_interrupt(device_t bridge, device_t dev, int pin)
997 ofw_pci_intr_t mintr;
999 mintr = ofw_pci_route_interrupt_common(bridge, dev, pin);
1000 if (!PCI_INTERRUPT_VALID(mintr))
1001 device_printf(bridge,
1002 "could not route pin %d for device %d.%d\n",
1003 pin, pci_get_slot(dev), pci_get_function(dev));
1008 schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
1010 struct timeval cur, end;
1011 struct schizo_iommu_state *sis = dt->dt_cookie;
1012 struct schizo_softc *sc = sis->sis_sc;
1018 if ((map->dm_flags & DMF_STREAMED) != 0) {
1019 iommu_dma_methods.dm_dmamap_sync(dt, map, op);
1023 if ((map->dm_flags & DMF_LOADED) == 0)
1026 if ((op & BUS_DMASYNC_POSTREAD) != 0) {
1028 * Note that in order to allow this function to be called from
1029 * filters we would need to use a spin mutex for serialization
1030 * but given that these disable interrupts we have to emulate
1034 KASSERT((rdpr(pstate) & PSTATE_IE) != 0,
1035 ("%s: interrupts disabled", __func__));
1036 KASSERT((pil = rdpr(pil)) <= PIL_BRIDGE,
1037 ("%s: PIL too low (%ld)", __func__, pil));
1038 for (; atomic_cmpset_acq_32(&sc->sc_cdma_state,
1039 SCHIZO_CDMA_STATE_IDLE, SCHIZO_CDMA_STATE_PENDING) == 0;)
1041 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_map,
1042 INTMAP_ENABLE(sc->sc_cdma_vec, PCPU_GET(mid)));
1043 for (i = 0; i < SCHIZO_CDMA_TRIES; i++) {
1045 printf("%s: try %d\n", __func__, i);
1046 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr,
1049 end.tv_sec = SCHIZO_CDMA_TIMEOUT;
1051 timevaladd(&end, &cur);
1052 for (; (res = atomic_cmpset_rel_32(&sc->sc_cdma_state,
1053 SCHIZO_CDMA_STATE_RECEIVED,
1054 SCHIZO_CDMA_STATE_IDLE)) == 0 &&
1055 timevalcmp(&cur, &end, <=);)
1061 panic("%s: DMA does not sync", __func__);
1065 if ((op & BUS_DMASYNC_PREWRITE) != 0)
1070 ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
1072 struct timeval cur, end;
1073 struct schizo_iommu_state *sis = dt->dt_cookie;
1074 struct schizo_softc *sc = sis->sis_sc;
1077 if ((map->dm_flags & DMF_STREAMED) != 0) {
1078 iommu_dma_methods.dm_dmamap_sync(dt, map, op);
1082 if ((map->dm_flags & DMF_LOADED) == 0)
1085 if ((op & BUS_DMASYNC_POSTREAD) != 0) {
1086 if (sc->sc_mode == SCHIZO_MODE_XMS)
1087 mtx_lock_spin(&sc->sc_sync_mtx);
1088 SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND,
1093 timevaladd(&end, &cur);
1094 for (; ((reg = SCHIZO_PCI_READ_8(sc,
1095 TOMXMS_PCI_DMA_SYNC_PEND)) & sc->sc_sync_val) != 0 &&
1096 timevalcmp(&cur, &end, <=);)
1098 if ((reg & sc->sc_sync_val) != 0)
1099 panic("%s: DMA does not sync", __func__);
1100 if (sc->sc_mode == SCHIZO_MODE_XMS)
1101 mtx_unlock_spin(&sc->sc_sync_mtx);
1102 else if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) {
1103 ofw_pci_dmamap_sync_stst_order_common();
1108 if ((op & BUS_DMASYNC_PREWRITE) != 0)
1113 schizo_intr_enable(void *arg)
1115 struct intr_vector *iv = arg;
1116 struct schizo_icarg *sica = iv->iv_icarg;
1118 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map,
1119 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
1123 schizo_intr_disable(void *arg)
1125 struct intr_vector *iv = arg;
1126 struct schizo_icarg *sica = iv->iv_icarg;
1128 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec);
1132 schizo_intr_assign(void *arg)
1134 struct intr_vector *iv = arg;
1135 struct schizo_icarg *sica = iv->iv_icarg;
1137 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID(
1138 SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid));
1142 schizo_intr_clear(void *arg)
1144 struct intr_vector *iv = arg;
1145 struct schizo_icarg *sica = iv->iv_icarg;
1147 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE);
1151 schizo_setup_intr(device_t dev, device_t child, struct resource *ires,
1152 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
1155 struct schizo_softc *sc;
1159 sc = device_get_softc(dev);
1161 * Make sure the vector is fully specified.
1163 vec = rman_get_start(ires);
1164 if (INTIGN(vec) != sc->sc_ign) {
1165 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
1169 if (intr_vectors[vec].iv_ic == &schizo_ic) {
1171 * Ensure we use the right softc in case the interrupt
1172 * is routed to our companion PBM for some odd reason.
1174 sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)->
1176 } else if (intr_vectors[vec].iv_ic == NULL) {
1178 * Work around broken firmware which misses entries in
1181 error = schizo_intr_register(sc, INTINO(vec));
1183 device_printf(dev, "could not register interrupt "
1184 "controller for vector 0x%lx (%d)\n", vec, error);
1188 device_printf(dev, "belatedly registered as "
1189 "interrupt controller for vector 0x%lx\n", vec);
1192 "invalid interrupt controller for vector 0x%lx\n", vec);
1195 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
1199 static struct resource *
1200 schizo_alloc_resource(device_t bus, device_t child, int type, int *rid,
1201 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1203 struct schizo_softc *sc;
1205 if (type == SYS_RES_IRQ) {
1206 sc = device_get_softc(bus);
1207 start = end = INTMAP_VEC(sc->sc_ign, end);
1209 return (ofw_pci_alloc_resource(bus, child, type, rid, start, end,
1214 schizo_setup_device(device_t bus, device_t child)
1216 struct schizo_softc *sc;
1220 sc = device_get_softc(bus);
1222 * Disable bus parking in order to work around a bus hang caused by
1223 * Casinni/Skyhawk combinations.
1225 if (OF_getproplen(ofw_bus_get_node(child), "pci-req-removal") >= 0)
1226 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc,
1227 STX_PCI_CTRL) & ~STX_PCI_CTRL_ARB_PARK);
1229 if (sc->sc_mode == SCHIZO_MODE_XMS) {
1230 /* XMITS NCPQ WAR: set outstanding split transactions to 1. */
1231 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 &&
1232 (pci_read_config(child, PCIR_HDRTYPE, 1) &
1233 PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE &&
1234 pci_find_cap(child, PCIY_PCIX, &capreg) == 0)
1235 pci_write_config(child, capreg + PCIXR_COMMAND,
1236 pci_read_config(child, capreg + PCIXR_COMMAND,
1238 /* XMITS 3.x WAR: set BUGCNTL iff value is unexpected. */
1239 if (sc->sc_mrev >= 4) {
1240 reg = ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ?
1241 0xa0UL : 0xffUL) << XMS_PCI_X_DIAG_BUGCNTL_SHIFT;
1242 if ((SCHIZO_PCI_READ_8(sc, XMS_PCI_X_DIAG) &
1243 XMS_PCI_X_DIAG_BUGCNTL_MASK) != reg)
1244 SCHIZO_PCI_SET(sc, XMS_PCI_X_DIAG, reg);
1250 schizo_get_timecount(struct timecounter *tc)
1252 struct schizo_softc *sc;
1255 return ((SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) &
1256 (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)) >>
1257 STX_CTRL_PERF_CNT_CNT0_SHIFT);