3 * The President and Fellows of Harvard College. All rights reserved.
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
7 * This software was developed by the Computer Systems Engineering group
8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
9 * contributed to Berkeley.
11 * All advertising materials mentioning features or use of this software
12 * must display the following acknowledgement:
13 * This product includes software developed by Harvard University.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
19 * 1. Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution.
24 * 3. All advertising materials mentioning features or use of this software
25 * must display the following acknowledgement:
26 * This product includes software developed by Aaron Brown and
28 * 4. Neither the name of the University nor the names of its contributors
29 * may be used to endorse or promote products derived from this software
30 * without specific prior written permission.
32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * Copyright (c) 2001 by Thomas Moestl <tmm@FreeBSD.org>.
46 * Copyright (c) 2008, 2010 Marius Strobl <marius@FreeBSD.org>
47 * All rights reserved.
49 * Redistribution and use in source and binary forms, with or without
50 * modification, are permitted provided that the following conditions
52 * 1. Redistributions of source code must retain the above copyright
53 * notice, this list of conditions and the following disclaimer.
54 * 2. Redistributions in binary form must reproduce the above copyright
55 * notice, this list of conditions and the following disclaimer in the
56 * documentation and/or other materials provided with the distribution.
58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
61 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
65 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
66 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
67 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
69 * from: @(#)cache.c 8.2 (Berkeley) 10/30/93
70 * from: NetBSD: cache.c,v 1.5 2000/12/06 01:47:50 mrg Exp
73 #include <sys/cdefs.h>
74 __FBSDID("$FreeBSD$");
76 #include <sys/param.h>
77 #include <sys/systm.h>
80 #include <dev/ofw/openfirm.h>
82 #include <machine/cache.h>
83 #include <machine/tlb.h>
84 #include <machine/ver.h>
86 cache_enable_t *cache_enable;
87 cache_flush_t *cache_flush;
88 dcache_page_inval_t *dcache_page_inval;
89 icache_page_inval_t *icache_page_inval;
91 u_int dcache_color_ignore;
93 #define OF_GET(h, n, v) OF_getprop((h), (n), &(v), sizeof(v))
95 static u_int cache_new_prop(u_int cpu_impl);
98 cache_new_prop(u_int cpu_impl)
102 case CPU_IMPL_ULTRASPARCIV:
103 case CPU_IMPL_ULTRASPARCIVp:
111 * Fill in the cache parameters using the CPU node.
114 cache_init(struct pcpu *pcpu)
120 * For CPUs which ignore TD_CV and support hardware unaliasing don't
121 * bother doing page coloring. This is equal across all CPUs.
123 if (pcpu->pc_cpuid == 0 && pcpu->pc_impl == CPU_IMPL_SPARC64V)
124 dcache_color_ignore = 1;
126 use_new_prop = cache_new_prop(pcpu->pc_impl);
127 if (OF_GET(pcpu->pc_node, !use_new_prop ? "icache-size" :
128 "l1-icache-size", pcpu->pc_cache.ic_size) == -1 ||
129 OF_GET(pcpu->pc_node, !use_new_prop ? "icache-line-size" :
130 "l1-icache-line-size", pcpu->pc_cache.ic_linesize) == -1 ||
131 OF_GET(pcpu->pc_node, !use_new_prop ? "icache-associativity" :
132 "l1-icache-associativity", pcpu->pc_cache.ic_assoc) == -1 ||
133 OF_GET(pcpu->pc_node, !use_new_prop ? "dcache-size" :
134 "l1-dcache-size", pcpu->pc_cache.dc_size) == -1 ||
135 OF_GET(pcpu->pc_node, !use_new_prop ? "dcache-line-size" :
136 "l1-dcache-line-size", pcpu->pc_cache.dc_linesize) == -1 ||
137 OF_GET(pcpu->pc_node, !use_new_prop ? "dcache-associativity" :
138 "l1-dcache-associativity", pcpu->pc_cache.dc_assoc) == -1 ||
139 OF_GET(pcpu->pc_node, !use_new_prop ? "ecache-size" :
140 "l2-cache-size", pcpu->pc_cache.ec_size) == -1 ||
141 OF_GET(pcpu->pc_node, !use_new_prop ? "ecache-line-size" :
142 "l2-cache-line-size", pcpu->pc_cache.ec_linesize) == -1 ||
143 OF_GET(pcpu->pc_node, !use_new_prop ? "ecache-associativity" :
144 "l2-cache-associativity", pcpu->pc_cache.ec_assoc) == -1)
145 OF_panic("%s: could not retrieve cache parameters", __func__);
147 set = pcpu->pc_cache.ic_size / pcpu->pc_cache.ic_assoc;
148 if ((set & ~(1UL << (ffs(set) - 1))) != 0)
149 OF_panic("%s: I$ set size not a power of 2", __func__);
150 if ((pcpu->pc_cache.dc_size &
151 ~(1UL << (ffs(pcpu->pc_cache.dc_size) - 1))) != 0)
152 OF_panic("%s: D$ size not a power of 2", __func__);
154 * For CPUs which don't support unaliasing in hardware ensure that
155 * the data cache doesn't have too many virtual colors.
157 if (dcache_color_ignore == 0 && ((pcpu->pc_cache.dc_size /
158 pcpu->pc_cache.dc_assoc) / PAGE_SIZE) != DCACHE_COLORS)
159 OF_panic("%s: too many D$ colors", __func__);
160 set = pcpu->pc_cache.ec_size / pcpu->pc_cache.ec_assoc;
161 if ((set & ~(1UL << (ffs(set) - 1))) != 0)
162 OF_panic("%s: E$ set size not a power of 2", __func__);
164 if (pcpu->pc_impl >= CPU_IMPL_ULTRASPARCIII) {
165 cache_enable = cheetah_cache_enable;
166 cache_flush = cheetah_cache_flush;
167 dcache_page_inval = cheetah_dcache_page_inval;
168 icache_page_inval = cheetah_icache_page_inval;
169 tlb_flush_nonlocked = cheetah_tlb_flush_nonlocked;
170 tlb_flush_user = cheetah_tlb_flush_user;
171 } else if (pcpu->pc_impl == CPU_IMPL_SPARC64V) {
172 cache_enable = zeus_cache_enable;
173 cache_flush = zeus_cache_flush;
174 dcache_page_inval = zeus_dcache_page_inval;
175 icache_page_inval = zeus_icache_page_inval;
176 tlb_flush_nonlocked = zeus_tlb_flush_nonlocked;
177 tlb_flush_user = zeus_tlb_flush_user;
178 } else if (pcpu->pc_impl >= CPU_IMPL_ULTRASPARCI &&
179 pcpu->pc_impl < CPU_IMPL_ULTRASPARCIII) {
180 cache_enable = spitfire_cache_enable;
181 cache_flush = spitfire_cache_flush;
182 dcache_page_inval = spitfire_dcache_page_inval;
183 icache_page_inval = spitfire_icache_page_inval;
184 tlb_flush_nonlocked = spitfire_tlb_flush_nonlocked;
185 tlb_flush_user = spitfire_tlb_flush_user;
187 OF_panic("%s: unknown CPU", __func__);