2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 Jake Burkholder.
5 * Copyright (c) 2005 - 2011 Marius Strobl <marius@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/mutex.h>
42 #include <machine/asi.h>
43 #include <machine/cache.h>
44 #include <machine/cpu.h>
45 #include <machine/cpufunc.h>
46 #include <machine/dcr.h>
47 #include <machine/lsu.h>
48 #include <machine/smp.h>
49 #include <machine/tlb.h>
50 #include <machine/ver.h>
51 #include <machine/vmparam.h>
53 #define CHEETAH_ICACHE_TAG_LOWER 0x30
54 #define CHEETAH_T16_ENTRIES 16
55 #define CHEETAH_DT512_ENTRIES 512
56 #define CHEETAH_IT128_ENTRIES 128
57 #define CHEETAH_IT512_ENTRIES 512
60 * CPU-specific initialization for Sun Cheetah and later CPUs
63 cheetah_init(u_int cpu_impl)
67 /* Ensure the TSB Extension Registers hold 0 as TSB_Base. */
69 stxa(AA_DMMU_TSB_PEXT_REG, ASI_DMMU, 0);
70 stxa(AA_IMMU_TSB_PEXT_REG, ASI_IMMU, 0);
73 stxa(AA_DMMU_TSB_SEXT_REG, ASI_DMMU, 0);
75 * NB: the secondary context was removed from the iMMU.
79 stxa(AA_DMMU_TSB_NEXT_REG, ASI_DMMU, 0);
80 stxa(AA_IMMU_TSB_NEXT_REG, ASI_IMMU, 0);
84 * Configure the first large dTLB to hold 4MB pages (e.g. for direct
85 * mappings) for all three contexts and ensure the second one is set
86 * up to hold 8k pages for them. Note that this is constraint by
87 * US-IV+, whose large dTLBs can only hold entries of certain page
89 * For US-IV+, additionally ensure that the large iTLB is set up to
90 * hold 8k pages for nucleus and primary context (still no secondary
92 * NB: according to documentation, changing the page size of the same
93 * context requires a context demap before changing the corresponding
94 * page size, but we hardly can flush our locked pages here, so we use
95 * a demap all instead.
97 stxa(TLB_DEMAP_ALL, ASI_DMMU_DEMAP, 0);
99 val = (TS_4M << TLB_PCXR_N_PGSZ0_SHIFT) |
100 (TS_8K << TLB_PCXR_N_PGSZ1_SHIFT) |
101 (TS_4M << TLB_PCXR_P_PGSZ0_SHIFT) |
102 (TS_8K << TLB_PCXR_P_PGSZ1_SHIFT);
103 if (cpu_impl == CPU_IMPL_ULTRASPARCIVp)
104 val |= (TS_8K << TLB_PCXR_N_PGSZ_I_SHIFT) |
105 (TS_8K << TLB_PCXR_P_PGSZ_I_SHIFT);
106 stxa(AA_DMMU_PCXR, ASI_DMMU, val);
107 val = (TS_4M << TLB_SCXR_S_PGSZ0_SHIFT) |
108 (TS_8K << TLB_SCXR_S_PGSZ1_SHIFT);
109 stxa(AA_DMMU_SCXR, ASI_DMMU, val);
113 * Ensure DCR_IFPOE is disabled as long as we haven't implemented
114 * support for it (if ever) as most if not all firmware versions
115 * apparently turn it on. Not making use of DCR_IFPOE should also
116 * avoid Cheetah erratum #109.
118 val = rd(asr18) & ~DCR_IFPOE;
119 if (cpu_impl == CPU_IMPL_ULTRASPARCIVp) {
121 * Ensure the branch prediction mode is set to PC indexing
122 * in order to work around US-IV+ erratum #2.
124 val = (val & ~DCR_BPM_MASK) | DCR_BPM_PC;
126 * XXX disable dTLB parity error reporting as otherwise we
127 * get seemingly false positives when copying in the user
128 * window by simulating a fill trap on return to usermode in
129 * case single issue is disabled, which thus appears to be
138 * Enable level 1 caches.
141 cheetah_cache_enable(u_int cpu_impl)
145 lsu = ldxa(0, ASI_LSU_CTL_REG);
146 if (cpu_impl == CPU_IMPL_ULTRASPARCIII) {
147 /* Disable P$ due to US-III erratum #18. */
150 stxa(0, ASI_LSU_CTL_REG, lsu | LSU_IC | LSU_DC);
155 * Flush all lines from the level 1 caches.
158 cheetah_cache_flush(void)
164 for (addr = 0; addr < PCPU_GET(cache.dc_size);
165 addr += PCPU_GET(cache.dc_linesize))
167 * Note that US-IV+ additionally require a membar #Sync before
168 * a load or store to ASI_DCACHE_TAG.
172 "stxa %%g0, [%0] %1;"
174 : : "r" (addr), "n" (ASI_DCACHE_TAG));
176 /* The I$ must be disabled when flushing it so ensure it's off. */
177 lsu = ldxa(0, ASI_LSU_CTL_REG);
178 stxa(0, ASI_LSU_CTL_REG, lsu & ~(LSU_IC));
180 for (addr = CHEETAH_ICACHE_TAG_LOWER;
181 addr < PCPU_GET(cache.ic_size) * 2;
182 addr += PCPU_GET(cache.ic_linesize) * 2)
184 "stxa %%g0, [%0] %1;"
186 : : "r" (addr), "n" (ASI_ICACHE_TAG));
187 stxa(0, ASI_LSU_CTL_REG, lsu);
193 * Flush a physical page from the data cache.
196 cheetah_dcache_page_inval(vm_paddr_t spa)
201 KASSERT((spa & PAGE_MASK) == 0,
202 ("%s: pa not page aligned", __func__));
203 cookie = ipi_dcache_page_inval(tl_ipi_cheetah_dcache_page_inval, spa);
204 for (pa = spa; pa < spa + PAGE_SIZE;
205 pa += PCPU_GET(cache.dc_linesize))
206 stxa_sync(pa, ASI_DCACHE_INVALIDATE, 0);
211 * Flush a physical page from the intsruction cache. Instruction cache
212 * consistency is maintained by hardware.
215 cheetah_icache_page_inval(vm_paddr_t pa __unused)
221 * Flush all non-locked mappings from the TLBs.
224 cheetah_tlb_flush_nonlocked(void)
227 stxa(TLB_DEMAP_ALL, ASI_DMMU_DEMAP, 0);
228 stxa(TLB_DEMAP_ALL, ASI_IMMU_DEMAP, 0);
233 * Flush all user mappings from the TLBs.
236 cheetah_tlb_flush_user(void)
243 * We read ASI_{D,I}TLB_DATA_ACCESS_REG twice back-to-back in order
244 * to work around errata of USIII and beyond.
246 for (i = 0; i < CHEETAH_T16_ENTRIES; i++) {
247 slot = TLB_DAR_SLOT(TLB_DAR_T16, i);
249 (void)ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
250 data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
252 tag = ldxa(slot, ASI_DTLB_TAG_READ_REG);
253 if ((data & TD_V) != 0 && (data & TD_L) == 0 &&
254 TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
255 stxa_sync(slot, ASI_DTLB_DATA_ACCESS_REG, 0);
257 (void)ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
258 data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
260 tag = ldxa(slot, ASI_ITLB_TAG_READ_REG);
261 if ((data & TD_V) != 0 && (data & TD_L) == 0 &&
262 TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
263 stxa_sync(slot, ASI_ITLB_DATA_ACCESS_REG, 0);
265 for (i = 0; i < CHEETAH_DT512_ENTRIES; i++) {
266 slot = TLB_DAR_SLOT(TLB_DAR_DT512_0, i);
268 (void)ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
269 data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
271 tag = ldxa(slot, ASI_DTLB_TAG_READ_REG);
272 if ((data & TD_V) != 0 && TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
273 stxa_sync(slot, ASI_DTLB_DATA_ACCESS_REG, 0);
274 slot = TLB_DAR_SLOT(TLB_DAR_DT512_1, i);
276 (void)ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
277 data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
279 tag = ldxa(slot, ASI_DTLB_TAG_READ_REG);
280 if ((data & TD_V) != 0 && TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
281 stxa_sync(slot, ASI_DTLB_DATA_ACCESS_REG, 0);
283 if (PCPU_GET(impl) == CPU_IMPL_ULTRASPARCIVp) {
284 for (i = 0; i < CHEETAH_IT512_ENTRIES; i++) {
285 slot = TLB_DAR_SLOT(TLB_DAR_IT512, i);
287 (void)ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
288 data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
290 tag = ldxa(slot, ASI_ITLB_TAG_READ_REG);
291 if ((data & TD_V) != 0 &&
292 TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
293 stxa_sync(slot, ASI_ITLB_DATA_ACCESS_REG, 0);
296 for (i = 0; i < CHEETAH_IT128_ENTRIES; i++) {
297 slot = TLB_DAR_SLOT(TLB_DAR_IT128, i);
299 (void)ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
300 data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
301 tag = ldxa(slot, ASI_ITLB_TAG_READ_REG);
303 if ((data & TD_V) != 0 &&
304 TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
305 stxa_sync(slot, ASI_ITLB_DATA_ACCESS_REG, 0);