2 * Copyright (c) 1997 Berkeley Software Design, Inc. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. Berkeley Software Design Inc's name may not be used to endorse or
13 * promote products derived from this software without specific prior
16 * THIS SOFTWARE IS PROVIDED BY BERKELEY SOFTWARE DESIGN INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL BERKELEY SOFTWARE DESIGN INC BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * BSDI $Id: locore.s,v 1.36.2.15 1999/08/23 22:34:41 cp Exp $
31 * Copyright (c) 2001 Jake Burkholder.
32 * All rights reserved.
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
44 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
45 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
46 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
47 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
48 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
49 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
51 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
52 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
56 #include <machine/asm.h>
57 __FBSDID("$FreeBSD$");
59 #include "opt_compat.h"
61 #include "opt_kstack_pages.h"
63 #include <machine/asi.h>
64 #include <machine/asmacros.h>
65 #include <machine/frame.h>
66 #include <machine/fsr.h>
67 #include <machine/intr_machdep.h>
68 #include <machine/ktr.h>
69 #include <machine/pcb.h>
70 #include <machine/pstate.h>
71 #include <machine/trap.h>
72 #include <machine/tsb.h>
73 #include <machine/tstate.h>
74 #include <machine/utrap.h>
75 #include <machine/wstate.h>
80 #define TSB_KERNEL 0x0
81 #define TSB_KERNEL_MASK 0x0
82 #define TSB_KERNEL_PHYS 0x0
83 #define TSB_KERNEL_PHYS_END 0x0
84 #define TSB_QUAD_LDD 0x0
92 * Atomically set a bit in a TTE.
94 #define TTE_SET_BIT(r1, r2, r3, bit, a, asi) \
95 add r1, TTE_DATA, r1 ; \
96 LD(x, a) [r1] asi, r2 ; \
98 CAS(x, a) [r1] asi, r2, r3 ; \
103 #define TTE_SET_REF(r1, r2, r3, a, asi) TTE_SET_BIT(r1, r2, r3, TD_REF, a, asi)
104 #define TTE_SET_W(r1, r2, r3, a, asi) TTE_SET_BIT(r1, r2, r3, TD_W, a, asi)
107 * Macros for spilling and filling live windows.
109 * NOTE: These macros use exactly 16 instructions, and it is assumed that the
110 * handler will not use more than 24 instructions total, to leave room for
111 * resume vectors which occupy the last 8 instructions.
114 #define SPILL(storer, base, size, asi) \
115 storer %l0, [base + (0 * size)] asi ; \
116 storer %l1, [base + (1 * size)] asi ; \
117 storer %l2, [base + (2 * size)] asi ; \
118 storer %l3, [base + (3 * size)] asi ; \
119 storer %l4, [base + (4 * size)] asi ; \
120 storer %l5, [base + (5 * size)] asi ; \
121 storer %l6, [base + (6 * size)] asi ; \
122 storer %l7, [base + (7 * size)] asi ; \
123 storer %i0, [base + (8 * size)] asi ; \
124 storer %i1, [base + (9 * size)] asi ; \
125 storer %i2, [base + (10 * size)] asi ; \
126 storer %i3, [base + (11 * size)] asi ; \
127 storer %i4, [base + (12 * size)] asi ; \
128 storer %i5, [base + (13 * size)] asi ; \
129 storer %i6, [base + (14 * size)] asi ; \
130 storer %i7, [base + (15 * size)] asi
132 #define FILL(loader, base, size, asi) \
133 loader [base + (0 * size)] asi, %l0 ; \
134 loader [base + (1 * size)] asi, %l1 ; \
135 loader [base + (2 * size)] asi, %l2 ; \
136 loader [base + (3 * size)] asi, %l3 ; \
137 loader [base + (4 * size)] asi, %l4 ; \
138 loader [base + (5 * size)] asi, %l5 ; \
139 loader [base + (6 * size)] asi, %l6 ; \
140 loader [base + (7 * size)] asi, %l7 ; \
141 loader [base + (8 * size)] asi, %i0 ; \
142 loader [base + (9 * size)] asi, %i1 ; \
143 loader [base + (10 * size)] asi, %i2 ; \
144 loader [base + (11 * size)] asi, %i3 ; \
145 loader [base + (12 * size)] asi, %i4 ; \
146 loader [base + (13 * size)] asi, %i5 ; \
147 loader [base + (14 * size)] asi, %i6 ; \
148 loader [base + (15 * size)] asi, %i7
150 #define ERRATUM50(reg) mov reg, reg
152 #define KSTACK_SLOP 1024
155 * Sanity check the kernel stack and bail out if it's wrong.
156 * XXX: doesn't handle being on the panic stack.
158 #define KSTACK_CHECK \
160 stx %g1, [ASP_REG + 0] ; \
161 stx %g2, [ASP_REG + 8] ; \
162 add %sp, SPOFF, %g1 ; \
163 andcc %g1, (1 << PTR_SHIFT) - 1, %g0 ; \
164 bnz,a %xcc, tl1_kstack_fault ; \
166 ldx [PCPU(CURTHREAD)], %g2 ; \
167 ldx [%g2 + TD_KSTACK], %g2 ; \
168 add %g2, KSTACK_SLOP, %g2 ; \
169 subcc %g1, %g2, %g1 ; \
170 ble,a %xcc, tl1_kstack_fault ; \
172 set KSTACK_PAGES * PAGE_SIZE, %g2 ; \
174 bgt,a %xcc, tl1_kstack_fault ; \
176 ldx [ASP_REG + 8], %g2 ; \
177 ldx [ASP_REG + 0], %g1 ; \
184 ENTRY(tl1_kstack_fault)
190 #if KTR_COMPILE & KTR_TRAP
191 CATR(KTR_TRAP, "tl1_kstack_fault: tl=%#lx tpc=%#lx tnpc=%#lx"
192 , %g2, %g3, %g4, 7, 8, 9)
194 stx %g3, [%g2 + KTR_PARM1]
196 stx %g3, [%g2 + KTR_PARM1]
198 stx %g3, [%g2 + KTR_PARM1]
208 #if KTR_COMPILE & KTR_TRAP
210 "tl1_kstack_fault: sp=%#lx ks=%#lx cr=%#lx cs=%#lx ow=%#lx ws=%#lx"
211 , %g1, %g2, %g3, 7, 8, 9)
213 stx %g2, [%g1 + KTR_PARM1]
214 ldx [PCPU(CURTHREAD)], %g2
215 ldx [%g2 + TD_KSTACK], %g2
216 stx %g2, [%g1 + KTR_PARM2]
217 rdpr %canrestore, %g2
218 stx %g2, [%g1 + KTR_PARM3]
220 stx %g2, [%g1 + KTR_PARM4]
222 stx %g2, [%g1 + KTR_PARM5]
224 stx %g2, [%g1 + KTR_PARM6]
228 wrpr %g0, 0, %canrestore
229 wrpr %g0, 6, %cansave
230 wrpr %g0, 0, %otherwin
231 wrpr %g0, WSTATE_KERNEL, %wstate
233 sub ASP_REG, SPOFF + CCFSZ, %sp
238 mov T_KSTACK_FAULT | T_KERNEL, %o0
239 END(tl1_kstack_fault)
242 * Magic to resume from a spill or fill trap. If we get an alignment or an
243 * MMU fault during a spill or a fill, this macro will detect the fault and
244 * resume at a set instruction offset in the trap handler.
246 * To check if the previous trap was a spill/fill we convert the trapped pc
247 * to a trap type and verify that it is in the range of spill/fill vectors.
248 * The spill/fill vectors are types 0x80-0xff and 0x280-0x2ff, masking off the
249 * tl bit allows us to detect both ranges with one test.
252 * 0x80 <= (((%tpc - %tba) >> 5) & ~0x200) < 0x100
254 * To calculate the new pc we take advantage of the xor feature of wrpr.
255 * Forcing all the low bits of the trapped pc on we can produce any offset
256 * into the spill/fill vector. The size of a spill/fill trap vector is 0x80.
258 * 0x7f ^ 0x1f == 0x60
259 * 0x1f == (0x80 - 0x60) - 1
261 * Which are the offset and xor value used to resume from alignment faults.
265 * Determine if we have trapped inside of a spill/fill vector, and if so resume
266 * at a fixed instruction offset in the trap vector. Must be called on
269 #define RESUME_SPILLFILL_MAGIC(stxa_g0_sfsr, xor) \
271 stx %g1, [ASP_REG + 0] ; \
272 stx %g2, [ASP_REG + 8] ; \
276 sub %g1, %g2, %g2 ; \
278 andn %g2, 0x200, %g2 ; \
283 or %g1, 0x7f, %g1 ; \
284 wrpr %g1, xor, %tnpc ; \
286 ldx [ASP_REG + 8], %g2 ; \
287 ldx [ASP_REG + 0], %g1 ; \
290 9: ldx [ASP_REG + 8], %g2 ; \
291 ldx [ASP_REG + 0], %g1 ; \
295 * For certain faults we need to clear the SFSR MMU register before returning.
297 #define RSF_CLR_SFSR \
298 wr %g0, ASI_DMMU, %asi ; \
299 stxa %g0, [%g0 + AA_DMMU_SFSR] %asi
301 #define RSF_XOR(off) ((0x80 - off) - 1)
304 * Instruction offsets in spill and fill trap handlers for handling certain
305 * nested traps, and corresponding xor constants for wrpr.
307 #define RSF_OFF_ALIGN 0x60
308 #define RSF_OFF_MMU 0x70
310 #define RESUME_SPILLFILL_ALIGN \
311 RESUME_SPILLFILL_MAGIC(RSF_CLR_SFSR, RSF_XOR(RSF_OFF_ALIGN))
312 #define RESUME_SPILLFILL_MMU \
313 RESUME_SPILLFILL_MAGIC(EMPTY, RSF_XOR(RSF_OFF_MMU))
314 #define RESUME_SPILLFILL_MMU_CLR_SFSR \
315 RESUME_SPILLFILL_MAGIC(RSF_CLR_SFSR, RSF_XOR(RSF_OFF_MMU))
318 * Constant to add to %tnpc when taking a fill trap just before returning to
321 #define RSF_FILL_INC tl0_ret_fill_end - tl0_ret_fill
324 * Generate a T_SPILL or T_FILL trap if the window operation fails.
326 #define RSF_TRAP(type) \
327 ba %xcc, tl0_sftrap ; \
332 * Game over if the window operation fails.
334 #define RSF_FATAL(type) \
335 ba %xcc, rsf_fatal ; \
340 * Magic to resume from a failed fill a few instructions after the corrsponding
341 * restore. This is used on return from the kernel to usermode.
343 #define RSF_FILL_MAGIC \
345 add %g1, RSF_FILL_INC, %g1 ; \
346 wrpr %g1, 0, %tnpc ; \
351 * Spill to the pcb if a spill to the user stack in kernel mode fails.
353 #define RSF_SPILL_TOPCB \
354 ba,a %xcc, tl1_spill_topcb ; \
359 #if KTR_COMPILE & KTR_TRAP
360 CATR(KTR_TRAP, "rsf_fatal: bad window trap tt=%#lx type=%#lx"
361 , %g1, %g3, %g4, 7, 8, 9)
363 stx %g3, [%g1 + KTR_PARM1]
364 stx %g2, [%g1 + KTR_PARM2]
375 .globl intrnames, sintrnames
377 .space (IV_MAX + PIL_MAX) * (MAXCOMLEN + 1)
379 .quad (IV_MAX + PIL_MAX) * (MAXCOMLEN + 1)
381 .globl intrcnt, sintrcnt
383 .space (IV_MAX + PIL_MAX) * 8
385 .quad (IV_MAX + PIL_MAX) * 8
390 * Trap table and associated macros
392 * Due to its size a trap table is an inherently hard thing to represent in
393 * code in a clean way. There are approximately 1024 vectors, of 8 or 32
394 * instructions each, many of which are identical. The way that this is
395 * laid out is the instructions (8 or 32) for the actual trap vector appear
396 * as an AS macro. In general this code branches to tl0_trap or tl1_trap,
397 * but if not supporting code can be placed just after the definition of the
398 * macro. The macros are then instantiated in a different section (.trap),
399 * which is setup to be placed by the linker at the beginning of .text, and the
400 * code around the macros is moved to the end of trap table. In this way the
401 * code that must be sequential in memory can be split up, and located near
402 * its supporting code so that it is easier to follow.
406 * Clean window traps occur when %cleanwin is zero to ensure that data
407 * is not leaked between address spaces in registers.
427 wrpr %l7, 0, %cleanwin
434 * Stack fixups for entry from user mode. We are still running on the
435 * user stack, and with its live registers, so we must save soon. We
436 * are on alternate globals so we do have some registers. Set the
437 * transitional window state, and do the save. If this traps we
438 * attempt to spill a window to the user stack. If this fails, we
439 * spill the window to the pcb and continue. Spilling to the pcb
442 * NOTE: Must be called with alternate globals and clobbers %g1.
447 wrpr %g1, WSTATE_TRANSITION, %wstate
451 .macro tl0_setup type
460 * Generic trap type. Call trap() with the specified type.
468 * This is used to suck up the massive swaths of reserved trap types.
469 * Generates count "reserved" trap vectors.
471 .macro tl0_reserved count
479 wrpr %g1, WSTATE_NESTED, %wstate
480 save %sp, -(CCFSZ + TF_SIZEOF), %sp
483 .macro tl1_setup type
488 mov \type | T_KERNEL, %o0
496 .macro tl1_reserved count
502 .macro tl0_insn_excptn
503 wrpr %g0, PSTATE_ALT, %pstate
504 wr %g0, ASI_IMMU, %asi
506 ldxa [%g0 + AA_IMMU_SFSR] %asi, %g4
508 * XXX in theory, a store to AA_IMMU_SFSR must be immediately
509 * followed by a DONE, FLUSH or RETRY for USIII. In practice,
510 * this triggers a RED state exception though.
512 stxa %g0, [%g0 + AA_IMMU_SFSR] %asi
514 ba %xcc, tl0_sfsr_trap
515 mov T_INSTRUCTION_EXCEPTION, %g2
519 .macro tl0_data_excptn
520 wrpr %g0, PSTATE_ALT, %pstate
521 wr %g0, ASI_DMMU, %asi
522 ldxa [%g0 + AA_DMMU_SFAR] %asi, %g3
523 ldxa [%g0 + AA_DMMU_SFSR] %asi, %g4
524 stxa %g0, [%g0 + AA_DMMU_SFSR] %asi
526 ba %xcc, tl0_sfsr_trap
527 mov T_DATA_EXCEPTION, %g2
532 wr %g0, ASI_DMMU, %asi
533 ldxa [%g0 + AA_DMMU_SFAR] %asi, %g3
534 ldxa [%g0 + AA_DMMU_SFSR] %asi, %g4
535 stxa %g0, [%g0 + AA_DMMU_SFSR] %asi
537 ba %xcc, tl0_sfsr_trap
538 mov T_MEM_ADDRESS_NOT_ALIGNED, %g2
552 .macro tl0_intr level, mask
560 #define INTR(level, traplvl) \
561 tl ## traplvl ## _intr level, 1 << level
563 #define TICK(traplvl) \
564 tl ## traplvl ## _intr PIL_TICK, 0x10001
566 #define INTR_LEVEL(tl) \
583 .macro tl0_intr_level
588 ldxa [%g0] ASI_INTR_RECEIVE, %g1
589 andcc %g1, IRSR_BUSY, %g0
590 bnz,a,pt %xcc, intr_vector
592 ba,a,pt %xcc, intr_vector_stray
599 * Load the context and the virtual page number from the tag access
600 * register. We ignore the context.
602 wr %g0, ASI_IMMU, %asi
603 ldxa [%g0 + AA_IMMU_TAR] %asi, %g1
606 * Initialize the page size walker.
611 * Loop over all supported page sizes.
615 * Compute the page shift for the page size we are currently looking
620 add %g3, PAGE_SHIFT, %g3
623 * Extract the virtual page number from the contents of the tag
629 * Compute the TTE bucket address.
631 ldxa [%g0 + AA_IMMU_TSB] %asi, %g5
632 and %g3, TSB_BUCKET_MASK, %g4
633 sllx %g4, TSB_BUCKET_SHIFT + TTE_SHIFT, %g4
637 * Compute the TTE tag target.
639 sllx %g3, TV_SIZE_BITS, %g3
643 * Loop over the TTEs in this bucket.
647 * Load the TTE. Note that this instruction may fault, clobbering
648 * the contents of the tag access register, %g5, %g6, and %g7. We
649 * do not use %g5, and %g6 and %g7 are not used until this instruction
650 * completes successfully.
652 2: ldda [%g4] ASI_NUCLEUS_QUAD_LDD, %g6 /*, %g7 */
655 * Check that it's valid and executable and that the TTE tags match.
658 andcc %g7, TD_EXEC, %g0
665 * We matched a TTE, load the TLB.
669 * Set the reference bit, if it's currently clear.
671 andcc %g7, TD_REF, %g0
672 bz,a,pn %xcc, tl0_immu_miss_set_ref
676 * Load the TTE tag and data into the TLB and retry the instruction.
678 stxa %g1, [%g0 + AA_IMMU_TAR] %asi
679 stxa %g7, [%g0] ASI_ITLB_DATA_IN_REG
683 * Advance to the next TTE in this bucket, and check the low bits
684 * of the bucket pointer to see if we've finished the bucket.
686 3: add %g4, 1 << TTE_SHIFT, %g4
687 andcc %g4, (1 << (TSB_BUCKET_SHIFT + TTE_SHIFT)) - 1, %g0
692 * See if we just checked the largest page size, and advance to the
700 * Not in user TSB, call C code.
702 ba,a %xcc, tl0_immu_miss_trap
706 ENTRY(tl0_immu_miss_set_ref)
708 * Set the reference bit.
710 TTE_SET_REF(%g4, %g2, %g3, a, ASI_N)
713 * May have become invalid during casxa, in which case start over.
719 * Load the TTE tag and data into the TLB and retry the instruction.
721 stxa %g1, [%g0 + AA_IMMU_TAR] %asi
722 stxa %g2, [%g0] ASI_ITLB_DATA_IN_REG
724 END(tl0_immu_miss_set_ref)
726 ENTRY(tl0_immu_miss_trap)
728 * Put back the contents of the tag access register, in case we
731 sethi %hi(KERNBASE), %g2
732 stxa %g1, [%g0 + AA_IMMU_TAR] %asi
736 * Switch to alternate globals.
738 wrpr %g0, PSTATE_ALT, %pstate
741 * Reload the tag access register.
743 ldxa [%g0 + AA_IMMU_TAR] %asi, %g2
746 * Save the tag access register, and call common trap code.
753 mov T_INSTRUCTION_MISS, %o0
754 END(tl0_immu_miss_trap)
758 * Load the context and the virtual page number from the tag access
759 * register. We ignore the context.
761 wr %g0, ASI_DMMU, %asi
762 ldxa [%g0 + AA_DMMU_TAR] %asi, %g1
765 * Initialize the page size walker.
771 * Loop over all supported page sizes.
775 * Compute the page shift for the page size we are currently looking
780 add %g3, PAGE_SHIFT, %g3
783 * Extract the virtual page number from the contents of the tag
789 * Compute the TTE bucket address.
791 ldxa [%g0 + AA_DMMU_TSB] %asi, %g5
792 and %g3, TSB_BUCKET_MASK, %g4
793 sllx %g4, TSB_BUCKET_SHIFT + TTE_SHIFT, %g4
797 * Compute the TTE tag target.
799 sllx %g3, TV_SIZE_BITS, %g3
803 * Loop over the TTEs in this bucket.
807 * Load the TTE. Note that this instruction may fault, clobbering
808 * the contents of the tag access register, %g5, %g6, and %g7. We
809 * do not use %g5, and %g6 and %g7 are not used until this instruction
810 * completes successfully.
812 2: ldda [%g4] ASI_NUCLEUS_QUAD_LDD, %g6 /*, %g7 */
815 * Check that it's valid and that the virtual page numbers match.
823 * We matched a TTE, load the TLB.
827 * Set the reference bit, if it's currently clear.
829 andcc %g7, TD_REF, %g0
830 bz,a,pn %xcc, tl0_dmmu_miss_set_ref
834 * Load the TTE tag and data into the TLB and retry the instruction.
836 stxa %g1, [%g0 + AA_DMMU_TAR] %asi
837 stxa %g7, [%g0] ASI_DTLB_DATA_IN_REG
841 * Advance to the next TTE in this bucket, and check the low bits
842 * of the bucket pointer to see if we've finished the bucket.
844 3: add %g4, 1 << TTE_SHIFT, %g4
845 andcc %g4, (1 << (TSB_BUCKET_SHIFT + TTE_SHIFT)) - 1, %g0
850 * See if we just checked the largest page size, and advance to the
858 * Not in user TSB, call C code.
860 ba,a %xcc, tl0_dmmu_miss_trap
864 ENTRY(tl0_dmmu_miss_set_ref)
866 * Set the reference bit.
868 TTE_SET_REF(%g4, %g2, %g3, a, ASI_N)
871 * May have become invalid during casxa, in which case start over.
877 * Load the TTE tag and data into the TLB and retry the instruction.
879 stxa %g1, [%g0 + AA_DMMU_TAR] %asi
880 stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG
882 END(tl0_dmmu_miss_set_ref)
884 ENTRY(tl0_dmmu_miss_trap)
886 * Put back the contents of the tag access register, in case we
889 stxa %g1, [%g0 + AA_DMMU_TAR] %asi
893 * Switch to alternate globals.
895 wrpr %g0, PSTATE_ALT, %pstate
898 * Check if we actually came from the kernel.
906 * Reload the tag access register.
908 ldxa [%g0 + AA_DMMU_TAR] %asi, %g2
911 * Save the tag access register and call common trap code.
921 * Handle faults during window spill/fill.
923 1: RESUME_SPILLFILL_MMU
926 * Reload the tag access register.
928 ldxa [%g0 + AA_DMMU_TAR] %asi, %g2
935 mov T_DATA_MISS | T_KERNEL, %o0
936 END(tl0_dmmu_miss_trap)
939 ba,a %xcc, tl0_dmmu_prot_1
944 ENTRY(tl0_dmmu_prot_1)
946 * Load the context and the virtual page number from the tag access
947 * register. We ignore the context.
949 wr %g0, ASI_DMMU, %asi
950 ldxa [%g0 + AA_DMMU_TAR] %asi, %g1
953 * Initialize the page size walker.
959 * Loop over all supported page sizes.
963 * Compute the page shift for the page size we are currently looking
968 add %g3, PAGE_SHIFT, %g3
971 * Extract the virtual page number from the contents of the tag
977 * Compute the TTE bucket address.
979 ldxa [%g0 + AA_DMMU_TSB] %asi, %g5
980 and %g3, TSB_BUCKET_MASK, %g4
981 sllx %g4, TSB_BUCKET_SHIFT + TTE_SHIFT, %g4
985 * Compute the TTE tag target.
987 sllx %g3, TV_SIZE_BITS, %g3
991 * Loop over the TTEs in this bucket.
995 * Load the TTE. Note that this instruction may fault, clobbering
996 * the contents of the tag access register, %g5, %g6, and %g7. We
997 * do not use %g5, and %g6 and %g7 are not used until this instruction
998 * completes successfully.
1000 2: ldda [%g4] ASI_NUCLEUS_QUAD_LDD, %g6 /*, %g7 */
1003 * Check that it's valid and writable and that the virtual page
1007 andcc %g7, TD_SW, %g0
1014 * Set the hardware write bit.
1016 TTE_SET_W(%g4, %g2, %g3, a, ASI_N)
1019 * Delete the old TLB entry and clear the SFSR.
1021 srlx %g1, PAGE_SHIFT, %g3
1022 sllx %g3, PAGE_SHIFT, %g3
1023 stxa %g0, [%g3] ASI_DMMU_DEMAP
1024 stxa %g0, [%g0 + AA_DMMU_SFSR] %asi
1028 * May have become invalid during casxa, in which case start over.
1034 * Load the TTE data into the TLB and retry the instruction.
1036 stxa %g1, [%g0 + AA_DMMU_TAR] %asi
1037 stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG
1041 * Check the low bits to see if we've finished the bucket.
1043 4: add %g4, 1 << TTE_SHIFT, %g4
1044 andcc %g4, (1 << (TSB_BUCKET_SHIFT + TTE_SHIFT)) - 1, %g0
1049 * See if we just checked the largest page size, and advance to the
1057 * Not in user TSB, call C code.
1059 ba,a %xcc, tl0_dmmu_prot_trap
1061 END(tl0_dmmu_prot_1)
1063 ENTRY(tl0_dmmu_prot_trap)
1065 * Put back the contents of the tag access register, in case we
1068 stxa %g1, [%g0 + AA_DMMU_TAR] %asi
1072 * Switch to alternate globals.
1074 wrpr %g0, PSTATE_ALT, %pstate
1077 * Check if we actually came from the kernel.
1085 * Load the SFAR, SFSR and TAR.
1087 ldxa [%g0 + AA_DMMU_TAR] %asi, %g2
1088 ldxa [%g0 + AA_DMMU_SFAR] %asi, %g3
1089 ldxa [%g0 + AA_DMMU_SFSR] %asi, %g4
1090 stxa %g0, [%g0 + AA_DMMU_SFSR] %asi
1094 * Save the MMU registers and call common trap code.
1103 mov T_DATA_PROTECTION, %o0
1106 * Handle faults during window spill/fill.
1108 1: RESUME_SPILLFILL_MMU_CLR_SFSR
1111 * Load the SFAR, SFSR and TAR. Clear the SFSR.
1113 ldxa [%g0 + AA_DMMU_TAR] %asi, %g2
1114 ldxa [%g0 + AA_DMMU_SFAR] %asi, %g3
1115 ldxa [%g0 + AA_DMMU_SFSR] %asi, %g4
1116 stxa %g0, [%g0 + AA_DMMU_SFSR] %asi
1126 mov T_DATA_PROTECTION | T_KERNEL, %o0
1127 END(tl0_dmmu_prot_trap)
1129 .macro tl0_spill_0_n
1130 wr %g0, ASI_AIUP, %asi
1131 SPILL(stxa, %sp + SPOFF, 8, %asi)
1139 .macro tl0_spill_1_n
1140 wr %g0, ASI_AIUP, %asi
1141 SPILL(stwa, %sp, 4, %asi)
1150 wr %g0, ASI_AIUP, %asi
1151 FILL(ldxa, %sp + SPOFF, 8, %asi)
1160 wr %g0, ASI_AIUP, %asi
1161 FILL(lduwa, %sp, 4, %asi)
1171 and %g1, TSTATE_CWP_MASK, %g1
1180 .macro tl0_spill_bad count
1187 .macro tl0_fill_bad count
1203 .macro tl0_fp_restore
1204 ba,a %xcc, tl0_fp_restore
1209 ENTRY(tl0_fp_restore)
1210 ldx [PCB_REG + PCB_FLAGS], %g1
1211 andn %g1, PCB_FEF, %g1
1212 stx %g1, [PCB_REG + PCB_FLAGS]
1214 wr %g0, FPRS_FEF, %fprs
1215 wr %g0, ASI_BLK_S, %asi
1216 ldda [PCB_REG + PCB_UFP + (0 * 64)] %asi, %f0
1217 ldda [PCB_REG + PCB_UFP + (1 * 64)] %asi, %f16
1218 ldda [PCB_REG + PCB_UFP + (2 * 64)] %asi, %f32
1219 ldda [PCB_REG + PCB_UFP + (3 * 64)] %asi, %f48
1224 .macro tl1_insn_excptn
1225 wrpr %g0, PSTATE_ALT, %pstate
1226 wr %g0, ASI_IMMU, %asi
1228 ldxa [%g0 + AA_IMMU_SFSR] %asi, %g4
1230 * XXX in theory, a store to AA_IMMU_SFSR must be immediately
1231 * followed by a DONE, FLUSH or RETRY for USIII. In practice,
1232 * this triggers a RED state exception though.
1234 stxa %g0, [%g0 + AA_IMMU_SFSR] %asi
1236 ba %xcc, tl1_insn_exceptn_trap
1237 mov T_INSTRUCTION_EXCEPTION | T_KERNEL, %g2
1241 ENTRY(tl1_insn_exceptn_trap)
1249 END(tl1_insn_exceptn_trap)
1251 .macro tl1_fp_disabled
1252 ba,a %xcc, tl1_fp_disabled_1
1257 ENTRY(tl1_fp_disabled_1)
1259 set fpu_fault_begin, %g2
1261 cmp %g1, fpu_fault_size
1265 wr %g0, FPRS_FEF, %fprs
1266 wr %g0, ASI_BLK_S, %asi
1267 ldda [PCB_REG + PCB_KFP + (0 * 64)] %asi, %f0
1268 ldda [PCB_REG + PCB_KFP + (1 * 64)] %asi, %f16
1269 ldda [PCB_REG + PCB_KFP + (2 * 64)] %asi, %f32
1270 ldda [PCB_REG + PCB_KFP + (3 * 64)] %asi, %f48
1278 mov T_FP_DISABLED | T_KERNEL, %o0
1279 END(tl1_fp_disabled_1)
1281 .macro tl1_data_excptn
1282 wrpr %g0, PSTATE_ALT, %pstate
1283 ba,a %xcc, tl1_data_excptn_trap
1288 ENTRY(tl1_data_excptn_trap)
1289 RESUME_SPILLFILL_MMU_CLR_SFSR
1290 ba %xcc, tl1_sfsr_trap
1291 mov T_DATA_EXCEPTION | T_KERNEL, %g2
1292 END(tl1_data_excptn_trap)
1295 wrpr %g0, PSTATE_ALT, %pstate
1296 ba,a %xcc, tl1_align_trap
1301 ENTRY(tl1_align_trap)
1302 RESUME_SPILLFILL_ALIGN
1303 ba %xcc, tl1_sfsr_trap
1304 mov T_MEM_ADDRESS_NOT_ALIGNED | T_KERNEL, %g2
1307 ENTRY(tl1_sfsr_trap)
1308 wr %g0, ASI_DMMU, %asi
1309 ldxa [%g0 + AA_DMMU_SFAR] %asi, %g3
1310 ldxa [%g0 + AA_DMMU_SFSR] %asi, %g4
1311 stxa %g0, [%g0 + AA_DMMU_SFSR] %asi
1323 .macro tl1_intr level, mask
1331 .macro tl1_intr_level
1335 .macro tl1_immu_miss
1337 * Load the context and the virtual page number from the tag access
1338 * register. We ignore the context.
1340 wr %g0, ASI_IMMU, %asi
1341 ldxa [%g0 + AA_IMMU_TAR] %asi, %g5
1344 * Compute the address of the TTE. The TSB mask and address of the
1345 * TSB are patched at startup.
1347 .globl tl1_immu_miss_patch_tsb_1
1348 tl1_immu_miss_patch_tsb_1:
1349 sethi %uhi(TSB_KERNEL), %g6
1350 or %g6, %ulo(TSB_KERNEL), %g6
1352 sethi %hi(TSB_KERNEL), %g7
1354 .globl tl1_immu_miss_patch_tsb_mask_1
1355 tl1_immu_miss_patch_tsb_mask_1:
1356 sethi %hi(TSB_KERNEL_MASK), %g6
1357 or %g6, %lo(TSB_KERNEL_MASK), %g6
1359 srlx %g5, TAR_VPN_SHIFT, %g5
1361 sllx %g6, TTE_SHIFT, %g6
1367 .globl tl1_immu_miss_patch_quad_ldd_1
1368 tl1_immu_miss_patch_quad_ldd_1:
1369 ldda [%g6] TSB_QUAD_LDD, %g6 /*, %g7 */
1372 * Check that it's valid and executable and that the virtual page
1375 brgez,pn %g7, tl1_immu_miss_trap
1376 andcc %g7, TD_EXEC, %g0
1377 bz,pn %xcc, tl1_immu_miss_trap
1378 srlx %g6, TV_SIZE_BITS, %g6
1380 bne,pn %xcc, tl1_immu_miss_trap
1384 * Set the reference bit if it's currently clear.
1386 andcc %g7, TD_REF, %g0
1387 bz,a,pn %xcc, tl1_immu_miss_set_ref
1391 * Load the TTE data into the TLB and retry the instruction.
1393 stxa %g7, [%g0] ASI_ITLB_DATA_IN_REG
1398 ENTRY(tl1_immu_miss_set_ref)
1400 * Recompute the TTE address, which we clobbered loading the TTE.
1401 * The TSB mask and address of the TSB are patched at startup.
1403 .globl tl1_immu_miss_patch_tsb_2
1404 tl1_immu_miss_patch_tsb_2:
1405 sethi %uhi(TSB_KERNEL), %g6
1406 or %g6, %ulo(TSB_KERNEL), %g6
1408 sethi %hi(TSB_KERNEL), %g7
1410 .globl tl1_immu_miss_patch_tsb_mask_2
1411 tl1_immu_miss_patch_tsb_mask_2:
1412 sethi %hi(TSB_KERNEL_MASK), %g6
1413 or %g6, %lo(TSB_KERNEL_MASK), %g6
1416 sllx %g5, TTE_SHIFT, %g5
1420 * Set the reference bit.
1422 .globl tl1_immu_miss_patch_asi_1
1423 tl1_immu_miss_patch_asi_1:
1424 wr %g0, TSB_ASI, %asi
1425 TTE_SET_REF(%g5, %g6, %g7, a, %asi)
1428 * May have become invalid during casxa, in which case start over.
1434 * Load the TTE data into the TLB and retry the instruction.
1436 stxa %g6, [%g0] ASI_ITLB_DATA_IN_REG
1438 END(tl1_immu_miss_set_ref)
1440 ENTRY(tl1_immu_miss_trap)
1442 * Switch to alternate globals.
1444 wrpr %g0, PSTATE_ALT, %pstate
1446 ldxa [%g0 + AA_IMMU_TAR] %asi, %g2
1453 mov T_INSTRUCTION_MISS | T_KERNEL, %o0
1454 END(tl1_immu_miss_trap)
1456 .macro tl1_dmmu_miss
1458 * Load the context and the virtual page number from the tag access
1461 wr %g0, ASI_DMMU, %asi
1462 ldxa [%g0 + AA_DMMU_TAR] %asi, %g5
1465 * Extract the context from the contents of the tag access register.
1466 * If it's non-zero this is a fault on a user address. Note that the
1467 * faulting address is passed in %g1.
1469 sllx %g5, 64 - TAR_VPN_SHIFT, %g6
1470 brnz,a,pn %g6, tl1_dmmu_miss_user
1474 * Check for the direct mapped physical region. These addresses have
1475 * the high bit set so they are negative.
1477 brlz,pn %g5, tl1_dmmu_miss_direct
1481 * Compute the address of the TTE. The TSB mask and address of the
1482 * TSB are patched at startup.
1484 .globl tl1_dmmu_miss_patch_tsb_1
1485 tl1_dmmu_miss_patch_tsb_1:
1486 sethi %uhi(TSB_KERNEL), %g6
1487 or %g6, %ulo(TSB_KERNEL), %g6
1489 sethi %hi(TSB_KERNEL), %g7
1491 .globl tl1_dmmu_miss_patch_tsb_mask_1
1492 tl1_dmmu_miss_patch_tsb_mask_1:
1493 sethi %hi(TSB_KERNEL_MASK), %g6
1494 or %g6, %lo(TSB_KERNEL_MASK), %g6
1496 srlx %g5, TAR_VPN_SHIFT, %g5
1498 sllx %g6, TTE_SHIFT, %g6
1504 .globl tl1_dmmu_miss_patch_quad_ldd_1
1505 tl1_dmmu_miss_patch_quad_ldd_1:
1506 ldda [%g6] TSB_QUAD_LDD, %g6 /*, %g7 */
1509 * Check that it's valid and that the virtual page numbers match.
1511 brgez,pn %g7, tl1_dmmu_miss_trap
1512 srlx %g6, TV_SIZE_BITS, %g6
1514 bne,pn %xcc, tl1_dmmu_miss_trap
1518 * Set the reference bit if it's currently clear.
1520 andcc %g7, TD_REF, %g0
1521 bz,a,pt %xcc, tl1_dmmu_miss_set_ref
1525 * Load the TTE data into the TLB and retry the instruction.
1527 stxa %g7, [%g0] ASI_DTLB_DATA_IN_REG
1532 ENTRY(tl1_dmmu_miss_set_ref)
1534 * Recompute the TTE address, which we clobbered loading the TTE.
1535 * The TSB mask and address of the TSB are patched at startup.
1537 .globl tl1_dmmu_miss_patch_tsb_mask_2
1538 tl1_dmmu_miss_patch_tsb_2:
1539 sethi %uhi(TSB_KERNEL), %g6
1540 or %g6, %ulo(TSB_KERNEL), %g6
1542 sethi %hi(TSB_KERNEL), %g7
1544 .globl tl1_dmmu_miss_patch_tsb_2
1545 tl1_dmmu_miss_patch_tsb_mask_2:
1546 sethi %hi(TSB_KERNEL_MASK), %g6
1547 or %g6, %lo(TSB_KERNEL_MASK), %g6
1550 sllx %g5, TTE_SHIFT, %g5
1554 * Set the reference bit.
1556 .globl tl1_dmmu_miss_patch_asi_1
1557 tl1_dmmu_miss_patch_asi_1:
1558 wr %g0, TSB_ASI, %asi
1559 TTE_SET_REF(%g5, %g6, %g7, a, %asi)
1562 * May have become invalid during casxa, in which case start over.
1568 * Load the TTE data into the TLB and retry the instruction.
1570 stxa %g6, [%g0] ASI_DTLB_DATA_IN_REG
1572 END(tl1_dmmu_miss_set_ref)
1574 ENTRY(tl1_dmmu_miss_trap)
1576 * Switch to alternate globals.
1578 wrpr %g0, PSTATE_ALT, %pstate
1580 ldxa [%g0 + AA_DMMU_TAR] %asi, %g2
1589 mov T_DATA_MISS | T_KERNEL, %o0
1590 END(tl1_dmmu_miss_trap)
1592 ENTRY(tl1_dmmu_miss_direct)
1594 * Mask off the high bits of the virtual address to get the physical
1595 * address, and or in the TTE bits. The virtual address bits that
1596 * correspond to the TTE valid and page size bits are left set, so
1597 * they don't have to be included in the TTE bits below. We know they
1598 * are set because the virtual address is in the upper va hole.
1599 * NB: if we are taking advantage of the ASI_ATOMIC_QUAD_LDD_PHYS
1600 * and we get a miss on the directly accessed kernel TSB we must not
1601 * set TD_CV in order to access it uniformly bypassing the D$.
1603 setx TLB_DIRECT_ADDRESS_MASK, %g7, %g4
1605 setx TLB_DIRECT_TO_TTE_MASK, %g7, %g6
1607 .globl tl1_dmmu_miss_direct_patch_tsb_phys_1
1608 tl1_dmmu_miss_direct_patch_tsb_phys_1:
1609 sethi %uhi(TSB_KERNEL_PHYS), %g3
1610 or %g3, %ulo(TSB_KERNEL_PHYS), %g3
1612 sethi %hi(TSB_KERNEL_PHYS), %g3
1616 or %g5, TD_CP | TD_W, %g5
1617 .globl tl1_dmmu_miss_direct_patch_tsb_phys_end_1
1618 tl1_dmmu_miss_direct_patch_tsb_phys_end_1:
1619 sethi %uhi(TSB_KERNEL_PHYS_END), %g3
1620 or %g3, %ulo(TSB_KERNEL_PHYS_END), %g3
1622 sethi %hi(TSB_KERNEL_PHYS_END), %g7
1629 1: or %g5, TD_CV, %g5
1632 * Load the TTE data into the TLB and retry the instruction.
1634 2: stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG
1636 END(tl1_dmmu_miss_direct)
1638 .macro tl1_dmmu_prot
1639 ba,a %xcc, tl1_dmmu_prot_1
1644 ENTRY(tl1_dmmu_prot_1)
1646 * Load the context and the virtual page number from the tag access
1649 wr %g0, ASI_DMMU, %asi
1650 ldxa [%g0 + AA_DMMU_TAR] %asi, %g5
1653 * Extract the context from the contents of the tag access register.
1654 * If it's non-zero this is a fault on a user address. Note that the
1655 * faulting address is passed in %g1.
1657 sllx %g5, 64 - TAR_VPN_SHIFT, %g6
1658 brnz,a,pn %g6, tl1_dmmu_prot_user
1662 * Compute the address of the TTE. The TSB mask and address of the
1663 * TSB are patched at startup.
1665 .globl tl1_dmmu_prot_patch_tsb_1
1666 tl1_dmmu_prot_patch_tsb_1:
1667 sethi %uhi(TSB_KERNEL), %g6
1668 or %g6, %ulo(TSB_KERNEL), %g6
1670 sethi %hi(TSB_KERNEL), %g7
1672 .globl tl1_dmmu_prot_patch_tsb_mask_1
1673 tl1_dmmu_prot_patch_tsb_mask_1:
1674 sethi %hi(TSB_KERNEL_MASK), %g6
1675 or %g6, %lo(TSB_KERNEL_MASK), %g6
1677 srlx %g5, TAR_VPN_SHIFT, %g5
1679 sllx %g6, TTE_SHIFT, %g6
1685 .globl tl1_dmmu_prot_patch_quad_ldd_1
1686 tl1_dmmu_prot_patch_quad_ldd_1:
1687 ldda [%g6] TSB_QUAD_LDD, %g6 /*, %g7 */
1690 * Check that it's valid and writeable and that the virtual page
1693 brgez,pn %g7, tl1_dmmu_prot_trap
1694 andcc %g7, TD_SW, %g0
1695 bz,pn %xcc, tl1_dmmu_prot_trap
1696 srlx %g6, TV_SIZE_BITS, %g6
1698 bne,pn %xcc, tl1_dmmu_prot_trap
1702 * Delete the old TLB entry and clear the SFSR.
1704 sllx %g5, TAR_VPN_SHIFT, %g6
1705 or %g6, TLB_DEMAP_NUCLEUS, %g6
1706 stxa %g0, [%g6] ASI_DMMU_DEMAP
1707 stxa %g0, [%g0 + AA_DMMU_SFSR] %asi
1711 * Recompute the TTE address, which we clobbered loading the TTE.
1712 * The TSB mask and address of the TSB are patched at startup.
1714 .globl tl1_dmmu_prot_patch_tsb_2
1715 tl1_dmmu_prot_patch_tsb_2:
1716 sethi %uhi(TSB_KERNEL), %g6
1717 or %g6, %ulo(TSB_KERNEL), %g6
1719 sethi %hi(TSB_KERNEL), %g7
1721 .globl tl1_dmmu_prot_patch_tsb_mask_2
1722 tl1_dmmu_prot_patch_tsb_mask_2:
1723 sethi %hi(TSB_KERNEL_MASK), %g6
1724 or %g6, %lo(TSB_KERNEL_MASK), %g6
1726 sllx %g5, TTE_SHIFT, %g5
1730 * Set the hardware write bit.
1732 .globl tl1_dmmu_prot_patch_asi_1
1733 tl1_dmmu_prot_patch_asi_1:
1734 wr %g0, TSB_ASI, %asi
1735 TTE_SET_W(%g5, %g6, %g7, a, %asi)
1738 * May have become invalid during casxa, in which case start over.
1744 * Load the TTE data into the TLB and retry the instruction.
1746 stxa %g6, [%g0] ASI_DTLB_DATA_IN_REG
1748 END(tl1_dmmu_prot_1)
1750 ENTRY(tl1_dmmu_prot_trap)
1752 * Switch to alternate globals.
1754 wrpr %g0, PSTATE_ALT, %pstate
1757 * Load the SFAR, SFSR and TAR. Clear the SFSR.
1759 ldxa [%g0 + AA_DMMU_TAR] %asi, %g2
1760 ldxa [%g0 + AA_DMMU_SFAR] %asi, %g3
1761 ldxa [%g0 + AA_DMMU_SFSR] %asi, %g4
1762 stxa %g0, [%g0 + AA_DMMU_SFSR] %asi
1772 mov T_DATA_PROTECTION | T_KERNEL, %o0
1773 END(tl1_dmmu_prot_trap)
1775 .macro tl1_spill_0_n
1776 SPILL(stx, %sp + SPOFF, 8, EMPTY)
1784 .macro tl1_spill_2_n
1785 wr %g0, ASI_AIUP, %asi
1786 SPILL(stxa, %sp + SPOFF, 8, %asi)
1794 .macro tl1_spill_3_n
1795 wr %g0, ASI_AIUP, %asi
1796 SPILL(stwa, %sp, 4, %asi)
1804 .macro tl1_spill_7_n
1806 bnz,a,pn %xcc, tl1_spill_0_n
1809 SPILL(stw, %sp, 4, EMPTY)
1817 .macro tl1_spill_0_o
1818 wr %g0, ASI_AIUP, %asi
1819 SPILL(stxa, %sp + SPOFF, 8, %asi)
1827 .macro tl1_spill_1_o
1828 wr %g0, ASI_AIUP, %asi
1829 SPILL(stwa, %sp, 4, %asi)
1837 .macro tl1_spill_2_o
1843 FILL(ldx, %sp + SPOFF, 8, EMPTY)
1852 wr %g0, ASI_AIUP, %asi
1853 FILL(ldxa, %sp + SPOFF, 8, %asi)
1862 wr %g0, ASI_AIUP, %asi
1863 FILL(lduwa, %sp, 4, %asi)
1873 bnz,a,pt %xcc, tl1_fill_0_n
1876 FILL(lduw, %sp, 4, EMPTY)
1885 * This is used to spill windows that are still occupied with user
1886 * data on kernel entry to the pcb.
1888 ENTRY(tl1_spill_topcb)
1889 wrpr %g0, PSTATE_ALT, %pstate
1891 /* Free some globals for our use. */
1893 stx %g1, [ASP_REG + 0]
1894 stx %g2, [ASP_REG + 8]
1895 stx %g3, [ASP_REG + 16]
1897 ldx [PCB_REG + PCB_NSAVED], %g1
1899 sllx %g1, PTR_SHIFT, %g2
1900 add %g2, PCB_REG, %g2
1901 stx %sp, [%g2 + PCB_RWSP]
1903 sllx %g1, RW_SHIFT, %g2
1904 add %g2, PCB_REG, %g2
1905 SPILL(stx, %g2 + PCB_RW, 8, EMPTY)
1908 stx %g1, [PCB_REG + PCB_NSAVED]
1910 #if KTR_COMPILE & KTR_TRAP
1911 CATR(KTR_TRAP, "tl1_spill_topcb: pc=%#lx npc=%#lx sp=%#lx nsaved=%d"
1912 , %g1, %g2, %g3, 7, 8, 9)
1914 stx %g2, [%g1 + KTR_PARM1]
1916 stx %g2, [%g1 + KTR_PARM2]
1917 stx %sp, [%g1 + KTR_PARM3]
1918 ldx [PCB_REG + PCB_NSAVED], %g2
1919 stx %g2, [%g1 + KTR_PARM4]
1925 ldx [ASP_REG + 16], %g3
1926 ldx [ASP_REG + 8], %g2
1927 ldx [ASP_REG + 0], %g1
1930 END(tl1_spill_topcb)
1932 .macro tl1_spill_bad count
1939 .macro tl1_fill_bad count
1946 .macro tl1_soft count
1948 tl1_gen T_SOFT | T_KERNEL
1953 .globl tl_trap_begin
1961 tl0_reserved 8 ! 0x0-0x7
1963 tl0_insn_excptn ! 0x8
1964 tl0_reserved 1 ! 0x9
1966 tl0_gen T_INSTRUCTION_ERROR ! 0xa
1967 tl0_reserved 5 ! 0xb-0xf
1969 tl0_gen T_ILLEGAL_INSTRUCTION ! 0x10
1971 tl0_gen T_PRIVILEGED_OPCODE ! 0x11
1972 tl0_reserved 14 ! 0x12-0x1f
1974 tl0_gen T_FP_DISABLED ! 0x20
1976 tl0_gen T_FP_EXCEPTION_IEEE_754 ! 0x21
1978 tl0_gen T_FP_EXCEPTION_OTHER ! 0x22
1980 tl0_gen T_TAG_OVERFLOW ! 0x23
1984 tl0_gen T_DIVISION_BY_ZERO ! 0x28
1985 tl0_reserved 7 ! 0x29-0x2f
1987 tl0_data_excptn ! 0x30
1988 tl0_reserved 1 ! 0x31
1990 tl0_gen T_DATA_ERROR ! 0x32
1991 tl0_reserved 1 ! 0x33
1995 tl0_gen T_RESERVED ! 0x35
1997 tl0_gen T_RESERVED ! 0x36
1999 tl0_gen T_PRIVILEGED_ACTION ! 0x37
2000 tl0_reserved 9 ! 0x38-0x40
2002 tl0_intr_level ! 0x41-0x4f
2003 tl0_reserved 16 ! 0x50-0x5f
2007 tl0_gen T_PA_WATCHPOINT ! 0x61
2009 tl0_gen T_VA_WATCHPOINT ! 0x62
2011 tl0_gen T_CORRECTED_ECC_ERROR ! 0x63
2013 tl0_immu_miss ! 0x64
2015 tl0_dmmu_miss ! 0x68
2017 tl0_dmmu_prot ! 0x6c
2018 tl0_reserved 16 ! 0x70-0x7f
2020 tl0_spill_0_n ! 0x80
2022 tl0_spill_1_n ! 0x84
2023 tl0_spill_bad 14 ! 0x88-0xbf
2028 tl0_fill_bad 14 ! 0xc8-0xff
2030 tl0_gen T_SYSCALL ! 0x100
2031 tl0_gen T_BREAKPOINT ! 0x101
2032 tl0_gen T_DIVISION_BY_ZERO ! 0x102
2033 tl0_reserved 1 ! 0x103
2034 tl0_gen T_CLEAN_WINDOW ! 0x104
2035 tl0_gen T_RANGE_CHECK ! 0x105
2036 tl0_gen T_FIX_ALIGNMENT ! 0x106
2037 tl0_gen T_INTEGER_OVERFLOW ! 0x107
2038 tl0_gen T_SYSCALL ! 0x108
2039 tl0_gen T_SYSCALL ! 0x109
2040 tl0_fp_restore ! 0x10a
2041 tl0_reserved 5 ! 0x10b-0x10f
2042 tl0_gen T_TRAP_INSTRUCTION_16 ! 0x110
2043 tl0_gen T_TRAP_INSTRUCTION_17 ! 0x111
2044 tl0_gen T_TRAP_INSTRUCTION_18 ! 0x112
2045 tl0_gen T_TRAP_INSTRUCTION_19 ! 0x113
2046 tl0_gen T_TRAP_INSTRUCTION_20 ! 0x114
2047 tl0_gen T_TRAP_INSTRUCTION_21 ! 0x115
2048 tl0_gen T_TRAP_INSTRUCTION_22 ! 0x116
2049 tl0_gen T_TRAP_INSTRUCTION_23 ! 0x117
2050 tl0_gen T_TRAP_INSTRUCTION_24 ! 0x118
2051 tl0_gen T_TRAP_INSTRUCTION_25 ! 0x119
2052 tl0_gen T_TRAP_INSTRUCTION_26 ! 0x11a
2053 tl0_gen T_TRAP_INSTRUCTION_27 ! 0x11b
2054 tl0_gen T_TRAP_INSTRUCTION_28 ! 0x11c
2055 tl0_gen T_TRAP_INSTRUCTION_29 ! 0x11d
2056 tl0_gen T_TRAP_INSTRUCTION_30 ! 0x11e
2057 tl0_gen T_TRAP_INSTRUCTION_31 ! 0x11f
2058 tl0_reserved 32 ! 0x120-0x13f
2059 tl0_gen T_SYSCALL ! 0x140
2061 tl0_gen T_SYSCALL ! 0x142
2062 tl0_gen T_SYSCALL ! 0x143
2063 tl0_reserved 188 ! 0x144-0x1ff
2066 tl1_reserved 8 ! 0x200-0x207
2068 tl1_insn_excptn ! 0x208
2069 tl1_reserved 1 ! 0x209
2071 tl1_gen T_INSTRUCTION_ERROR ! 0x20a
2072 tl1_reserved 5 ! 0x20b-0x20f
2074 tl1_gen T_ILLEGAL_INSTRUCTION ! 0x210
2076 tl1_gen T_PRIVILEGED_OPCODE ! 0x211
2077 tl1_reserved 14 ! 0x212-0x21f
2079 tl1_fp_disabled ! 0x220
2081 tl1_gen T_FP_EXCEPTION_IEEE_754 ! 0x221
2083 tl1_gen T_FP_EXCEPTION_OTHER ! 0x222
2085 tl1_gen T_TAG_OVERFLOW ! 0x223
2087 clean_window ! 0x224
2089 tl1_gen T_DIVISION_BY_ZERO ! 0x228
2090 tl1_reserved 7 ! 0x229-0x22f
2092 tl1_data_excptn ! 0x230
2093 tl1_reserved 1 ! 0x231
2095 tl1_gen T_DATA_ERROR ! 0x232
2096 tl1_reserved 1 ! 0x233
2100 tl1_gen T_RESERVED ! 0x235
2102 tl1_gen T_RESERVED ! 0x236
2104 tl1_gen T_PRIVILEGED_ACTION ! 0x237
2105 tl1_reserved 9 ! 0x238-0x240
2107 tl1_intr_level ! 0x241-0x24f
2108 tl1_reserved 16 ! 0x250-0x25f
2112 tl1_gen T_PA_WATCHPOINT ! 0x261
2114 tl1_gen T_VA_WATCHPOINT ! 0x262
2116 tl1_gen T_CORRECTED_ECC_ERROR ! 0x263
2118 tl1_immu_miss ! 0x264
2120 tl1_dmmu_miss ! 0x268
2122 tl1_dmmu_prot ! 0x26c
2123 tl1_reserved 16 ! 0x270-0x27f
2125 tl1_spill_0_n ! 0x280
2126 tl1_spill_bad 1 ! 0x284
2128 tl1_spill_2_n ! 0x288
2130 tl1_spill_3_n ! 0x28c
2131 tl1_spill_bad 3 ! 0x290-0x29b
2133 tl1_spill_7_n ! 0x29c
2135 tl1_spill_0_o ! 0x2a0
2137 tl1_spill_1_o ! 0x2a4
2139 tl1_spill_2_o ! 0x2a8
2140 tl1_spill_bad 5 ! 0x2ac-0x2bf
2142 tl1_fill_0_n ! 0x2c0
2143 tl1_fill_bad 1 ! 0x2c4
2145 tl1_fill_2_n ! 0x2c8
2147 tl1_fill_3_n ! 0x2cc
2148 tl1_fill_bad 3 ! 0x2d0-0x2db
2150 tl1_fill_7_n ! 0x2dc
2151 tl1_fill_bad 8 ! 0x2e0-0x2ff
2152 tl1_reserved 1 ! 0x300
2154 tl1_gen T_BREAKPOINT ! 0x301
2155 tl1_gen T_RSTRWP_PHYS ! 0x302
2156 tl1_gen T_RSTRWP_VIRT ! 0x303
2157 tl1_reserved 252 ! 0x304-0x3ff
2164 * User trap entry point
2166 * void tl0_utrap(u_long type, u_long o1, u_long o2, u_long tar, u_long sfar,
2169 * This handles redirecting a trap back to usermode as a user trap. The user
2170 * program must have first registered a trap handler with the kernel using
2171 * sysarch(SPARC_UTRAP_INSTALL). The trap handler is passed enough state
2172 * for it to return to the trapping code directly, it will not return through
2173 * the kernel. The trap type is passed in %o0, all out registers must be
2174 * passed through to tl0_trap or to usermode untouched. Note that the
2175 * parameters passed in out registers may be used by the user trap handler.
2176 * Do not change the registers they are passed in or you will break the ABI.
2178 * If the trap type allows user traps, setup state to execute the user trap
2179 * handler and bounce back to usermode, otherwise branch to tl0_trap.
2183 * Check if the trap type allows user traps.
2186 bge,a,pt %xcc, tl0_trap
2190 * Load the user trap handler from the utrap table.
2192 ldx [PCPU(CURTHREAD)], %l0
2193 ldx [%l0 + TD_PROC], %l0
2194 ldx [%l0 + P_MD + MD_UTRAP], %l0
2195 brz,pt %l0, tl0_trap
2196 sllx %o0, PTR_SHIFT, %l1
2197 ldx [%l0 + %l1], %l0
2198 brz,a,pt %l0, tl0_trap
2202 * If the save we did on entry to the kernel had to spill a window
2203 * to the pcb, pretend we took a spill trap instead. Any windows
2204 * that are in the pcb must be copied out or the fill handler will
2205 * not be able to find them, since the user trap handler returns
2206 * directly to the trapping code. Note that we only support precise
2207 * user traps, which implies that the condition that caused the trap
2208 * in the first place is still valid, so it will occur again when we
2209 * re-execute the trapping instruction.
2211 ldx [PCB_REG + PCB_NSAVED], %l1
2212 brnz,a,pn %l1, tl0_trap
2216 * Pass %fsr in %l4, %tstate in %l5, %tpc in %l6 and %tnpc in %l7.
2217 * The ABI specifies only %l6 and %l7, but we need to pass %fsr or
2218 * it may be clobbered by an interrupt before the user trap code
2219 * can read it, and we must pass %tstate in order to restore %ccr
2220 * and %asi. The %fsr must be stored to memory, so we use the
2221 * temporary stack for that.
2224 or %l1, FPRS_FEF, %l2
2237 * Setup %tnpc to return to.
2242 * Setup %wstate for return, clear WSTATE_TRANSITION.
2245 and %l1, WSTATE_NORMAL_MASK, %l1
2246 wrpr %l1, 0, %wstate
2249 * Setup %tstate for return, change the saved cwp to point to the
2250 * current window instead of the window at the time of the trap.
2252 andn %l5, TSTATE_CWP_MASK, %l1
2254 wrpr %l1, %l2, %tstate
2257 * Setup %sp. Userland processes will crash if this is not setup.
2262 * Execute the user trap handler.
2268 * (Real) User trap entry point
2270 * void tl0_trap(u_int type, u_long o1, u_long o2, u_long tar, u_long sfsr,
2273 * The following setup has been performed:
2274 * - the windows have been split and the active user window has been saved
2275 * (maybe just to the pcb)
2276 * - we are on alternate globals and interrupts are disabled
2278 * We switch to the kernel stack, build a trapframe, switch to normal
2279 * globals, enable interrupts and call trap.
2281 * NOTE: We must be very careful setting up the per-cpu pointer. We know that
2282 * it has been pre-set in alternate globals, so we read it from there and setup
2283 * the normal %g7 *before* enabling interrupts. This avoids any possibility
2284 * of cpu migration and using the wrong pcpup.
2288 * Force kernel store order.
2290 wrpr %g0, PSTATE_ALT, %pstate
2299 #if KTR_COMPILE & KTR_TRAP
2301 "tl0_trap: td=%p type=%#x pil=%#lx pc=%#lx npc=%#lx sp=%#lx"
2302 , %g1, %g2, %g3, 7, 8, 9)
2303 ldx [PCPU(CURTHREAD)], %g2
2304 stx %g2, [%g1 + KTR_PARM1]
2305 stx %o0, [%g1 + KTR_PARM2]
2307 stx %g2, [%g1 + KTR_PARM3]
2308 stx %l1, [%g1 + KTR_PARM4]
2309 stx %l2, [%g1 + KTR_PARM5]
2310 stx %i6, [%g1 + KTR_PARM6]
2314 1: and %l5, WSTATE_NORMAL_MASK, %l5
2315 sllx %l5, WSTATE_OTHER_SHIFT, %l5
2316 wrpr %l5, WSTATE_KERNEL, %wstate
2317 rdpr %canrestore, %l6
2318 wrpr %l6, 0, %otherwin
2319 wrpr %g0, 0, %canrestore
2321 sub PCB_REG, SPOFF + CCFSZ + TF_SIZEOF, %sp
2323 stx %o0, [%sp + SPOFF + CCFSZ + TF_TYPE]
2324 stx %o1, [%sp + SPOFF + CCFSZ + TF_LEVEL]
2325 stx %o3, [%sp + SPOFF + CCFSZ + TF_TAR]
2326 stx %o4, [%sp + SPOFF + CCFSZ + TF_SFAR]
2327 stx %o5, [%sp + SPOFF + CCFSZ + TF_SFSR]
2329 stx %l0, [%sp + SPOFF + CCFSZ + TF_TSTATE]
2330 stx %l1, [%sp + SPOFF + CCFSZ + TF_TPC]
2331 stx %l2, [%sp + SPOFF + CCFSZ + TF_TNPC]
2332 stx %l3, [%sp + SPOFF + CCFSZ + TF_Y]
2333 stx %l4, [%sp + SPOFF + CCFSZ + TF_FPRS]
2334 stx %l5, [%sp + SPOFF + CCFSZ + TF_WSTATE]
2336 wr %g0, FPRS_FEF, %fprs
2337 stx %fsr, [%sp + SPOFF + CCFSZ + TF_FSR]
2339 stx %l6, [%sp + SPOFF + CCFSZ + TF_GSR]
2344 wrpr %g0, PSTATE_NORMAL, %pstate
2346 stx %g6, [%sp + SPOFF + CCFSZ + TF_G6]
2347 stx %g7, [%sp + SPOFF + CCFSZ + TF_G7]
2351 wrpr %g0, PSTATE_KERNEL, %pstate
2353 stx %i0, [%sp + SPOFF + CCFSZ + TF_O0]
2354 stx %i1, [%sp + SPOFF + CCFSZ + TF_O1]
2355 stx %i2, [%sp + SPOFF + CCFSZ + TF_O2]
2356 stx %i3, [%sp + SPOFF + CCFSZ + TF_O3]
2357 stx %i4, [%sp + SPOFF + CCFSZ + TF_O4]
2358 stx %i5, [%sp + SPOFF + CCFSZ + TF_O5]
2359 stx %i6, [%sp + SPOFF + CCFSZ + TF_O6]
2360 stx %i7, [%sp + SPOFF + CCFSZ + TF_O7]
2362 stx %g1, [%sp + SPOFF + CCFSZ + TF_G1]
2363 stx %g2, [%sp + SPOFF + CCFSZ + TF_G2]
2364 stx %g3, [%sp + SPOFF + CCFSZ + TF_G3]
2365 stx %g4, [%sp + SPOFF + CCFSZ + TF_G4]
2366 stx %g5, [%sp + SPOFF + CCFSZ + TF_G5]
2368 set tl0_ret - 8, %o7
2370 add %sp, CCFSZ + SPOFF, %o0
2374 * void tl0_intr(u_int level, u_int mask)
2378 * Force kernel store order.
2380 wrpr %g0, PSTATE_ALT, %pstate
2389 #if KTR_COMPILE & KTR_INTR
2391 "tl0_intr: td=%p level=%#x pil=%#lx pc=%#lx npc=%#lx sp=%#lx"
2392 , %g1, %g2, %g3, 7, 8, 9)
2393 ldx [PCPU(CURTHREAD)], %g2
2394 stx %g2, [%g1 + KTR_PARM1]
2395 stx %o0, [%g1 + KTR_PARM2]
2397 stx %g2, [%g1 + KTR_PARM3]
2398 stx %l1, [%g1 + KTR_PARM4]
2399 stx %l2, [%g1 + KTR_PARM5]
2400 stx %i6, [%g1 + KTR_PARM6]
2405 wr %o1, 0, %clear_softint
2407 and %l5, WSTATE_NORMAL_MASK, %l5
2408 sllx %l5, WSTATE_OTHER_SHIFT, %l5
2409 wrpr %l5, WSTATE_KERNEL, %wstate
2410 rdpr %canrestore, %l6
2411 wrpr %l6, 0, %otherwin
2412 wrpr %g0, 0, %canrestore
2414 sub PCB_REG, SPOFF + CCFSZ + TF_SIZEOF, %sp
2416 stx %l0, [%sp + SPOFF + CCFSZ + TF_TSTATE]
2417 stx %l1, [%sp + SPOFF + CCFSZ + TF_TPC]
2418 stx %l2, [%sp + SPOFF + CCFSZ + TF_TNPC]
2419 stx %l3, [%sp + SPOFF + CCFSZ + TF_Y]
2420 stx %l4, [%sp + SPOFF + CCFSZ + TF_FPRS]
2421 stx %l5, [%sp + SPOFF + CCFSZ + TF_WSTATE]
2423 wr %g0, FPRS_FEF, %fprs
2424 stx %fsr, [%sp + SPOFF + CCFSZ + TF_FSR]
2426 stx %l6, [%sp + SPOFF + CCFSZ + TF_GSR]
2430 mov T_INTERRUPT, %o1
2432 stx %o0, [%sp + SPOFF + CCFSZ + TF_LEVEL]
2433 stx %o1, [%sp + SPOFF + CCFSZ + TF_TYPE]
2437 wrpr %g0, PSTATE_NORMAL, %pstate
2439 stx %g1, [%sp + SPOFF + CCFSZ + TF_G1]
2440 stx %g2, [%sp + SPOFF + CCFSZ + TF_G2]
2441 stx %g3, [%sp + SPOFF + CCFSZ + TF_G3]
2442 stx %g4, [%sp + SPOFF + CCFSZ + TF_G4]
2443 stx %g5, [%sp + SPOFF + CCFSZ + TF_G5]
2444 stx %g6, [%sp + SPOFF + CCFSZ + TF_G6]
2445 stx %g7, [%sp + SPOFF + CCFSZ + TF_G7]
2449 wrpr %g0, PSTATE_KERNEL, %pstate
2451 stx %i0, [%sp + SPOFF + CCFSZ + TF_O0]
2452 stx %i1, [%sp + SPOFF + CCFSZ + TF_O1]
2453 stx %i2, [%sp + SPOFF + CCFSZ + TF_O2]
2454 stx %i3, [%sp + SPOFF + CCFSZ + TF_O3]
2455 stx %i4, [%sp + SPOFF + CCFSZ + TF_O4]
2456 stx %i5, [%sp + SPOFF + CCFSZ + TF_O5]
2457 stx %i6, [%sp + SPOFF + CCFSZ + TF_O6]
2458 stx %i7, [%sp + SPOFF + CCFSZ + TF_O7]
2460 SET(intr_handlers, %l1, %l0)
2461 sllx %l3, IH_SHIFT, %l1
2462 ldx [%l0 + %l1], %l1
2463 KASSERT(%l1, "tl0_intr: ih null")
2465 add %sp, CCFSZ + SPOFF, %o0
2467 /* %l3 contains PIL */
2468 SET(intrcnt, %l1, %l2)
2469 prefetcha [%l2] ASI_N, 1
2470 SET(pil_countp, %l1, %l0)
2472 lduh [%l0 + %l1], %l0
2479 call counter_intr_inc
2487 * Initiate return to usermode.
2489 * Called with a trapframe on the stack. The window that was setup in
2490 * tl0_trap may have been used by "fast" trap handlers that pretend to be
2491 * leaf functions, so all ins and locals may have been clobbered since
2494 * This code is rather long and complicated.
2498 * Check for pending asts atomically with returning. We must raise
2499 * the PIL before checking, and if no asts are found the PIL must
2500 * remain raised until the retry is executed, or we risk missing asts
2501 * caused by interrupts occurring after the test. If the PIL is
2502 * lowered, as it is when we call ast, the check must be re-executed.
2504 wrpr %g0, PIL_TICK, %pil
2505 ldx [PCPU(CURTHREAD)], %l0
2506 lduw [%l0 + TD_FLAGS], %l1
2507 set TDF_ASTPENDING | TDF_NEEDRESCHED, %l2
2513 * We have an AST. Re-enable interrupts and handle it, then restart
2514 * the return sequence.
2518 add %sp, CCFSZ + SPOFF, %o0
2523 * Check for windows that were spilled to the pcb and need to be
2524 * copied out. This must be the last thing that is done before the
2525 * return to usermode. If there are still user windows in the cpu
2526 * and we call a nested function after this, which causes them to be
2527 * spilled to the pcb, they will not be copied out and the stack will
2530 1: ldx [PCB_REG + PCB_NSAVED], %l1
2535 stx %o0, [%sp + SPOFF + CCFSZ + TF_TYPE]
2537 add %sp, SPOFF + CCFSZ, %o0
2542 * Restore the out and most global registers from the trapframe.
2543 * The ins will become the outs when we restore below.
2545 2: ldx [%sp + SPOFF + CCFSZ + TF_O0], %i0
2546 ldx [%sp + SPOFF + CCFSZ + TF_O1], %i1
2547 ldx [%sp + SPOFF + CCFSZ + TF_O2], %i2
2548 ldx [%sp + SPOFF + CCFSZ + TF_O3], %i3
2549 ldx [%sp + SPOFF + CCFSZ + TF_O4], %i4
2550 ldx [%sp + SPOFF + CCFSZ + TF_O5], %i5
2551 ldx [%sp + SPOFF + CCFSZ + TF_O6], %i6
2552 ldx [%sp + SPOFF + CCFSZ + TF_O7], %i7
2554 ldx [%sp + SPOFF + CCFSZ + TF_G1], %g1
2555 ldx [%sp + SPOFF + CCFSZ + TF_G2], %g2
2556 ldx [%sp + SPOFF + CCFSZ + TF_G3], %g3
2557 ldx [%sp + SPOFF + CCFSZ + TF_G4], %g4
2558 ldx [%sp + SPOFF + CCFSZ + TF_G5], %g5
2561 * Load everything we need to restore below before disabling
2564 ldx [%sp + SPOFF + CCFSZ + TF_FPRS], %l0
2565 ldx [%sp + SPOFF + CCFSZ + TF_GSR], %l1
2566 ldx [%sp + SPOFF + CCFSZ + TF_TNPC], %l2
2567 ldx [%sp + SPOFF + CCFSZ + TF_TPC], %l3
2568 ldx [%sp + SPOFF + CCFSZ + TF_TSTATE], %l4
2569 ldx [%sp + SPOFF + CCFSZ + TF_Y], %l5
2570 ldx [%sp + SPOFF + CCFSZ + TF_WSTATE], %l6
2573 * Disable interrupts to restore the special globals. They are not
2574 * saved and restored for all kernel traps, so an interrupt at the
2575 * wrong time would clobber them.
2577 wrpr %g0, PSTATE_NORMAL, %pstate
2579 ldx [%sp + SPOFF + CCFSZ + TF_G6], %g6
2580 ldx [%sp + SPOFF + CCFSZ + TF_G7], %g7
2583 * Switch to alternate globals. This frees up some registers we
2584 * can use after the restore changes our window.
2586 wrpr %g0, PSTATE_ALT, %pstate
2589 * Drop %pil to zero. It must have been zero at the time of the
2590 * trap, since we were in usermode, but it was raised above in
2591 * order to check for asts atomically. We have interrupts disabled
2592 * so any interrupts will not be serviced until we complete the
2593 * return to usermode.
2598 * Save %fprs in an alternate global so it can be restored after the
2599 * restore instruction below. If we restore it before the restore,
2600 * and the restore traps we may run for a while with floating point
2601 * enabled in the kernel, which we want to avoid.
2606 * Restore %fsr and %gsr. These need floating point enabled in %fprs,
2607 * so we set it temporarily and then clear it.
2609 wr %g0, FPRS_FEF, %fprs
2610 ldx [%sp + SPOFF + CCFSZ + TF_FSR], %fsr
2615 * Restore program counters. This could be done after the restore
2616 * but we're out of alternate globals to store them in...
2622 * Save %tstate in an alternate global and clear the %cwp field. %cwp
2623 * will be affected by the restore below and we need to make sure it
2624 * points to the current window at that time, not the window that was
2625 * active at the time of the trap.
2627 andn %l4, TSTATE_CWP_MASK, %g2
2630 * Restore %y. Could also be below if we had more alternate globals.
2635 * Setup %wstate for return. We need to restore the user window state
2636 * which we saved in wstate.other when we trapped. We also need to
2637 * set the transition bit so the restore will be handled specially
2638 * if it traps, use the xor feature of wrpr to do that.
2640 srlx %l6, WSTATE_OTHER_SHIFT, %g3
2641 wrpr %g3, WSTATE_TRANSITION, %wstate
2644 * Setup window management registers for return. If not all user
2645 * windows were spilled in the kernel %otherwin will be non-zero,
2646 * so we need to transfer it to %canrestore to correctly restore
2647 * those windows. Otherwise everything gets set to zero and the
2648 * restore below will fill a window directly from the user stack.
2651 wrpr %o0, 0, %canrestore
2652 wrpr %g0, 0, %otherwin
2653 wrpr %o0, 0, %cleanwin
2656 * Now do the restore. If this instruction causes a fill trap which
2657 * fails to fill a window from the user stack, we will resume at
2658 * tl0_ret_fill_end and call back into the kernel.
2664 * We made it. We're back in the window that was active at the time
2665 * of the trap, and ready to return to usermode.
2669 * Restore %frps. This was saved in an alternate global above.
2674 * Fixup %tstate so the saved %cwp points to the current window and
2678 wrpr %g2, %g4, %tstate
2681 * Restore the user window state. The transition bit was set above
2682 * for special handling of the restore, this clears it.
2684 wrpr %g3, 0, %wstate
2686 #if KTR_COMPILE & KTR_TRAP
2687 CATR(KTR_TRAP, "tl0_ret: td=%#lx pil=%#lx pc=%#lx npc=%#lx sp=%#lx"
2688 , %g2, %g3, %g4, 7, 8, 9)
2689 ldx [PCPU(CURTHREAD)], %g3
2690 stx %g3, [%g2 + KTR_PARM1]
2692 stx %g3, [%g2 + KTR_PARM2]
2694 stx %g3, [%g2 + KTR_PARM3]
2696 stx %g3, [%g2 + KTR_PARM4]
2697 stx %sp, [%g2 + KTR_PARM5]
2702 * Return to usermode.
2707 #if KTR_COMPILE & KTR_TRAP
2708 CATR(KTR_TRAP, "tl0_ret: fill magic ps=%#lx ws=%#lx sp=%#lx"
2709 , %l0, %l1, %l2, 7, 8, 9)
2711 stx %l1, [%l0 + KTR_PARM1]
2712 stx %l6, [%l0 + KTR_PARM2]
2713 stx %sp, [%l0 + KTR_PARM3]
2718 * The restore above caused a fill trap and the fill handler was
2719 * unable to fill a window from the user stack. The special fill
2720 * handler recognized this and punted, sending us here. We need
2721 * to carefully undo any state that was restored before the restore
2722 * was executed and call trap again. Trap will copyin a window
2723 * from the user stack which will fault in the page we need so the
2724 * restore above will succeed when we try again. If this fails
2725 * the process has trashed its stack, so we kill it.
2729 * Restore the kernel window state. This was saved in %l6 above, and
2730 * since the restore failed we're back in the same window.
2732 wrpr %l6, 0, %wstate
2735 * Restore the normal globals which have predefined values in the
2736 * kernel. We clobbered them above restoring the user's globals
2737 * so this is very important.
2738 * XXX PSTATE_ALT must already be set.
2740 wrpr %g0, PSTATE_ALT, %pstate
2743 wrpr %g0, PSTATE_NORMAL, %pstate
2746 wrpr %g0, PSTATE_KERNEL, %pstate
2749 * Simulate a fill trap and then start the whole return sequence over
2750 * again. This is special because it only copies in 1 window, not 2
2751 * as we would for a normal failed fill. This may be the first time
2752 * the process has been run, so there may not be 2 windows worth of
2756 stx %o0, [%sp + SPOFF + CCFSZ + TF_TYPE]
2758 add %sp, SPOFF + CCFSZ, %o0
2764 * Kernel trap entry point
2766 * void tl1_trap(u_int type, u_long o1, u_long o2, u_long tar, u_long sfar,
2769 * This is easy because the stack is already setup and the windows don't need
2770 * to be split. We build a trapframe and call trap(), the same as above, but
2771 * the outs don't need to be saved.
2781 #if KTR_COMPILE & KTR_TRAP
2782 CATR(KTR_TRAP, "tl1_trap: td=%p type=%#lx pil=%#lx pc=%#lx sp=%#lx"
2783 , %g1, %g2, %g3, 7, 8, 9)
2784 ldx [PCPU(CURTHREAD)], %g2
2785 stx %g2, [%g1 + KTR_PARM1]
2786 stx %o0, [%g1 + KTR_PARM2]
2787 stx %l3, [%g1 + KTR_PARM3]
2788 stx %l1, [%g1 + KTR_PARM4]
2789 stx %i6, [%g1 + KTR_PARM5]
2795 and %l5, WSTATE_OTHER_MASK, %l5
2796 wrpr %l5, WSTATE_KERNEL, %wstate
2798 stx %o0, [%sp + SPOFF + CCFSZ + TF_TYPE]
2799 stx %o1, [%sp + SPOFF + CCFSZ + TF_LEVEL]
2800 stx %o3, [%sp + SPOFF + CCFSZ + TF_TAR]
2801 stx %o4, [%sp + SPOFF + CCFSZ + TF_SFAR]
2802 stx %o5, [%sp + SPOFF + CCFSZ + TF_SFSR]
2804 stx %l0, [%sp + SPOFF + CCFSZ + TF_TSTATE]
2805 stx %l1, [%sp + SPOFF + CCFSZ + TF_TPC]
2806 stx %l2, [%sp + SPOFF + CCFSZ + TF_TNPC]
2807 stx %l3, [%sp + SPOFF + CCFSZ + TF_PIL]
2808 stx %l4, [%sp + SPOFF + CCFSZ + TF_Y]
2812 wrpr %g0, PSTATE_NORMAL, %pstate
2814 stx %g6, [%sp + SPOFF + CCFSZ + TF_G6]
2815 stx %g7, [%sp + SPOFF + CCFSZ + TF_G7]
2819 wrpr %g0, PSTATE_KERNEL, %pstate
2821 stx %i0, [%sp + SPOFF + CCFSZ + TF_O0]
2822 stx %i1, [%sp + SPOFF + CCFSZ + TF_O1]
2823 stx %i2, [%sp + SPOFF + CCFSZ + TF_O2]
2824 stx %i3, [%sp + SPOFF + CCFSZ + TF_O3]
2825 stx %i4, [%sp + SPOFF + CCFSZ + TF_O4]
2826 stx %i5, [%sp + SPOFF + CCFSZ + TF_O5]
2827 stx %i6, [%sp + SPOFF + CCFSZ + TF_O6]
2828 stx %i7, [%sp + SPOFF + CCFSZ + TF_O7]
2830 stx %g1, [%sp + SPOFF + CCFSZ + TF_G1]
2831 stx %g2, [%sp + SPOFF + CCFSZ + TF_G2]
2832 stx %g3, [%sp + SPOFF + CCFSZ + TF_G3]
2833 stx %g4, [%sp + SPOFF + CCFSZ + TF_G4]
2834 stx %g5, [%sp + SPOFF + CCFSZ + TF_G5]
2836 set tl1_ret - 8, %o7
2838 add %sp, CCFSZ + SPOFF, %o0
2842 ldx [%sp + SPOFF + CCFSZ + TF_O0], %i0
2843 ldx [%sp + SPOFF + CCFSZ + TF_O1], %i1
2844 ldx [%sp + SPOFF + CCFSZ + TF_O2], %i2
2845 ldx [%sp + SPOFF + CCFSZ + TF_O3], %i3
2846 ldx [%sp + SPOFF + CCFSZ + TF_O4], %i4
2847 ldx [%sp + SPOFF + CCFSZ + TF_O5], %i5
2848 ldx [%sp + SPOFF + CCFSZ + TF_O6], %i6
2849 ldx [%sp + SPOFF + CCFSZ + TF_O7], %i7
2851 ldx [%sp + SPOFF + CCFSZ + TF_G1], %g1
2852 ldx [%sp + SPOFF + CCFSZ + TF_G2], %g2
2853 ldx [%sp + SPOFF + CCFSZ + TF_G3], %g3
2854 ldx [%sp + SPOFF + CCFSZ + TF_G4], %g4
2855 ldx [%sp + SPOFF + CCFSZ + TF_G5], %g5
2857 ldx [%sp + SPOFF + CCFSZ + TF_TSTATE], %l0
2858 ldx [%sp + SPOFF + CCFSZ + TF_TPC], %l1
2859 ldx [%sp + SPOFF + CCFSZ + TF_TNPC], %l2
2860 ldx [%sp + SPOFF + CCFSZ + TF_PIL], %l3
2861 ldx [%sp + SPOFF + CCFSZ + TF_Y], %l4
2863 set VM_MIN_PROM_ADDRESS, %l5
2867 set VM_MAX_PROM_ADDRESS, %l5
2872 wrpr %g0, PSTATE_NORMAL, %pstate
2874 ldx [%sp + SPOFF + CCFSZ + TF_G6], %g6
2875 ldx [%sp + SPOFF + CCFSZ + TF_G7], %g7
2877 1: wrpr %g0, PSTATE_ALT, %pstate
2879 andn %l0, TSTATE_CWP_MASK, %g1
2891 wrpr %g1, %g4, %tstate
2895 #if KTR_COMPILE & KTR_TRAP
2896 CATR(KTR_TRAP, "tl1_ret: td=%#lx pil=%#lx ts=%#lx pc=%#lx sp=%#lx"
2897 , %g2, %g3, %g4, 7, 8, 9)
2898 ldx [PCPU(CURTHREAD)], %g3
2899 stx %g3, [%g2 + KTR_PARM1]
2901 stx %g3, [%g2 + KTR_PARM2]
2903 stx %g3, [%g2 + KTR_PARM3]
2905 stx %g3, [%g2 + KTR_PARM4]
2906 stx %sp, [%g2 + KTR_PARM5]
2914 * void tl1_intr(u_int level, u_int mask)
2924 #if KTR_COMPILE & KTR_INTR
2926 "tl1_intr: td=%p level=%#x pil=%#lx pc=%#lx sp=%#lx"
2927 , %g1, %g2, %g3, 7, 8, 9)
2928 ldx [PCPU(CURTHREAD)], %g2
2929 stx %g2, [%g1 + KTR_PARM1]
2930 stx %o0, [%g1 + KTR_PARM2]
2931 stx %l3, [%g1 + KTR_PARM3]
2932 stx %l1, [%g1 + KTR_PARM4]
2933 stx %i6, [%g1 + KTR_PARM5]
2938 wr %o1, 0, %clear_softint
2942 and %l5, WSTATE_OTHER_MASK, %l5
2943 wrpr %l5, WSTATE_KERNEL, %wstate
2945 stx %l0, [%sp + SPOFF + CCFSZ + TF_TSTATE]
2946 stx %l1, [%sp + SPOFF + CCFSZ + TF_TPC]
2947 stx %l2, [%sp + SPOFF + CCFSZ + TF_TNPC]
2948 stx %l3, [%sp + SPOFF + CCFSZ + TF_PIL]
2949 stx %l4, [%sp + SPOFF + CCFSZ + TF_Y]
2952 mov T_INTERRUPT | T_KERNEL, %o1
2954 stx %o0, [%sp + SPOFF + CCFSZ + TF_LEVEL]
2955 stx %o1, [%sp + SPOFF + CCFSZ + TF_TYPE]
2957 stx %i6, [%sp + SPOFF + CCFSZ + TF_O6]
2958 stx %i7, [%sp + SPOFF + CCFSZ + TF_O7]
2962 wrpr %g0, PSTATE_NORMAL, %pstate
2964 stx %g1, [%sp + SPOFF + CCFSZ + TF_G1]
2965 stx %g2, [%sp + SPOFF + CCFSZ + TF_G2]
2966 stx %g3, [%sp + SPOFF + CCFSZ + TF_G3]
2967 stx %g4, [%sp + SPOFF + CCFSZ + TF_G4]
2968 stx %g5, [%sp + SPOFF + CCFSZ + TF_G5]
2972 wrpr %g0, PSTATE_KERNEL, %pstate
2974 SET(intr_handlers, %l5, %l4)
2975 sllx %l7, IH_SHIFT, %l5
2976 ldx [%l4 + %l5], %l5
2977 KASSERT(%l5, "tl1_intr: ih null")
2979 add %sp, CCFSZ + SPOFF, %o0
2981 /* %l7 contains PIL */
2982 SET(intrcnt, %l5, %l4)
2983 prefetcha [%l4] ASI_N, 1
2984 SET(pil_countp, %l5, %l6)
2986 lduh [%l5 + %l6], %l5
2991 call counter_intr_inc
2994 ldx [%sp + SPOFF + CCFSZ + TF_Y], %l4
2996 ldx [%sp + SPOFF + CCFSZ + TF_G1], %g1
2997 ldx [%sp + SPOFF + CCFSZ + TF_G2], %g2
2998 ldx [%sp + SPOFF + CCFSZ + TF_G3], %g3
2999 ldx [%sp + SPOFF + CCFSZ + TF_G4], %g4
3000 ldx [%sp + SPOFF + CCFSZ + TF_G5], %g5
3002 wrpr %g0, PSTATE_ALT, %pstate
3004 andn %l0, TSTATE_CWP_MASK, %g1
3015 wrpr %g1, %g4, %tstate
3019 #if KTR_COMPILE & KTR_INTR
3020 CATR(KTR_INTR, "tl1_intr: td=%#x pil=%#lx ts=%#lx pc=%#lx sp=%#lx"
3021 , %g2, %g3, %g4, 7, 8, 9)
3022 ldx [PCPU(CURTHREAD)], %g3
3023 stx %g3, [%g2 + KTR_PARM1]
3025 stx %g3, [%g2 + KTR_PARM2]
3027 stx %g3, [%g2 + KTR_PARM3]
3029 stx %g3, [%g2 + KTR_PARM4]
3030 stx %sp, [%g2 + KTR_PARM5]
3042 * Freshly forked processes come here when switched to for the first time.
3043 * The arguments to fork_exit() have been setup in the locals, we must move
3046 ENTRY(fork_trampoline)
3047 #if KTR_COMPILE & KTR_PROC
3048 CATR(KTR_PROC, "fork_trampoline: td=%p (%s) cwp=%#lx"
3049 , %g1, %g2, %g3, 7, 8, 9)
3050 ldx [PCPU(CURTHREAD)], %g2
3051 stx %g2, [%g1 + KTR_PARM1]
3052 ldx [%g2 + TD_PROC], %g2
3053 add %g2, P_COMM, %g2
3054 stx %g2, [%g1 + KTR_PARM2]
3056 stx %g2, [%g1 + KTR_PARM3]
3065 END(fork_trampoline)