2 * Copyright (c) 1991 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 4. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * Copyright (c) 2001 Jake Burkholder.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
57 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91
58 * form: src/sys/i386/isa/intr_machdep.c,v 1.57 2001/07/20
61 #include <sys/cdefs.h>
62 __FBSDID("$FreeBSD$");
64 #include <sys/param.h>
65 #include <sys/systm.h>
67 #include <sys/errno.h>
68 #include <sys/interrupt.h>
69 #include <sys/kernel.h>
71 #include <sys/mutex.h>
77 #include <machine/frame.h>
78 #include <machine/intr_machdep.h>
80 #define MAX_STRAY_LOG 5
82 CTASSERT((1 << IV_SHIFT) == sizeof(struct intr_vector));
84 ih_func_t *intr_handlers[PIL_MAX];
85 uint16_t pil_countp[PIL_MAX];
87 struct intr_vector intr_vectors[IV_MAX];
88 uint16_t intr_countp[IV_MAX];
89 static u_long intr_stray_count[IV_MAX];
91 static const char *pil_names[] = {
94 "ithrd", /* PIL_ITHREAD */
95 "rndzvs", /* PIL_RENDEZVOUS */
97 "stop", /* PIL_STOP */
98 "preempt", /* PIL_PREEMPT */
99 "stray", "stray", "stray", "stray", "stray", "stray",
100 "fast", /* PIL_FAST */
101 "tick", /* PIL_TICK */
104 /* protect the intr_vectors table */
105 static struct sx intr_table_lock;
106 /* protect intrcnt_index */
107 static struct mtx intrcnt_lock;
110 static int assign_cpu;
112 static void intr_assign_next_cpu(struct intr_vector *iv);
113 static void intr_shuffle_irqs(void *arg __unused);
116 static int intr_assign_cpu(void *arg, u_char cpu);
117 static void intr_execute_handlers(void *);
118 static void intr_stray_level(struct trapframe *);
119 static void intr_stray_vector(void *);
120 static int intrcnt_setname(const char *, int);
121 static void intrcnt_updatename(int, const char *, int);
124 intrcnt_updatename(int vec, const char *name, int ispil)
126 static int intrcnt_index, stray_pil_index, stray_vec_index;
129 mtx_lock_spin(&intrcnt_lock);
130 if (intrnames[0] == '\0') {
133 printf("initalizing intr_countp\n");
134 intrcnt_setname("???", intrcnt_index++);
136 stray_vec_index = intrcnt_index++;
137 intrcnt_setname("stray", stray_vec_index);
138 for (name_index = 0; name_index < IV_MAX; name_index++)
139 intr_countp[name_index] = stray_vec_index;
141 stray_pil_index = intrcnt_index++;
142 intrcnt_setname("pil", stray_pil_index);
143 for (name_index = 0; name_index < PIL_MAX; name_index++)
144 pil_countp[name_index] = stray_pil_index;
150 if (!ispil && intr_countp[vec] != stray_vec_index)
151 name_index = intr_countp[vec];
152 else if (ispil && pil_countp[vec] != stray_pil_index)
153 name_index = pil_countp[vec];
155 name_index = intrcnt_index++;
157 if (intrcnt_setname(name, name_index))
161 intr_countp[vec] = name_index;
163 pil_countp[vec] = name_index;
164 mtx_unlock_spin(&intrcnt_lock);
168 intrcnt_setname(const char *name, int index)
171 if (intrnames + (MAXCOMLEN + 1) * index >= eintrnames)
173 snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s",
179 intr_setup(int pri, ih_func_t *ihf, int vec, iv_func_t *ivf, void *iva)
181 char pilname[MAXCOMLEN + 1];
186 intr_vectors[vec].iv_func = ivf;
187 intr_vectors[vec].iv_arg = iva;
188 intr_vectors[vec].iv_pri = pri;
189 intr_vectors[vec].iv_vec = vec;
191 intr_handlers[pri] = ihf;
193 snprintf(pilname, MAXCOMLEN + 1, "pil%d: %s", pri, pil_names[pri]);
194 intrcnt_updatename(pri, pilname, 1);
198 intr_stray_level(struct trapframe *tf)
201 printf("stray level interrupt %ld\n", tf->tf_level);
205 intr_stray_vector(void *cookie)
207 struct intr_vector *iv;
210 if (intr_stray_count[iv->iv_vec] < MAX_STRAY_LOG) {
211 printf("stray vector interrupt %d\n", iv->iv_vec);
212 intr_stray_count[iv->iv_vec]++;
213 if (intr_stray_count[iv->iv_vec] >= MAX_STRAY_LOG)
214 printf("got %d stray interrupt %d's: not logging "
215 "anymore\n", MAX_STRAY_LOG, iv->iv_vec);
224 /* Mark all interrupts as being stray. */
225 for (i = 0; i < PIL_MAX; i++)
226 intr_handlers[i] = intr_stray_level;
227 for (i = 0; i < IV_MAX; i++) {
228 intr_vectors[i].iv_func = intr_stray_vector;
229 intr_vectors[i].iv_arg = &intr_vectors[i];
230 intr_vectors[i].iv_pri = PIL_LOW;
231 intr_vectors[i].iv_vec = i;
232 intr_vectors[i].iv_refcnt = 0;
234 intr_handlers[PIL_LOW] = intr_fast;
241 sx_init(&intr_table_lock, "intr sources");
242 mtx_init(&intrcnt_lock, "intrcnt", NULL, MTX_SPIN);
246 intr_assign_cpu(void *arg, u_char cpu)
250 struct intr_vector *iv;
253 * Don't do anything during early boot. We will pick up the
254 * assignment once the APs are started.
256 if (assign_cpu && cpu != NOCPU) {
261 sx_xlock(&intr_table_lock);
262 iv->iv_mid = pc->pc_mid;
263 iv->iv_ic->ic_assign(iv);
264 sx_xunlock(&intr_table_lock);
273 intr_execute_handlers(void *cookie)
275 struct intr_vector *iv;
278 if (iv->iv_ic == NULL || intr_event_handle(iv->iv_event, NULL) != 0)
279 intr_stray_vector(iv);
283 intr_controller_register(int vec, const struct intr_controller *ic,
286 struct intr_event *ie;
287 struct intr_vector *iv;
290 if (vec < 0 || vec >= IV_MAX)
292 sx_xlock(&intr_table_lock);
293 iv = &intr_vectors[vec];
295 sx_xunlock(&intr_table_lock);
298 error = intr_event_create(&ie, iv, 0, vec, NULL, ic->ic_clear,
299 ic->ic_clear, intr_assign_cpu, "vec%d:", vec);
302 sx_xlock(&intr_table_lock);
303 if (iv->iv_event != NULL) {
304 sx_xunlock(&intr_table_lock);
305 intr_event_destroy(ie);
309 iv->iv_icarg = icarg;
311 iv->iv_mid = PCPU_GET(mid);
312 sx_xunlock(&intr_table_lock);
317 inthand_add(const char *name, int vec, driver_filter_t *filt,
318 driver_intr_t *handler, void *arg, int flags, void **cookiep)
320 const struct intr_controller *ic;
321 struct intr_event *ie;
322 struct intr_handler *ih;
323 struct intr_vector *iv;
326 if (vec < 0 || vec >= IV_MAX)
328 sx_xlock(&intr_table_lock);
329 iv = &intr_vectors[vec];
332 sx_xunlock(&intr_table_lock);
333 if (ic == NULL || ie == NULL)
335 error = intr_event_add_handler(ie, name, filt, handler, arg,
336 intr_priority(flags), flags, cookiep);
339 sx_xlock(&intr_table_lock);
340 /* Disable the interrupt while we fiddle with it. */
343 if (iv->iv_refcnt == 1)
344 intr_setup(filt != NULL ? PIL_FAST : PIL_ITHREAD, intr_fast,
345 vec, intr_execute_handlers, iv);
346 else if (filt != NULL) {
348 * Check if we need to upgrade from PIL_ITHREAD to PIL_FAST.
349 * Given that apart from the on-board SCCs and UARTs shared
350 * interrupts are rather uncommon on sparc64 this sould be
351 * pretty rare in practice.
354 TAILQ_FOREACH(ih, &ie->ie_handlers, ih_next) {
355 if (ih->ih_filter != NULL && ih->ih_filter != filt) {
361 intr_setup(PIL_FAST, intr_fast, vec,
362 intr_execute_handlers, iv);
364 intr_stray_count[vec] = 0;
365 intrcnt_updatename(vec, ie->ie_fullname, 0);
368 intr_assign_next_cpu(iv);
371 /* Ensure the interrupt is cleared, it might have triggered before. */
373 sx_xunlock(&intr_table_lock);
378 inthand_remove(int vec, void *cookie)
380 struct intr_vector *iv;
383 if (vec < 0 || vec >= IV_MAX)
385 error = intr_event_remove_handler(cookie);
388 * XXX: maybe this should be done regardless of whether
389 * intr_event_remove_handler() succeeded?
391 sx_xlock(&intr_table_lock);
392 iv = &intr_vectors[vec];
394 if (iv->iv_refcnt == 0) {
396 * Don't disable the interrupt for now, so that
397 * stray interrupts get detected...
399 intr_setup(PIL_LOW, intr_fast, vec,
400 intr_stray_vector, iv);
402 sx_xunlock(&intr_table_lock);
409 * Support for balancing interrupt sources across CPUs. For now we just
410 * allocate CPUs round-robin.
413 /* The BSP is always a valid target. */
414 static cpumask_t intr_cpus = (1 << 0);
415 static int current_cpu;
418 intr_assign_next_cpu(struct intr_vector *iv)
422 sx_assert(&intr_table_lock, SA_XLOCKED);
425 * Assign this source to a CPU in a round-robin fashion.
427 pc = pcpu_find(current_cpu);
430 iv->iv_mid = pc->pc_mid;
431 iv->iv_ic->ic_assign(iv);
434 if (current_cpu > mp_maxid)
436 } while (!(intr_cpus & (1 << current_cpu)));
439 /* Attempt to bind the specified IRQ to the specified CPU. */
441 intr_bind(int vec, u_char cpu)
443 struct intr_vector *iv;
445 if (vec < 0 || vec >= IV_MAX)
447 iv = &intr_vectors[vec];
450 return (intr_event_bind(iv->iv_event, cpu));
454 * Add a CPU to our mask of valid CPUs that can be destinations of
458 intr_add_cpu(u_int cpu)
462 panic("%s: Invalid CPU ID", __func__);
464 printf("INTR: Adding CPU %d as a target\n", cpu);
466 intr_cpus |= (1 << cpu);
470 * Distribute all the interrupt sources among the available CPUs once the
471 * APs have been launched.
474 intr_shuffle_irqs(void *arg __unused)
477 struct intr_vector *iv;
480 /* Don't bother on UP. */
484 sx_xlock(&intr_table_lock);
486 for (i = 0; i < IV_MAX; i++) {
487 iv = &intr_vectors[i];
488 if (iv != NULL && iv->iv_refcnt > 0) {
490 * If this event is already bound to a CPU,
491 * then assign the source to that CPU instead
492 * of picking one via round-robin.
494 if (iv->iv_event->ie_cpu != NOCPU &&
495 (pc = pcpu_find(iv->iv_event->ie_cpu)) != NULL) {
496 iv->iv_mid = pc->pc_mid;
497 iv->iv_ic->ic_assign(iv);
499 intr_assign_next_cpu(iv);
502 sx_xunlock(&intr_table_lock);
504 SYSINIT(intr_shuffle_irqs, SI_SUB_SMP, SI_ORDER_SECOND, intr_shuffle_irqs,