2 * Copyright (c) 2002 Jake Burkholder.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <machine/asm.h>
28 __FBSDID("$FreeBSD$");
30 #include <machine/asi.h>
31 #include <machine/asmacros.h>
32 #include <machine/cache.h>
33 #include <machine/ktr.h>
34 #include <machine/pstate.h>
38 .register %g2, #ignore
39 .register %g3, #ignore
41 #define IPI_DONE(r1, r2, r3, r4, r5) \
42 lduw [PCPU(CPUID)], r2 ; \
46 sllx r5, PTR_SHIFT, r5 ; \
52 ATOMIC_CLEAR_LONG(r1, r2, r3, r4)
55 * Invalidate a physical page in the data cache. For UltraSPARC I and II.
57 ENTRY(tl_ipi_spitfire_dcache_page_inval)
58 #if KTR_COMPILE & KTR_SMP
59 CATR(KTR_SMP, "tl_ipi_spitfire_dcache_page_inval: pa=%#lx"
60 , %g1, %g2, %g3, 7, 8, 9)
61 ldx [%g5 + ICA_PA], %g2
62 stx %g2, [%g1 + KTR_PARM1]
66 ldx [%g5 + ICA_PA], %g6
67 srlx %g6, PAGE_SHIFT - DC_TAG_SHIFT, %g6
69 lduw [PCPU(CACHE) + DC_SIZE], %g3
70 lduw [PCPU(CACHE) + DC_LINESIZE], %g4
73 1: ldxa [%g2] ASI_DCACHE_TAG, %g1
74 srlx %g1, DC_VALID_SHIFT, %g3
75 andcc %g3, DC_VALID_MASK, %g0
78 sllx %g3, DC_TAG_SHIFT, %g3
83 stxa %g1, [%g2] ASI_DCACHE_TAG
89 IPI_DONE(%g5, %g1, %g2, %g3, %g4)
91 END(tl_ipi_spitfire_dcache_page_inval)
94 * Invalidate a physical page in the instruction cache. For UltraSPARC I and
97 ENTRY(tl_ipi_spitfire_icache_page_inval)
98 #if KTR_COMPILE & KTR_SMP
99 CATR(KTR_SMP, "tl_ipi_spitfire_icache_page_inval: pa=%#lx"
100 , %g1, %g2, %g3, 7, 8, 9)
101 ldx [%g5 + ICA_PA], %g2
102 stx %g2, [%g1 + KTR_PARM1]
106 ldx [%g5 + ICA_PA], %g6
107 srlx %g6, PAGE_SHIFT - IC_TAG_SHIFT, %g6
109 lduw [PCPU(CACHE) + IC_SIZE], %g3
110 lduw [PCPU(CACHE) + IC_LINESIZE], %g4
113 1: ldda [%g2] ASI_ICACHE_TAG, %g0 /*, %g1 */
114 srlx %g1, IC_VALID_SHIFT, %g3
115 andcc %g3, IC_VALID_MASK, %g0
118 sllx %g3, IC_TAG_SHIFT, %g3
123 stxa %g1, [%g2] ASI_ICACHE_TAG
129 IPI_DONE(%g5, %g1, %g2, %g3, %g4)
131 END(tl_ipi_spitfire_icache_page_inval)
134 * Invalidate a physical page in the data cache. For UltraSPARC III.
136 ENTRY(tl_ipi_cheetah_dcache_page_inval)
137 #if KTR_COMPILE & KTR_SMP
138 CATR(KTR_SMP, "tl_ipi_cheetah_dcache_page_inval: pa=%#lx"
139 , %g1, %g2, %g3, 7, 8, 9)
140 ldx [%g5 + ICA_PA], %g2
141 stx %g2, [%g1 + KTR_PARM1]
145 ldx [%g5 + ICA_PA], %g1
150 lduw [PCPU(CACHE) + DC_LINESIZE], %g2
152 1: stxa %g0, [%g1] ASI_DCACHE_INVALIDATE
160 IPI_DONE(%g5, %g1, %g2, %g3, %g4)
162 END(tl_ipi_cheetah_dcache_page_inval)
165 * Trigger a softint at the desired level.
168 #if KTR_COMPILE & KTR_SMP
169 CATR(KTR_SMP, "tl_ipi_level: cpuid=%d mid=%d d1=%#lx d2=%#lx"
170 , %g1, %g2, %g3, 7, 8, 9)
171 lduw [PCPU(CPUID)], %g2
172 stx %g2, [%g1 + KTR_PARM1]
173 lduw [PCPU(MID)], %g2
174 stx %g2, [%g1 + KTR_PARM2]
175 stx %g4, [%g1 + KTR_PARM3]
176 stx %g5, [%g1 + KTR_PARM4]
182 wr %g1, 0, %set_softint
187 * Demap a page from the dtlb and/or itlb.
189 ENTRY(tl_ipi_tlb_page_demap)
190 #if KTR_COMPILE & KTR_SMP
191 CATR(KTR_SMP, "ipi_tlb_page_demap: pm=%p va=%#lx"
192 , %g1, %g2, %g3, 7, 8, 9)
193 ldx [%g5 + ITA_PMAP], %g2
194 stx %g2, [%g1 + KTR_PARM1]
195 ldx [%g5 + ITA_VA], %g2
196 stx %g2, [%g1 + KTR_PARM2]
200 ldx [%g5 + ITA_PMAP], %g1
202 SET(kernel_pmap_store, %g3, %g2)
203 mov TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE, %g3
206 movne %xcc, TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE, %g3
208 ldx [%g5 + ITA_VA], %g2
211 sethi %hi(KERNBASE), %g3
212 stxa %g0, [%g2] ASI_DMMU_DEMAP
213 stxa %g0, [%g2] ASI_IMMU_DEMAP
216 IPI_DONE(%g5, %g1, %g2, %g3, %g4)
218 END(tl_ipi_tlb_page_demap)
221 * Demap a range of pages from the dtlb and itlb.
223 ENTRY(tl_ipi_tlb_range_demap)
224 #if KTR_COMPILE & KTR_SMP
225 CATR(KTR_SMP, "ipi_tlb_range_demap: pm=%p start=%#lx end=%#lx"
226 , %g1, %g2, %g3, 7, 8, 9)
227 ldx [%g5 + ITA_PMAP], %g2
228 stx %g2, [%g1 + KTR_PARM1]
229 ldx [%g5 + ITA_START], %g2
230 stx %g2, [%g1 + KTR_PARM2]
231 ldx [%g5 + ITA_END], %g2
232 stx %g2, [%g1 + KTR_PARM3]
236 ldx [%g5 + ITA_PMAP], %g1
238 SET(kernel_pmap_store, %g3, %g2)
239 mov TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE, %g3
242 movne %xcc, TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE, %g3
244 ldx [%g5 + ITA_START], %g1
245 ldx [%g5 + ITA_END], %g2
247 sethi %hi(KERNBASE), %g6
249 stxa %g0, [%g4] ASI_DMMU_DEMAP
250 stxa %g0, [%g4] ASI_IMMU_DEMAP
257 sethi %hi(KERNBASE), %g6
259 IPI_DONE(%g5, %g1, %g2, %g3, %g4)
261 END(tl_ipi_tlb_range_demap)
264 * Demap the primary context from the dtlb and itlb.
266 ENTRY(tl_ipi_tlb_context_demap)
267 #if KTR_COMPILE & KTR_SMP
268 CATR(KTR_SMP, "tl_ipi_tlb_context_demap: pm=%p va=%#lx"
269 , %g1, %g2, %g3, 7, 8, 9)
270 ldx [%g5 + ITA_PMAP], %g2
271 stx %g2, [%g1 + KTR_PARM1]
272 ldx [%g5 + ITA_VA], %g2
273 stx %g2, [%g1 + KTR_PARM2]
277 mov TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, %g1
278 sethi %hi(KERNBASE), %g3
279 stxa %g0, [%g1] ASI_DMMU_DEMAP
280 stxa %g0, [%g1] ASI_IMMU_DEMAP
283 IPI_DONE(%g5, %g1, %g2, %g3, %g4)
285 END(tl_ipi_tlb_context_demap)
290 ENTRY(tl_ipi_stick_rd)
291 ldx [%g5 + IRA_VAL], %g1
295 IPI_DONE(%g5, %g1, %g2, %g3, %g4)
302 ENTRY(tl_ipi_tick_rd)
303 ldx [%g5 + IRA_VAL], %g1
307 IPI_DONE(%g5, %g1, %g2, %g3, %g4)