2 * Copyright (c) 2002 Jake Burkholder.
3 * Copyright (c) 2008 Marius Strobl <marius@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <machine/asm.h>
29 __FBSDID("$FreeBSD$");
31 #include <machine/asi.h>
32 #include <machine/asmacros.h>
33 #include <machine/intr_machdep.h>
34 #include <machine/ktr.h>
35 #include <machine/pstate.h>
36 #include <machine/smp.h>
37 #include <machine/ver.h>
41 .register %g2, #ignore
42 .register %g3, #ignore
47 * Initialize misc. state to known values: interrupts disabled, normal
48 * globals, windows flushed (cr = 0, cs = nwindows - 1), PIL_TICK and
49 * floating point disabled.
50 * Note that some firmware versions don't implement a clean window
51 * trap handler so we unfortunately can't clear the windows by setting
52 * %cleanwin to zero here.
54 1: wrpr %g0, PSTATE_NORMAL, %pstate
55 wrpr %g0, PIL_TICK, %pil
59 srlx %l7, VER_IMPL_SHIFT, %l7
60 sll %l7, VER_IMPL_SIZE, %l7
61 srl %l7, VER_IMPL_SIZE, %l7
62 cmp %l7, CPU_IMPL_ULTRASPARCIIIp
67 * Relocate the locked entry in it16 slot 0 (if existent)
68 * as part of working around Cheetah+ erratum 34.
71 setx TD_V | TD_L, %l1, %l0
73 * We read ASI_ITLB_DATA_ACCESS_REG twice in order to work
74 * around errata of USIII and beyond.
76 ldxa [%g0] ASI_ITLB_DATA_ACCESS_REG, %g0
77 ldxa [%g0] ASI_ITLB_DATA_ACCESS_REG, %l6
83 /* Flush the mapping of slot 0. */
84 ldxa [%g0] ASI_ITLB_TAG_READ_REG, %l5
85 srlx %l5, TAR_VPN_SHIFT, %l0
86 sllx %l0, TAR_VPN_SHIFT, %l0
87 or %l0, TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE, %l0
88 stxa %g0, [%l0] ASI_IMMU_DEMAP
89 /* The USIII-family ignores the address. */
93 * Search a replacement slot != 0 and enter the data and tag
94 * that formerly were in slot 0.
96 mov (1 << TLB_DAR_SLOT_SHIFT), %l4
99 * We read ASI_ITLB_DATA_ACCESS_REG twice in order to work
100 * around errata of USIII and beyond.
102 2: ldxa [%l4] ASI_ITLB_DATA_ACCESS_REG, %g0
103 ldxa [%l4] ASI_ITLB_DATA_ACCESS_REG, %l1
107 add %l4, (1 << TLB_DAR_SLOT_SHIFT), %l4
108 wr %g0, ASI_IMMU, %asi
109 stxa %l5, [%g0 + AA_IMMU_TAR] %asi
110 stxa %l6, [%l4] ASI_ITLB_DATA_ACCESS_REG
111 /* The USIII-family ignores the address. */
115 ldx [%l6 + (9f-3b)], %l1
116 add %l6, (11f-3b), %l2
121 ldx [%l2 + TTE_VPN], %l4
122 ldx [%l2 + TTE_DATA], %l5
123 srlx %l4, TV_SIZE_BITS, %l4
124 sllx %l4, PAGE_SHIFT_4M, %l4
125 wr %g0, ASI_DMMU, %asi
126 stxa %l4, [%g0 + AA_DMMU_TAR] %asi
127 stxa %l5, [%g0] ASI_DTLB_DATA_IN_REG
130 cmp %l7, CPU_IMPL_ULTRASPARCIIIp
132 wr %g0, ASI_IMMU, %asi
135 * Search an unused slot != 0 and explicitly enter the data
136 * and tag there in order to avoid Cheetah+ erratum 34.
138 mov (1 << TLB_DAR_SLOT_SHIFT), %l0
141 * We read ASI_ITLB_DATA_ACCESS_REG twice in order to work
142 * around errata of USIII and beyond.
144 5: ldxa [%l0] ASI_ITLB_DATA_ACCESS_REG, %g0
145 ldxa [%l0] ASI_ITLB_DATA_ACCESS_REG, %o1
149 add %l0, (1 << TLB_DAR_SLOT_SHIFT), %l0
150 sethi %hi(KERNBASE), %o0
151 stxa %l4, [%g0 + AA_IMMU_TAR] %asi
152 stxa %l5, [%l0] ASI_ITLB_DATA_ACCESS_REG
157 6: sethi %hi(KERNBASE), %l0
158 stxa %l4, [%g0 + AA_IMMU_TAR] %asi
159 stxa %l5, [%g0] ASI_ITLB_DATA_IN_REG
161 7: add %l2, 1 << TTE_SHIFT, %l2
165 8: ldx [%l6 + (10f-3b)], %l1
175 DATA(mp_tramp_code_len)
177 DATA(mp_tramp_tlb_slots)
183 * void mp_startup(void)
186 SET(cpu_start_args, %l1, %l0)
188 mov CPU_TICKSYNC, %l1
190 stw %l1, [%l0 + CSA_STATE]
192 1: ldx [%l0 + CSA_TICK], %l1
198 stx %l1, [%l0 + CSA_VER]
200 srlx %l1, VER_IMPL_SHIFT, %l1
201 sll %l1, VER_IMPL_SIZE, %l1
202 srl %l1, VER_IMPL_SIZE, %l1
203 cmp %l1, CPU_IMPL_SPARC64V
206 cmp %l1, CPU_IMPL_ULTRASPARCI
209 cmp %l1, CPU_IMPL_ULTRASPARCIII
212 2: mov CPU_STICKSYNC, %l2
214 stw %l2, [%l0 + CSA_STATE]
216 3: ldx [%l0 + CSA_STICK], %l2
225 * Inform the boot processor we have inited.
229 stw %l1, [%l0 + CSA_STATE]
232 * Wait till its our turn to bootstrap.
234 5: lduw [%l0 + CSA_MID], %l1
239 add %l0, CSA_TTES, %l1
243 * Map the per-CPU pages.
245 6: sllx %l2, TTE_SHIFT, %l3
248 ldx [%l3 + TTE_VPN], %l4
249 ldx [%l3 + TTE_DATA], %l5
251 wr %g0, ASI_DMMU, %asi
252 srlx %l4, TV_SIZE_BITS, %l4
253 sllx %l4, PAGE_SHIFT_8K, %l4
254 stxa %l4, [%g0 + AA_DMMU_TAR] %asi
255 stxa %l5, [%g0] ASI_DTLB_DATA_IN_REG
264 * Get onto our per-CPU panic stack, which precedes the struct pcpu
265 * in the per-CPU page.
267 ldx [%l0 + CSA_PCPU], %l1
268 set PCPU_PAGES * PAGE_SIZE - PC_SIZEOF, %l2
270 sub %l1, SPOFF + CCFSZ, %sp
272 #if KTR_COMPILE & KTR_SMP
274 "mp_startup: bootstrap cpuid=%d mid=%d pcpu=%#lx data=%#lx sp=%#lx"
275 , %g1, %g2, %g3, 7, 8, 9)
276 lduw [%l1 + PC_CPUID], %g2
277 stx %g2, [%g1 + KTR_PARM1]
278 lduw [%l1 + PC_MID], %g2
279 stx %g2, [%g1 + KTR_PARM2]
280 stx %l1, [%g1 + KTR_PARM3]
281 stx %sp, [%g1 + KTR_PARM5]
286 * And away we go. This doesn't return.
288 call cpu_mp_bootstrap