2 * SPDX-License-Identifier: BSD-3-Clause AND BSD-2-Clause-FreeBSD
4 * Copyright (c) 1997 Berkeley Software Design, Inc. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Berkeley Software Design Inc's name may not be used to endorse or
15 * promote products derived from this software without specific prior
18 * THIS SOFTWARE IS PROVIDED BY BERKELEY SOFTWARE DESIGN INC ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL BERKELEY SOFTWARE DESIGN INC BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from BSDI: locore.s,v 1.36.2.15 1999/08/23 22:34:41 cp Exp
33 * Copyright (c) 2002 Jake Burkholder.
34 * Copyright (c) 2007 - 2010 Marius Strobl <marius@FreeBSD.org>
35 * All rights reserved.
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * 2. Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in the
44 * documentation and/or other materials provided with the distribution.
46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
49 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
59 #include <sys/cdefs.h>
60 __FBSDID("$FreeBSD$");
62 #include <sys/param.h>
63 #include <sys/systm.h>
66 #include <sys/kernel.h>
68 #include <sys/mutex.h>
71 #include <sys/sched.h>
75 #include <vm/vm_param.h>
77 #include <vm/vm_kern.h>
78 #include <vm/vm_extern.h>
79 #include <vm/vm_map.h>
81 #include <dev/ofw/openfirm.h>
83 #include <machine/asi.h>
84 #include <machine/atomic.h>
85 #include <machine/bus.h>
86 #include <machine/cpu.h>
87 #include <machine/cpufunc.h>
88 #include <machine/md_var.h>
89 #include <machine/metadata.h>
90 #include <machine/ofw_machdep.h>
91 #include <machine/pcb.h>
92 #include <machine/smp.h>
93 #include <machine/tick.h>
94 #include <machine/tlb.h>
95 #include <machine/tsb.h>
96 #include <machine/tte.h>
97 #include <machine/ver.h>
99 #define SUNW_STARTCPU "SUNW,start-cpu"
100 #define SUNW_STOPSELF "SUNW,stop-self"
102 static ih_func_t cpu_ipi_ast;
103 static ih_func_t cpu_ipi_hardclock;
104 static ih_func_t cpu_ipi_preempt;
105 static ih_func_t cpu_ipi_stop;
108 * Argument area used to pass data to non-boot processors as they start up.
109 * This must be statically initialized with a known invalid CPU module ID,
110 * since the other processors will use it before the boot CPU enters the
113 struct cpu_start_args cpu_start_args = { 0, -1, -1, 0, 0, 0 };
114 struct ipi_cache_args ipi_cache_args;
115 struct ipi_rd_args ipi_rd_args;
116 struct ipi_tlb_args ipi_tlb_args;
117 struct pcb stoppcbs[MAXCPU];
121 cpu_ipi_selected_t *cpu_ipi_selected;
122 cpu_ipi_single_t *cpu_ipi_single;
124 static u_int cpuid_to_mid[MAXCPU];
125 static u_int cpuids = 1;
126 static volatile cpuset_t shutdown_cpus;
127 static char ipi_pbuf[CPUSETBUFSIZ];
128 static vm_offset_t mp_tramp;
130 static void ap_count(phandle_t node, u_int mid, u_int cpu_impl);
131 static void ap_start(phandle_t node, u_int mid, u_int cpu_impl);
132 static void cpu_mp_unleash(void *v);
133 static void foreach_ap(phandle_t node, void (*func)(phandle_t node,
134 u_int mid, u_int cpu_impl));
135 static void sun4u_startcpu(phandle_t cpu, void *func, u_long arg);
137 static cpu_ipi_selected_t cheetah_ipi_selected;
138 static cpu_ipi_single_t cheetah_ipi_single;
139 static cpu_ipi_selected_t jalapeno_ipi_selected;
140 static cpu_ipi_single_t jalapeno_ipi_single;
141 static cpu_ipi_selected_t spitfire_ipi_selected;
142 static cpu_ipi_single_t spitfire_ipi_single;
144 SYSINIT(cpu_mp_unleash, SI_SUB_SMP, SI_ORDER_FIRST, cpu_mp_unleash, NULL);
152 mp_tramp = (vm_offset_t)OF_claim(NULL, PAGE_SIZE, PAGE_SIZE);
153 if (mp_tramp == (vm_offset_t)-1)
154 panic("%s", __func__);
155 bcopy(mp_tramp_code, (void *)mp_tramp, mp_tramp_code_len);
156 *(vm_offset_t *)(mp_tramp + mp_tramp_tlb_slots) = kernel_tlb_slots;
157 *(vm_offset_t *)(mp_tramp + mp_tramp_func) = (vm_offset_t)mp_startup;
158 tp = (struct tte *)(mp_tramp + mp_tramp_code_len);
159 for (i = 0; i < kernel_tlb_slots; i++) {
160 tp[i].tte_vpn = TV_VPN(kernel_tlbs[i].te_va, TS_4M);
161 tp[i].tte_data = TD_V | TD_4M | TD_PA(kernel_tlbs[i].te_pa) |
162 TD_L | TD_CP | TD_CV | TD_P | TD_W;
164 for (i = 0; i < PAGE_SIZE; i += sizeof(vm_offset_t))
169 foreach_ap(phandle_t node, void (*func)(phandle_t node, u_int mid,
172 static char type[sizeof("cpu")];
174 uint32_t cpu_impl, portid;
176 /* There's no need to traverse the whole OFW tree twice. */
177 if (mp_maxid > 0 && cpuids > mp_maxid)
180 for (; node != 0; node = OF_peer(node)) {
181 child = OF_child(node);
183 foreach_ap(child, func);
185 if (OF_getprop(node, "device_type", type,
188 if (strcmp(type, "cpu") != 0)
190 if (OF_getprop(node, "implementation#", &cpu_impl,
191 sizeof(cpu_impl)) <= 0)
192 panic("%s: couldn't determine CPU "
193 "implementation", __func__);
194 if (OF_getprop(node, cpu_portid_prop(cpu_impl),
195 &portid, sizeof(portid)) <= 0)
196 panic("%s: couldn't determine CPU port ID",
198 if (portid == PCPU_GET(mid))
200 (*func)(node, portid, cpu_impl);
206 * Probe for other CPUs.
209 cpu_mp_setmaxid(void)
212 CPU_SETOF(curcpu, &all_cpus);
215 foreach_ap(OF_child(OF_peer(0)), ap_count);
216 mp_ncpus = MIN(mp_ncpus, MAXCPU);
217 mp_maxid = mp_ncpus - 1;
221 ap_count(phandle_t node __unused, u_int mid __unused, u_int cpu_impl __unused)
231 return (mp_maxid > 0);
238 return (smp_topo_none());
242 sun4u_startcpu(phandle_t cpu, void *func, u_long arg)
252 (cell_t)SUNW_STARTCPU,
257 args.func = (cell_t)func;
258 args.arg = (cell_t)arg;
263 * Fire up any non-boot processors.
268 u_int cpu_impl, isjbus;
270 mtx_init(&ipi_mtx, "ipi", NULL, MTX_SPIN);
273 cpu_impl = PCPU_GET(impl);
274 if (cpu_impl == CPU_IMPL_ULTRASPARCIIIi ||
275 cpu_impl == CPU_IMPL_ULTRASPARCIIIip) {
277 cpu_ipi_selected = jalapeno_ipi_selected;
278 cpu_ipi_single = jalapeno_ipi_single;
279 } else if (cpu_impl == CPU_IMPL_SPARC64V ||
280 cpu_impl >= CPU_IMPL_ULTRASPARCIII) {
281 cpu_ipi_selected = cheetah_ipi_selected;
282 cpu_ipi_single = cheetah_ipi_single;
284 cpu_ipi_selected = spitfire_ipi_selected;
285 cpu_ipi_single = spitfire_ipi_single;
288 intr_setup(PIL_AST, cpu_ipi_ast, -1, NULL, NULL);
289 intr_setup(PIL_RENDEZVOUS, (ih_func_t *)smp_rendezvous_action,
291 intr_setup(PIL_STOP, cpu_ipi_stop, -1, NULL, NULL);
292 intr_setup(PIL_PREEMPT, cpu_ipi_preempt, -1, NULL, NULL);
293 intr_setup(PIL_HARDCLOCK, cpu_ipi_hardclock, -1, NULL, NULL);
295 cpuid_to_mid[curcpu] = PCPU_GET(mid);
297 foreach_ap(OF_child(OF_peer(0)), ap_start);
298 KASSERT(!isjbus || mp_ncpus <= IDR_JALAPENO_MAX_BN_PAIRS,
299 ("%s: can only IPI a maximum of %d JBus-CPUs",
300 __func__, IDR_JALAPENO_MAX_BN_PAIRS));
304 ap_start(phandle_t node, u_int mid, u_int cpu_impl)
306 volatile struct cpu_start_args *csa;
313 if (cpuids > mp_maxid)
316 if (OF_getprop(node, "clock-frequency", &clock, sizeof(clock)) <= 0)
317 panic("%s: couldn't determine CPU frequency", __func__);
318 if (clock != PCPU_GET(clock))
319 tick_et_use_stick = 1;
321 csa = &cpu_start_args;
323 sun4u_startcpu(node, (void *)mp_tramp, 0);
325 while (csa->csa_state != CPU_TICKSYNC)
328 csa->csa_tick = rd(tick);
329 if (cpu_impl == CPU_IMPL_SPARC64V ||
330 cpu_impl >= CPU_IMPL_ULTRASPARCIII) {
331 while (csa->csa_state != CPU_STICKSYNC)
334 csa->csa_stick = rdstick();
336 while (csa->csa_state != CPU_INIT)
338 csa->csa_tick = csa->csa_stick = 0;
342 cpuid_to_mid[cpuid] = mid;
343 cpu_identify(csa->csa_ver, clock, cpuid);
345 va = kmem_malloc(kernel_arena, PCPU_PAGES * PAGE_SIZE,
347 pc = (struct pcpu *)(va + (PCPU_PAGES * PAGE_SIZE)) - 1;
348 pcpu_init(pc, cpuid, sizeof(*pc));
349 dpcpu_init((void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
350 M_WAITOK | M_ZERO), cpuid);
352 pc->pc_clock = clock;
353 pc->pc_impl = cpu_impl;
359 CPU_SET(cpuid, &all_cpus);
364 cpu_mp_announce(void)
370 cpu_mp_unleash(void *v __unused)
372 volatile struct cpu_start_args *csa;
381 ctx_min = TLB_CTX_USER_MIN;
382 ctx_inc = (TLB_CTX_USER_MAX - 1) / mp_ncpus;
383 csa = &cpu_start_args;
384 csa->csa_count = mp_ncpus;
385 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
386 pc->pc_tlb_ctx = ctx_min;
387 pc->pc_tlb_ctx_min = ctx_min;
388 pc->pc_tlb_ctx_max = ctx_min + ctx_inc;
391 if (pc->pc_cpuid == curcpu)
393 KASSERT(pc->pc_idlethread != NULL,
394 ("%s: idlethread", __func__));
395 pc->pc_curthread = pc->pc_idlethread;
396 pc->pc_curpcb = pc->pc_curthread->td_pcb;
397 for (i = 0; i < PCPU_PAGES; i++) {
398 va = pc->pc_addr + i * PAGE_SIZE;
399 pa = pmap_kextract(va);
401 panic("%s: pmap_kextract", __func__);
402 csa->csa_ttes[i].tte_vpn = TV_VPN(va, TS_8K);
403 csa->csa_ttes[i].tte_data = TD_V | TD_8K | TD_PA(pa) |
404 TD_L | TD_CP | TD_CV | TD_P | TD_W;
407 csa->csa_pcpu = pc->pc_addr;
408 csa->csa_mid = pc->pc_mid;
410 while (csa->csa_state != CPU_BOOTSTRAP)
420 cpu_mp_bootstrap(struct pcpu *pc)
422 volatile struct cpu_start_args *csa;
424 csa = &cpu_start_args;
426 /* Do CPU-specific initialization. */
427 if (pc->pc_impl >= CPU_IMPL_ULTRASPARCIII)
428 cheetah_init(pc->pc_impl);
429 else if (pc->pc_impl == CPU_IMPL_SPARC64V)
430 zeus_init(pc->pc_impl);
433 * Enable the caches. Note that his may include applying workarounds.
435 cache_enable(pc->pc_impl);
438 * Clear (S)TICK timer(s) (including NPT) and ensure they are stopped.
440 tick_clear(pc->pc_impl);
441 tick_stop(pc->pc_impl);
443 /* Set the kernel context. */
446 /* Lock the kernel TSB in the TLB if necessary. */
447 if (tsb_kernel_ldd_phys == 0)
451 * Flush all non-locked TLB entries possibly left over by the
454 tlb_flush_nonlocked();
458 * Note that the PIL we be lowered indirectly via sched_throw(NULL)
459 * when fake spinlock held by the idle thread eventually is released.
461 wrpr(pstate, 0, PSTATE_KERNEL);
464 KASSERT(curthread != NULL, ("%s: curthread", __func__));
465 printf("SMP: AP CPU #%d Launched!\n", curcpu);
469 csa->csa_state = CPU_BOOTSTRAP;
470 while (csa->csa_count != 0)
473 if (smp_cpus == mp_ncpus)
474 atomic_store_rel_int(&smp_started, 1);
476 /* Start per-CPU event timers. */
479 /* Ok, now enter the scheduler. */
484 cpu_mp_shutdown(void)
490 shutdown_cpus = all_cpus;
491 CPU_CLR(PCPU_GET(cpuid), &shutdown_cpus);
492 cpus = shutdown_cpus;
494 /* XXX: Stop all the CPUs which aren't already. */
495 if (CPU_CMP(&stopped_cpus, &cpus)) {
497 /* cpus is just a flat "on" mask without curcpu. */
498 CPU_NAND(&cpus, &stopped_cpus);
502 while (!CPU_EMPTY(&shutdown_cpus)) {
504 printf("timeout shutting down CPUs.\n");
512 cpu_ipi_ast(struct trapframe *tf __unused)
518 cpu_ipi_stop(struct trapframe *tf __unused)
522 CTR2(KTR_SMP, "%s: stopped %d", __func__, curcpu);
524 savectx(&stoppcbs[curcpu]);
525 cpuid = PCPU_GET(cpuid);
526 CPU_SET_ATOMIC(cpuid, &stopped_cpus);
527 while (!CPU_ISSET(cpuid, &started_cpus)) {
528 if (CPU_ISSET(cpuid, &shutdown_cpus)) {
529 CPU_CLR_ATOMIC(cpuid, &shutdown_cpus);
530 (void)intr_disable();
535 CPU_CLR_ATOMIC(cpuid, &started_cpus);
536 CPU_CLR_ATOMIC(cpuid, &stopped_cpus);
538 CTR2(KTR_SMP, "%s: restarted %d", __func__, curcpu);
542 cpu_ipi_preempt(struct trapframe *tf __unused)
545 sched_preempt(curthread);
549 cpu_ipi_hardclock(struct trapframe *tf)
551 struct trapframe *oldframe;
556 td->td_intr_nesting_level++;
557 oldframe = td->td_intr_frame;
558 td->td_intr_frame = tf;
560 td->td_intr_frame = oldframe;
561 td->td_intr_nesting_level--;
566 spitfire_ipi_selected(cpuset_t cpus, u_long d0, u_long d1, u_long d2)
570 while ((cpu = CPU_FFS(&cpus)) != 0) {
573 spitfire_ipi_single(cpu, d0, d1, d2);
578 spitfire_ipi_single(u_int cpu, u_long d0, u_long d1, u_long d2)
585 mtx_assert(&ipi_mtx, MA_OWNED);
586 KASSERT(cpu != curcpu, ("%s: CPU can't IPI itself", __func__));
587 KASSERT((ldxa(0, ASI_INTR_DISPATCH_STATUS) & IDR_BUSY) == 0,
588 ("%s: outstanding dispatch", __func__));
590 mid = cpuid_to_mid[cpu];
591 for (i = 0; i < IPI_RETRIES; i++) {
593 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0);
594 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1);
595 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2);
597 stxa(AA_INTR_SEND | (mid << IDC_ITID_SHIFT),
600 * Workaround for SpitFire erratum #54; do a dummy read
601 * from a SDB internal register before the MEMBAR #Sync
602 * for the write to ASI_SDB_INTR_W (requiring another
603 * MEMBAR #Sync in order to make sure the write has
604 * occurred before the load).
607 (void)ldxa(AA_SDB_CNTL_HIGH, ASI_SDB_CONTROL_R);
609 while (((ids = ldxa(0, ASI_INTR_DISPATCH_STATUS)) &
613 if ((ids & (IDR_BUSY | IDR_NACK)) == 0)
616 if (kdb_active != 0 || panicstr != NULL)
617 printf("%s: couldn't send IPI to module 0x%u\n",
620 panic("%s: couldn't send IPI to module 0x%u",
625 cheetah_ipi_single(u_int cpu, u_long d0, u_long d1, u_long d2)
632 mtx_assert(&ipi_mtx, MA_OWNED);
633 KASSERT(cpu != curcpu, ("%s: CPU can't IPI itself", __func__));
634 KASSERT((ldxa(0, ASI_INTR_DISPATCH_STATUS) &
635 IDR_CHEETAH_ALL_BUSY) == 0,
636 ("%s: outstanding dispatch", __func__));
638 mid = cpuid_to_mid[cpu];
639 for (i = 0; i < IPI_RETRIES; i++) {
641 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0);
642 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1);
643 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2);
645 stxa(AA_INTR_SEND | (mid << IDC_ITID_SHIFT),
648 while (((ids = ldxa(0, ASI_INTR_DISPATCH_STATUS)) &
652 if ((ids & (IDR_BUSY | IDR_NACK)) == 0)
655 if (kdb_active != 0 || panicstr != NULL)
656 printf("%s: couldn't send IPI to module 0x%u\n",
659 panic("%s: couldn't send IPI to module 0x%u",
664 cheetah_ipi_selected(cpuset_t cpus, u_long d0, u_long d1, u_long d2)
672 mtx_assert(&ipi_mtx, MA_OWNED);
673 KASSERT(!CPU_EMPTY(&cpus), ("%s: no CPUs to IPI", __func__));
674 KASSERT(!CPU_ISSET(curcpu, &cpus), ("%s: CPU can't IPI itself",
676 KASSERT((ldxa(0, ASI_INTR_DISPATCH_STATUS) &
677 IDR_CHEETAH_ALL_BUSY) == 0,
678 ("%s: outstanding dispatch", __func__));
681 for (i = 0; i < IPI_RETRIES * smp_cpus; i++) {
683 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0);
684 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1);
685 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2);
688 for (cpu = 0; cpu < smp_cpus; cpu++) {
689 if (CPU_ISSET(cpu, &cpus)) {
690 stxa(AA_INTR_SEND | (cpuid_to_mid[cpu] <<
691 IDC_ITID_SHIFT) | bnp << IDC_BN_SHIFT,
695 if (bnp == IDR_CHEETAH_MAX_BN_PAIRS)
699 while (((ids = ldxa(0, ASI_INTR_DISPATCH_STATUS)) &
700 IDR_CHEETAH_ALL_BUSY) != 0)
704 for (cpu = 0; cpu < smp_cpus; cpu++) {
705 if (CPU_ISSET(cpu, &cpus)) {
706 if ((ids & (IDR_NACK << (2 * bnp))) == 0)
711 if (CPU_EMPTY(&cpus))
714 if (kdb_active != 0 || panicstr != NULL)
715 printf("%s: couldn't send IPI (cpus=%s ids=0x%lu)\n",
716 __func__, cpusetobj_strprint(ipi_pbuf, &cpus), ids);
718 panic("%s: couldn't send IPI (cpus=%s ids=0x%lu)",
719 __func__, cpusetobj_strprint(ipi_pbuf, &cpus), ids);
723 jalapeno_ipi_single(u_int cpu, u_long d0, u_long d1, u_long d2)
727 u_int busy, busynack, mid;
730 mtx_assert(&ipi_mtx, MA_OWNED);
731 KASSERT(cpu != curcpu, ("%s: CPU can't IPI itself", __func__));
732 KASSERT((ldxa(0, ASI_INTR_DISPATCH_STATUS) &
733 IDR_CHEETAH_ALL_BUSY) == 0,
734 ("%s: outstanding dispatch", __func__));
736 mid = cpuid_to_mid[cpu];
737 busy = IDR_BUSY << (2 * mid);
738 busynack = (IDR_BUSY | IDR_NACK) << (2 * mid);
739 for (i = 0; i < IPI_RETRIES; i++) {
741 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0);
742 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1);
743 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2);
745 stxa(AA_INTR_SEND | (mid << IDC_ITID_SHIFT),
748 while (((ids = ldxa(0, ASI_INTR_DISPATCH_STATUS)) &
752 if ((ids & busynack) == 0)
755 if (kdb_active != 0 || panicstr != NULL)
756 printf("%s: couldn't send IPI to module 0x%u\n",
759 panic("%s: couldn't send IPI to module 0x%u",
764 jalapeno_ipi_selected(cpuset_t cpus, u_long d0, u_long d1, u_long d2)
771 mtx_assert(&ipi_mtx, MA_OWNED);
772 KASSERT(!CPU_EMPTY(&cpus), ("%s: no CPUs to IPI", __func__));
773 KASSERT(!CPU_ISSET(curcpu, &cpus), ("%s: CPU can't IPI itself",
775 KASSERT((ldxa(0, ASI_INTR_DISPATCH_STATUS) &
776 IDR_CHEETAH_ALL_BUSY) == 0,
777 ("%s: outstanding dispatch", __func__));
780 for (i = 0; i < IPI_RETRIES * smp_cpus; i++) {
782 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0);
783 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1);
784 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2);
786 for (cpu = 0; cpu < smp_cpus; cpu++) {
787 if (CPU_ISSET(cpu, &cpus)) {
788 stxa(AA_INTR_SEND | (cpuid_to_mid[cpu] <<
789 IDC_ITID_SHIFT), ASI_SDB_INTR_W, 0);
793 while (((ids = ldxa(0, ASI_INTR_DISPATCH_STATUS)) &
794 IDR_CHEETAH_ALL_BUSY) != 0)
798 (IDR_CHEETAH_ALL_BUSY | IDR_CHEETAH_ALL_NACK)) == 0)
800 for (cpu = 0; cpu < smp_cpus; cpu++)
801 if (CPU_ISSET(cpu, &cpus))
802 if ((ids & (IDR_NACK <<
803 (2 * cpuid_to_mid[cpu]))) == 0)
806 if (kdb_active != 0 || panicstr != NULL)
807 printf("%s: couldn't send IPI (cpus=%s ids=0x%lu)\n",
808 __func__, cpusetobj_strprint(ipi_pbuf, &cpus), ids);
810 panic("%s: couldn't send IPI (cpus=%s ids=0x%lu)",
811 __func__, cpusetobj_strprint(ipi_pbuf, &cpus), ids);