2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
46 * Manages physical address maps.
48 * Since the information managed by this module is also stored by the
49 * logical address mapping module, this module may throw away valid virtual
50 * to physical mappings at almost any time. However, invalidations of
51 * mappings must be done as requested.
53 * In order to cope with hardware architectures which make virtual to
54 * physical map invalidates expensive, this module may delay invalidate
55 * reduced protection operations until such time as they are actually
56 * necessary. This module is given full information as to which processors
57 * are currently using which maps, and to when physical maps must be made
61 #include "opt_kstack_pages.h"
64 #include <sys/param.h>
65 #include <sys/kernel.h>
68 #include <sys/msgbuf.h>
69 #include <sys/mutex.h>
71 #include <sys/rwlock.h>
73 #include <sys/sysctl.h>
74 #include <sys/systm.h>
75 #include <sys/vmmeter.h>
77 #include <dev/ofw/openfirm.h>
80 #include <vm/vm_param.h>
81 #include <vm/vm_kern.h>
82 #include <vm/vm_page.h>
83 #include <vm/vm_map.h>
84 #include <vm/vm_object.h>
85 #include <vm/vm_extern.h>
86 #include <vm/vm_pageout.h>
87 #include <vm/vm_pager.h>
88 #include <vm/vm_phys.h>
90 #include <machine/cache.h>
91 #include <machine/frame.h>
92 #include <machine/instr.h>
93 #include <machine/md_var.h>
94 #include <machine/metadata.h>
95 #include <machine/ofw_mem.h>
96 #include <machine/smp.h>
97 #include <machine/tlb.h>
98 #include <machine/tte.h>
99 #include <machine/tsb.h>
100 #include <machine/ver.h>
103 * Map of physical memory reagions
105 static struct ofw_mem_region mra[VM_PHYSSEG_MAX];
106 struct ofw_mem_region sparc64_memreg[VM_PHYSSEG_MAX];
108 static struct ofw_map translations[VM_PHYSSEG_MAX];
109 static int translations_size;
111 static vm_offset_t pmap_idle_map;
112 static vm_offset_t pmap_temp_map_1;
113 static vm_offset_t pmap_temp_map_2;
116 * First and last available kernel virtual addresses
118 vm_offset_t virtual_avail;
119 vm_offset_t virtual_end;
120 vm_offset_t kernel_vm_end;
122 vm_offset_t vm_max_kernel_address;
127 struct pmap kernel_pmap_store;
129 struct rwlock_padalign tte_list_global_lock;
132 * Allocate physical memory for use in pmap_bootstrap.
134 static vm_paddr_t pmap_bootstrap_alloc(vm_size_t size, uint32_t colors);
136 static void pmap_bootstrap_set_tte(struct tte *tp, u_long vpn, u_long data);
137 static void pmap_cache_remove(vm_page_t m, vm_offset_t va);
138 static int pmap_protect_tte(struct pmap *pm1, struct pmap *pm2,
139 struct tte *tp, vm_offset_t va);
140 static int pmap_unwire_tte(pmap_t pm, pmap_t pm2, struct tte *tp,
142 static void pmap_init_qpages(void);
145 * Map the given physical page at the specified virtual address in the
146 * target pmap with the protection requested. If specified the page
147 * will be wired down.
149 * The page queues and pmap must be locked.
151 static int pmap_enter_locked(pmap_t pm, vm_offset_t va, vm_page_t m,
152 vm_prot_t prot, u_int flags, int8_t psind);
154 extern int tl1_dmmu_miss_direct_patch_tsb_phys_1[];
155 extern int tl1_dmmu_miss_direct_patch_tsb_phys_end_1[];
156 extern int tl1_dmmu_miss_patch_asi_1[];
157 extern int tl1_dmmu_miss_patch_quad_ldd_1[];
158 extern int tl1_dmmu_miss_patch_tsb_1[];
159 extern int tl1_dmmu_miss_patch_tsb_2[];
160 extern int tl1_dmmu_miss_patch_tsb_mask_1[];
161 extern int tl1_dmmu_miss_patch_tsb_mask_2[];
162 extern int tl1_dmmu_prot_patch_asi_1[];
163 extern int tl1_dmmu_prot_patch_quad_ldd_1[];
164 extern int tl1_dmmu_prot_patch_tsb_1[];
165 extern int tl1_dmmu_prot_patch_tsb_2[];
166 extern int tl1_dmmu_prot_patch_tsb_mask_1[];
167 extern int tl1_dmmu_prot_patch_tsb_mask_2[];
168 extern int tl1_immu_miss_patch_asi_1[];
169 extern int tl1_immu_miss_patch_quad_ldd_1[];
170 extern int tl1_immu_miss_patch_tsb_1[];
171 extern int tl1_immu_miss_patch_tsb_2[];
172 extern int tl1_immu_miss_patch_tsb_mask_1[];
173 extern int tl1_immu_miss_patch_tsb_mask_2[];
176 * If user pmap is processed with pmap_remove and with pmap_remove and the
177 * resident count drops to 0, there are no more pages to remove, so we
180 #define PMAP_REMOVE_DONE(pm) \
181 ((pm) != kernel_pmap && (pm)->pm_stats.resident_count == 0)
184 * The threshold (in bytes) above which tsb_foreach() is used in pmap_remove()
185 * and pmap_protect() instead of trying each virtual address.
187 #define PMAP_TSB_THRESH ((TSB_SIZE / 2) * PAGE_SIZE)
189 SYSCTL_NODE(_debug, OID_AUTO, pmap_stats, CTLFLAG_RD, 0, "");
191 PMAP_STATS_VAR(pmap_nenter);
192 PMAP_STATS_VAR(pmap_nenter_update);
193 PMAP_STATS_VAR(pmap_nenter_replace);
194 PMAP_STATS_VAR(pmap_nenter_new);
195 PMAP_STATS_VAR(pmap_nkenter);
196 PMAP_STATS_VAR(pmap_nkenter_oc);
197 PMAP_STATS_VAR(pmap_nkenter_stupid);
198 PMAP_STATS_VAR(pmap_nkremove);
199 PMAP_STATS_VAR(pmap_nqenter);
200 PMAP_STATS_VAR(pmap_nqremove);
201 PMAP_STATS_VAR(pmap_ncache_enter);
202 PMAP_STATS_VAR(pmap_ncache_enter_c);
203 PMAP_STATS_VAR(pmap_ncache_enter_oc);
204 PMAP_STATS_VAR(pmap_ncache_enter_cc);
205 PMAP_STATS_VAR(pmap_ncache_enter_coc);
206 PMAP_STATS_VAR(pmap_ncache_enter_nc);
207 PMAP_STATS_VAR(pmap_ncache_enter_cnc);
208 PMAP_STATS_VAR(pmap_ncache_remove);
209 PMAP_STATS_VAR(pmap_ncache_remove_c);
210 PMAP_STATS_VAR(pmap_ncache_remove_oc);
211 PMAP_STATS_VAR(pmap_ncache_remove_cc);
212 PMAP_STATS_VAR(pmap_ncache_remove_coc);
213 PMAP_STATS_VAR(pmap_ncache_remove_nc);
214 PMAP_STATS_VAR(pmap_nzero_page);
215 PMAP_STATS_VAR(pmap_nzero_page_c);
216 PMAP_STATS_VAR(pmap_nzero_page_oc);
217 PMAP_STATS_VAR(pmap_nzero_page_nc);
218 PMAP_STATS_VAR(pmap_nzero_page_area);
219 PMAP_STATS_VAR(pmap_nzero_page_area_c);
220 PMAP_STATS_VAR(pmap_nzero_page_area_oc);
221 PMAP_STATS_VAR(pmap_nzero_page_area_nc);
222 PMAP_STATS_VAR(pmap_ncopy_page);
223 PMAP_STATS_VAR(pmap_ncopy_page_c);
224 PMAP_STATS_VAR(pmap_ncopy_page_oc);
225 PMAP_STATS_VAR(pmap_ncopy_page_nc);
226 PMAP_STATS_VAR(pmap_ncopy_page_dc);
227 PMAP_STATS_VAR(pmap_ncopy_page_doc);
228 PMAP_STATS_VAR(pmap_ncopy_page_sc);
229 PMAP_STATS_VAR(pmap_ncopy_page_soc);
231 PMAP_STATS_VAR(pmap_nnew_thread);
232 PMAP_STATS_VAR(pmap_nnew_thread_oc);
234 static inline u_long dtlb_get_data(u_int tlb, u_int slot);
237 * Quick sort callout for comparing memory regions
239 static int mr_cmp(const void *a, const void *b);
240 static int om_cmp(const void *a, const void *b);
243 mr_cmp(const void *a, const void *b)
245 const struct ofw_mem_region *mra;
246 const struct ofw_mem_region *mrb;
250 if (mra->mr_start < mrb->mr_start)
252 else if (mra->mr_start > mrb->mr_start)
259 om_cmp(const void *a, const void *b)
261 const struct ofw_map *oma;
262 const struct ofw_map *omb;
266 if (oma->om_start < omb->om_start)
268 else if (oma->om_start > omb->om_start)
275 dtlb_get_data(u_int tlb, u_int slot)
280 slot = TLB_DAR_SLOT(tlb, slot);
282 * We read ASI_DTLB_DATA_ACCESS_REG twice back-to-back in order to
283 * work around errata of USIII and beyond.
286 (void)ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
287 data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
293 * Bootstrap the system enough to run with virtual memory.
296 pmap_bootstrap(u_int cpu_impl)
309 u_int dtlb_slots_avail;
318 * Set the kernel context.
322 colors = dcache_color_ignore != 0 ? 1 : DCACHE_COLORS;
325 * Find out what physical memory is available from the PROM and
326 * initialize the phys_avail array. This must be done before
327 * pmap_bootstrap_alloc is called.
329 if ((pmem = OF_finddevice("/memory")) == -1)
330 OF_panic("%s: finddevice /memory", __func__);
331 if ((sz = OF_getproplen(pmem, "available")) == -1)
332 OF_panic("%s: getproplen /memory/available", __func__);
333 if (PHYS_AVAIL_ENTRIES < sz)
334 OF_panic("%s: phys_avail too small", __func__);
335 if (sizeof(mra) < sz)
336 OF_panic("%s: mra too small", __func__);
338 if (OF_getprop(pmem, "available", mra, sz) == -1)
339 OF_panic("%s: getprop /memory/available", __func__);
342 OF_printf("pmap_bootstrap: physical memory\n");
344 qsort(mra, sz, sizeof (*mra), mr_cmp);
346 getenv_quad("hw.physmem", &physmem);
347 physmem = btoc(physmem);
348 for (i = 0, j = 0; i < sz; i++, j += 2) {
350 OF_printf("start=%#lx size=%#lx\n", mra[i].mr_start,
353 if (physmem != 0 && btoc(physsz + mra[i].mr_size) >= physmem) {
354 if (btoc(physsz) < physmem) {
355 phys_avail[j] = mra[i].mr_start;
356 phys_avail[j + 1] = mra[i].mr_start +
357 (ctob(physmem) - physsz);
358 physsz = ctob(physmem);
362 phys_avail[j] = mra[i].mr_start;
363 phys_avail[j + 1] = mra[i].mr_start + mra[i].mr_size;
364 physsz += mra[i].mr_size;
366 physmem = btoc(physsz);
369 * Calculate the size of kernel virtual memory, and the size and mask
370 * for the kernel TSB based on the phsyical memory size but limited
371 * by the amount of dTLB slots available for locked entries if we have
372 * to lock the TSB in the TLB (given that for spitfire-class CPUs all
373 * of the dt64 slots can hold locked entries but there is no large
374 * dTLB for unlocked ones, we don't use more than half of it for the
376 * Note that for reasons unknown OpenSolaris doesn't take advantage of
377 * ASI_ATOMIC_QUAD_LDD_PHYS on UltraSPARC-III. However, given that no
378 * public documentation is available for these, the latter just might
379 * not support it, yet.
381 if (cpu_impl == CPU_IMPL_SPARC64V ||
382 cpu_impl >= CPU_IMPL_ULTRASPARCIIIp) {
383 tsb_kernel_ldd_phys = 1;
384 virtsz = roundup(5 / 3 * physsz, PAGE_SIZE_4M <<
385 (PAGE_SHIFT - TTE_SHIFT));
387 dtlb_slots_avail = 0;
388 for (i = 0; i < dtlb_slots; i++) {
389 data = dtlb_get_data(cpu_impl ==
390 CPU_IMPL_ULTRASPARCIII ? TLB_DAR_T16 :
392 if ((data & (TD_V | TD_L)) != (TD_V | TD_L))
396 dtlb_slots_avail -= PCPU_PAGES;
398 if (cpu_impl >= CPU_IMPL_ULTRASPARCI &&
399 cpu_impl < CPU_IMPL_ULTRASPARCIII)
400 dtlb_slots_avail /= 2;
401 virtsz = roundup(physsz, PAGE_SIZE_4M <<
402 (PAGE_SHIFT - TTE_SHIFT));
403 virtsz = MIN(virtsz, (dtlb_slots_avail * PAGE_SIZE_4M) <<
404 (PAGE_SHIFT - TTE_SHIFT));
406 vm_max_kernel_address = VM_MIN_KERNEL_ADDRESS + virtsz;
407 tsb_kernel_size = virtsz >> (PAGE_SHIFT - TTE_SHIFT);
408 tsb_kernel_mask = (tsb_kernel_size >> TTE_SHIFT) - 1;
411 * Allocate the kernel TSB and lock it in the TLB if necessary.
413 pa = pmap_bootstrap_alloc(tsb_kernel_size, colors);
414 if (pa & PAGE_MASK_4M)
415 OF_panic("%s: TSB unaligned", __func__);
416 tsb_kernel_phys = pa;
417 if (tsb_kernel_ldd_phys == 0) {
419 (struct tte *)(VM_MIN_KERNEL_ADDRESS - tsb_kernel_size);
421 bzero(tsb_kernel, tsb_kernel_size);
424 (struct tte *)TLB_PHYS_TO_DIRECT(tsb_kernel_phys);
425 aszero(ASI_PHYS_USE_EC, tsb_kernel_phys, tsb_kernel_size);
429 * Allocate and map the dynamic per-CPU area for the BSP.
431 pa = pmap_bootstrap_alloc(DPCPU_SIZE, colors);
432 dpcpu0 = (void *)TLB_PHYS_TO_DIRECT(pa);
435 * Allocate and map the message buffer.
437 pa = pmap_bootstrap_alloc(msgbufsize, colors);
438 msgbufp = (struct msgbuf *)TLB_PHYS_TO_DIRECT(pa);
441 * Patch the TSB addresses and mask as well as the ASIs used to load
442 * it into the trap table.
445 #define LDDA_R_I_R(rd, imm_asi, rs1, rs2) \
446 (EIF_OP(IOP_LDST) | EIF_F3_RD(rd) | EIF_F3_OP3(INS3_LDDA) | \
447 EIF_F3_RS1(rs1) | EIF_F3_I(0) | EIF_F3_IMM_ASI(imm_asi) | \
449 #define OR_R_I_R(rd, imm13, rs1) \
450 (EIF_OP(IOP_MISC) | EIF_F3_RD(rd) | EIF_F3_OP3(INS2_OR) | \
451 EIF_F3_RS1(rs1) | EIF_F3_I(1) | EIF_IMM(imm13, 13))
452 #define SETHI(rd, imm22) \
453 (EIF_OP(IOP_FORM2) | EIF_F2_RD(rd) | EIF_F2_OP2(INS0_SETHI) | \
454 EIF_IMM((imm22) >> 10, 22))
455 #define WR_R_I(rd, imm13, rs1) \
456 (EIF_OP(IOP_MISC) | EIF_F3_RD(rd) | EIF_F3_OP3(INS2_WR) | \
457 EIF_F3_RS1(rs1) | EIF_F3_I(1) | EIF_IMM(imm13, 13))
459 #define PATCH_ASI(addr, asi) do { \
460 if (addr[0] != WR_R_I(IF_F3_RD(addr[0]), 0x0, \
461 IF_F3_RS1(addr[0]))) \
462 OF_panic("%s: patched instructions have changed", \
464 addr[0] |= EIF_IMM((asi), 13); \
468 #define PATCH_LDD(addr, asi) do { \
469 if (addr[0] != LDDA_R_I_R(IF_F3_RD(addr[0]), 0x0, \
470 IF_F3_RS1(addr[0]), IF_F3_RS2(addr[0]))) \
471 OF_panic("%s: patched instructions have changed", \
473 addr[0] |= EIF_F3_IMM_ASI(asi); \
477 #define PATCH_TSB(addr, val) do { \
478 if (addr[0] != SETHI(IF_F2_RD(addr[0]), 0x0) || \
479 addr[1] != OR_R_I_R(IF_F3_RD(addr[1]), 0x0, \
480 IF_F3_RS1(addr[1])) || \
481 addr[3] != SETHI(IF_F2_RD(addr[3]), 0x0)) \
482 OF_panic("%s: patched instructions have changed", \
484 addr[0] |= EIF_IMM((val) >> 42, 22); \
485 addr[1] |= EIF_IMM((val) >> 32, 10); \
486 addr[3] |= EIF_IMM((val) >> 10, 22); \
492 #define PATCH_TSB_MASK(addr, val) do { \
493 if (addr[0] != SETHI(IF_F2_RD(addr[0]), 0x0) || \
494 addr[1] != OR_R_I_R(IF_F3_RD(addr[1]), 0x0, \
495 IF_F3_RS1(addr[1]))) \
496 OF_panic("%s: patched instructions have changed", \
498 addr[0] |= EIF_IMM((val) >> 10, 22); \
499 addr[1] |= EIF_IMM((val), 10); \
504 if (tsb_kernel_ldd_phys == 0) {
506 ldd = ASI_NUCLEUS_QUAD_LDD;
507 off = (vm_offset_t)tsb_kernel;
509 asi = ASI_PHYS_USE_EC;
510 ldd = ASI_ATOMIC_QUAD_LDD_PHYS;
511 off = (vm_offset_t)tsb_kernel_phys;
513 PATCH_TSB(tl1_dmmu_miss_direct_patch_tsb_phys_1, tsb_kernel_phys);
514 PATCH_TSB(tl1_dmmu_miss_direct_patch_tsb_phys_end_1,
515 tsb_kernel_phys + tsb_kernel_size - 1);
516 PATCH_ASI(tl1_dmmu_miss_patch_asi_1, asi);
517 PATCH_LDD(tl1_dmmu_miss_patch_quad_ldd_1, ldd);
518 PATCH_TSB(tl1_dmmu_miss_patch_tsb_1, off);
519 PATCH_TSB(tl1_dmmu_miss_patch_tsb_2, off);
520 PATCH_TSB_MASK(tl1_dmmu_miss_patch_tsb_mask_1, tsb_kernel_mask);
521 PATCH_TSB_MASK(tl1_dmmu_miss_patch_tsb_mask_2, tsb_kernel_mask);
522 PATCH_ASI(tl1_dmmu_prot_patch_asi_1, asi);
523 PATCH_LDD(tl1_dmmu_prot_patch_quad_ldd_1, ldd);
524 PATCH_TSB(tl1_dmmu_prot_patch_tsb_1, off);
525 PATCH_TSB(tl1_dmmu_prot_patch_tsb_2, off);
526 PATCH_TSB_MASK(tl1_dmmu_prot_patch_tsb_mask_1, tsb_kernel_mask);
527 PATCH_TSB_MASK(tl1_dmmu_prot_patch_tsb_mask_2, tsb_kernel_mask);
528 PATCH_ASI(tl1_immu_miss_patch_asi_1, asi);
529 PATCH_LDD(tl1_immu_miss_patch_quad_ldd_1, ldd);
530 PATCH_TSB(tl1_immu_miss_patch_tsb_1, off);
531 PATCH_TSB(tl1_immu_miss_patch_tsb_2, off);
532 PATCH_TSB_MASK(tl1_immu_miss_patch_tsb_mask_1, tsb_kernel_mask);
533 PATCH_TSB_MASK(tl1_immu_miss_patch_tsb_mask_2, tsb_kernel_mask);
536 * Enter fake 8k pages for the 4MB kernel pages, so that
537 * pmap_kextract() will work for them.
539 for (i = 0; i < kernel_tlb_slots; i++) {
540 pa = kernel_tlbs[i].te_pa;
541 va = kernel_tlbs[i].te_va;
542 for (off = 0; off < PAGE_SIZE_4M; off += PAGE_SIZE) {
543 tp = tsb_kvtotte(va + off);
544 vpn = TV_VPN(va + off, TS_8K);
545 data = TD_V | TD_8K | TD_PA(pa + off) | TD_REF |
546 TD_SW | TD_CP | TD_CV | TD_P | TD_W;
547 pmap_bootstrap_set_tte(tp, vpn, data);
552 * Set the start and end of KVA. The kernel is loaded starting
553 * at the first available 4MB super page, so we advance to the
554 * end of the last one used for it.
556 virtual_avail = KERNBASE + kernel_tlb_slots * PAGE_SIZE_4M;
557 virtual_end = vm_max_kernel_address;
558 kernel_vm_end = vm_max_kernel_address;
561 * Allocate kva space for temporary mappings.
563 pmap_idle_map = virtual_avail;
564 virtual_avail += PAGE_SIZE * colors;
565 pmap_temp_map_1 = virtual_avail;
566 virtual_avail += PAGE_SIZE * colors;
567 pmap_temp_map_2 = virtual_avail;
568 virtual_avail += PAGE_SIZE * colors;
571 * Allocate a kernel stack with guard page for thread0 and map it
572 * into the kernel TSB. We must ensure that the virtual address is
573 * colored properly for corresponding CPUs, since we're allocating
574 * from phys_avail so the memory won't have an associated vm_page_t.
576 pa = pmap_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, colors);
578 virtual_avail += roundup(KSTACK_GUARD_PAGES, colors) * PAGE_SIZE;
579 kstack0 = virtual_avail;
580 virtual_avail += roundup(KSTACK_PAGES, colors) * PAGE_SIZE;
581 if (dcache_color_ignore == 0)
582 KASSERT(DCACHE_COLOR(kstack0) == DCACHE_COLOR(kstack0_phys),
583 ("pmap_bootstrap: kstack0 miscolored"));
584 for (i = 0; i < KSTACK_PAGES; i++) {
585 pa = kstack0_phys + i * PAGE_SIZE;
586 va = kstack0 + i * PAGE_SIZE;
587 tp = tsb_kvtotte(va);
588 vpn = TV_VPN(va, TS_8K);
589 data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_SW | TD_CP |
591 pmap_bootstrap_set_tte(tp, vpn, data);
595 * Calculate the last available physical address.
597 for (i = 0; phys_avail[i + 2] != 0; i += 2)
599 Maxmem = sparc64_btop(phys_avail[i + 1]);
602 * Add the PROM mappings to the kernel TSB.
604 if ((vmem = OF_finddevice("/virtual-memory")) == -1)
605 OF_panic("%s: finddevice /virtual-memory", __func__);
606 if ((sz = OF_getproplen(vmem, "translations")) == -1)
607 OF_panic("%s: getproplen translations", __func__);
608 if (sizeof(translations) < sz)
609 OF_panic("%s: translations too small", __func__);
610 bzero(translations, sz);
611 if (OF_getprop(vmem, "translations", translations, sz) == -1)
612 OF_panic("%s: getprop /virtual-memory/translations",
614 sz /= sizeof(*translations);
615 translations_size = sz;
617 OF_printf("pmap_bootstrap: translations\n");
619 qsort(translations, sz, sizeof (*translations), om_cmp);
620 for (i = 0; i < sz; i++) {
622 OF_printf("translation: start=%#lx size=%#lx tte=%#lx\n",
623 translations[i].om_start, translations[i].om_size,
624 translations[i].om_tte);
626 if ((translations[i].om_tte & TD_V) == 0)
628 if (translations[i].om_start < VM_MIN_PROM_ADDRESS ||
629 translations[i].om_start > VM_MAX_PROM_ADDRESS)
631 for (off = 0; off < translations[i].om_size;
633 va = translations[i].om_start + off;
634 tp = tsb_kvtotte(va);
635 vpn = TV_VPN(va, TS_8K);
636 data = ((translations[i].om_tte &
637 ~((TD_SOFT2_MASK << TD_SOFT2_SHIFT) |
638 (cpu_impl >= CPU_IMPL_ULTRASPARCI &&
639 cpu_impl < CPU_IMPL_ULTRASPARCIII ?
640 (TD_DIAG_SF_MASK << TD_DIAG_SF_SHIFT) :
641 (TD_RSVD_CH_MASK << TD_RSVD_CH_SHIFT)) |
642 (TD_SOFT_MASK << TD_SOFT_SHIFT))) | TD_EXEC) +
644 pmap_bootstrap_set_tte(tp, vpn, data);
649 * Get the available physical memory ranges from /memory/reg. These
650 * are only used for kernel dumps, but it may not be wise to do PROM
651 * calls in that situation.
653 if ((sz = OF_getproplen(pmem, "reg")) == -1)
654 OF_panic("%s: getproplen /memory/reg", __func__);
655 if (sizeof(sparc64_memreg) < sz)
656 OF_panic("%s: sparc64_memreg too small", __func__);
657 if (OF_getprop(pmem, "reg", sparc64_memreg, sz) == -1)
658 OF_panic("%s: getprop /memory/reg", __func__);
659 sparc64_nmemreg = sz / sizeof(*sparc64_memreg);
662 * Initialize the kernel pmap (which is statically allocated).
666 for (i = 0; i < MAXCPU; i++)
667 pm->pm_context[i] = TLB_CTX_KERNEL;
668 CPU_FILL(&pm->pm_active);
671 * Initialize the global tte list lock, which is more commonly
672 * known as the pmap pv global lock.
674 rw_init(&tte_list_global_lock, "pmap pv global");
677 * Flush all non-locked TLB entries possibly left over by the
680 tlb_flush_nonlocked();
684 pmap_init_qpages(void)
689 if (dcache_color_ignore != 0)
694 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE * DCACHE_COLORS);
695 if (pc->pc_qmap_addr == 0)
696 panic("pmap_init_qpages: unable to allocate KVA");
700 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_qpages, NULL);
703 * Map the 4MB kernel TSB pages.
713 for (i = 0; i < tsb_kernel_size; i += PAGE_SIZE_4M) {
714 va = (vm_offset_t)tsb_kernel + i;
715 pa = tsb_kernel_phys + i;
716 data = TD_V | TD_4M | TD_PA(pa) | TD_L | TD_CP | TD_CV |
718 stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) |
719 TLB_TAR_CTX(TLB_CTX_KERNEL));
720 stxa_sync(0, ASI_DTLB_DATA_IN_REG, data);
725 * Set the secondary context to be the kernel context (needed for FP block
726 * operations in the kernel).
732 stxa(AA_DMMU_SCXR, ASI_DMMU, (ldxa(AA_DMMU_SCXR, ASI_DMMU) &
733 TLB_CXR_PGSZ_MASK) | TLB_CTX_KERNEL);
738 * Allocate a physical page of memory directly from the phys_avail map.
739 * Can only be called from pmap_bootstrap before avail start and end are
743 pmap_bootstrap_alloc(vm_size_t size, uint32_t colors)
748 size = roundup(size, PAGE_SIZE * colors);
749 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
750 if (phys_avail[i + 1] - phys_avail[i] < size)
753 phys_avail[i] += size;
756 OF_panic("%s: no suitable region found", __func__);
760 * Set a TTE. This function is intended as a helper when tsb_kernel is
761 * direct-mapped but we haven't taken over the trap table, yet, as it's the
762 * case when we are taking advantage of ASI_ATOMIC_QUAD_LDD_PHYS to access
766 pmap_bootstrap_set_tte(struct tte *tp, u_long vpn, u_long data)
769 if (tsb_kernel_ldd_phys == 0) {
773 stxa((vm_paddr_t)tp + offsetof(struct tte, tte_vpn),
774 ASI_PHYS_USE_EC, vpn);
775 stxa((vm_paddr_t)tp + offsetof(struct tte, tte_data),
776 ASI_PHYS_USE_EC, data);
781 * Initialize a vm_page's machine-dependent fields.
784 pmap_page_init(vm_page_t m)
787 TAILQ_INIT(&m->md.tte_list);
788 m->md.color = DCACHE_COLOR(VM_PAGE_TO_PHYS(m));
793 * Initialize the pmap module.
803 for (i = 0; i < translations_size; i++) {
804 addr = translations[i].om_start;
805 size = translations[i].om_size;
806 if ((translations[i].om_tte & TD_V) == 0)
808 if (addr < VM_MIN_PROM_ADDRESS || addr > VM_MAX_PROM_ADDRESS)
810 result = vm_map_find(kernel_map, NULL, 0, &addr, size, 0,
811 VMFS_NO_SPACE, VM_PROT_ALL, VM_PROT_ALL, MAP_NOFAULT);
812 if (result != KERN_SUCCESS || addr != translations[i].om_start)
813 panic("pmap_init: vm_map_find");
818 * Extract the physical page address associated with the given
819 * map/virtual_address pair.
822 pmap_extract(pmap_t pm, vm_offset_t va)
827 if (pm == kernel_pmap)
828 return (pmap_kextract(va));
830 tp = tsb_tte_lookup(pm, va);
834 pa = TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp));
840 * Atomically extract and hold the physical page with the given
841 * pmap and virtual address pair if that mapping permits the given
845 pmap_extract_and_hold(pmap_t pm, vm_offset_t va, vm_prot_t prot)
855 if (pm == kernel_pmap) {
856 if (va >= VM_MIN_DIRECT_ADDRESS) {
858 m = PHYS_TO_VM_PAGE(TLB_DIRECT_TO_PHYS(va));
859 (void)vm_page_pa_tryrelock(pm, TLB_DIRECT_TO_PHYS(va),
863 tp = tsb_kvtotte(va);
864 if ((tp->tte_data & TD_V) == 0)
868 tp = tsb_tte_lookup(pm, va);
869 if (tp != NULL && ((tp->tte_data & TD_SW) ||
870 (prot & VM_PROT_WRITE) == 0)) {
871 if (vm_page_pa_tryrelock(pm, TTE_GET_PA(tp), &pa))
873 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
882 * Extract the physical page address associated with the given kernel virtual
886 pmap_kextract(vm_offset_t va)
890 if (va >= VM_MIN_DIRECT_ADDRESS)
891 return (TLB_DIRECT_TO_PHYS(va));
892 tp = tsb_kvtotte(va);
893 if ((tp->tte_data & TD_V) == 0)
895 return (TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp)));
899 pmap_cache_enter(vm_page_t m, vm_offset_t va)
904 rw_assert(&tte_list_global_lock, RA_WLOCKED);
905 KASSERT((m->flags & PG_FICTITIOUS) == 0,
906 ("pmap_cache_enter: fake page"));
907 PMAP_STATS_INC(pmap_ncache_enter);
909 if (dcache_color_ignore != 0)
913 * Find the color for this virtual address and note the added mapping.
915 color = DCACHE_COLOR(va);
916 m->md.colors[color]++;
919 * If all existing mappings have the same color, the mapping is
922 if (m->md.color == color) {
923 KASSERT(m->md.colors[DCACHE_OTHER_COLOR(color)] == 0,
924 ("pmap_cache_enter: cacheable, mappings of other color"));
925 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
926 PMAP_STATS_INC(pmap_ncache_enter_c);
928 PMAP_STATS_INC(pmap_ncache_enter_oc);
933 * If there are no mappings of the other color, and the page still has
934 * the wrong color, this must be a new mapping. Change the color to
935 * match the new mapping, which is cacheable. We must flush the page
936 * from the cache now.
938 if (m->md.colors[DCACHE_OTHER_COLOR(color)] == 0) {
939 KASSERT(m->md.colors[color] == 1,
940 ("pmap_cache_enter: changing color, not new mapping"));
941 dcache_page_inval(VM_PAGE_TO_PHYS(m));
943 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
944 PMAP_STATS_INC(pmap_ncache_enter_cc);
946 PMAP_STATS_INC(pmap_ncache_enter_coc);
951 * If the mapping is already non-cacheable, just return.
953 if (m->md.color == -1) {
954 PMAP_STATS_INC(pmap_ncache_enter_nc);
958 PMAP_STATS_INC(pmap_ncache_enter_cnc);
961 * Mark all mappings as uncacheable, flush any lines with the other
962 * color out of the dcache, and set the color to none (-1).
964 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
965 atomic_clear_long(&tp->tte_data, TD_CV);
966 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
968 dcache_page_inval(VM_PAGE_TO_PHYS(m));
974 pmap_cache_remove(vm_page_t m, vm_offset_t va)
979 rw_assert(&tte_list_global_lock, RA_WLOCKED);
980 CTR3(KTR_PMAP, "pmap_cache_remove: m=%p va=%#lx c=%d", m, va,
981 m->md.colors[DCACHE_COLOR(va)]);
982 KASSERT((m->flags & PG_FICTITIOUS) == 0,
983 ("pmap_cache_remove: fake page"));
984 PMAP_STATS_INC(pmap_ncache_remove);
986 if (dcache_color_ignore != 0)
989 KASSERT(m->md.colors[DCACHE_COLOR(va)] > 0,
990 ("pmap_cache_remove: no mappings %d <= 0",
991 m->md.colors[DCACHE_COLOR(va)]));
994 * Find the color for this virtual address and note the removal of
997 color = DCACHE_COLOR(va);
998 m->md.colors[color]--;
1001 * If the page is cacheable, just return and keep the same color, even
1002 * if there are no longer any mappings.
1004 if (m->md.color != -1) {
1005 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
1006 PMAP_STATS_INC(pmap_ncache_remove_c);
1008 PMAP_STATS_INC(pmap_ncache_remove_oc);
1012 KASSERT(m->md.colors[DCACHE_OTHER_COLOR(color)] != 0,
1013 ("pmap_cache_remove: uncacheable, no mappings of other color"));
1016 * If the page is not cacheable (color is -1), and the number of
1017 * mappings for this color is not zero, just return. There are
1018 * mappings of the other color still, so remain non-cacheable.
1020 if (m->md.colors[color] != 0) {
1021 PMAP_STATS_INC(pmap_ncache_remove_nc);
1026 * The number of mappings for this color is now zero. Recache the
1027 * other colored mappings, and change the page color to the other
1028 * color. There should be no lines in the data cache for this page,
1029 * so flushing should not be needed.
1031 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1032 atomic_set_long(&tp->tte_data, TD_CV);
1033 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1035 m->md.color = DCACHE_OTHER_COLOR(color);
1037 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
1038 PMAP_STATS_INC(pmap_ncache_remove_cc);
1040 PMAP_STATS_INC(pmap_ncache_remove_coc);
1044 * Map a wired page into kernel virtual address space.
1047 pmap_kenter(vm_offset_t va, vm_page_t m)
1054 rw_assert(&tte_list_global_lock, RA_WLOCKED);
1055 PMAP_STATS_INC(pmap_nkenter);
1056 tp = tsb_kvtotte(va);
1057 CTR4(KTR_PMAP, "pmap_kenter: va=%#lx pa=%#lx tp=%p data=%#lx",
1058 va, VM_PAGE_TO_PHYS(m), tp, tp->tte_data);
1059 if (DCACHE_COLOR(VM_PAGE_TO_PHYS(m)) != DCACHE_COLOR(va)) {
1061 "pmap_kenter: off color va=%#lx pa=%#lx o=%p ot=%d pi=%#lx",
1062 va, VM_PAGE_TO_PHYS(m), m->object,
1063 m->object ? m->object->type : -1,
1065 PMAP_STATS_INC(pmap_nkenter_oc);
1067 if ((tp->tte_data & TD_V) != 0) {
1068 om = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
1069 ova = TTE_GET_VA(tp);
1070 if (m == om && va == ova) {
1071 PMAP_STATS_INC(pmap_nkenter_stupid);
1074 TAILQ_REMOVE(&om->md.tte_list, tp, tte_link);
1075 pmap_cache_remove(om, ova);
1077 tlb_page_demap(kernel_pmap, ova);
1079 data = TD_V | TD_8K | VM_PAGE_TO_PHYS(m) | TD_REF | TD_SW | TD_CP |
1081 if (pmap_cache_enter(m, va) != 0)
1083 tp->tte_vpn = TV_VPN(va, TS_8K);
1084 tp->tte_data = data;
1085 TAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link);
1089 * Map a wired page into kernel virtual address space. This additionally
1090 * takes a flag argument which is or'ed to the TTE data. This is used by
1091 * sparc64_bus_mem_map().
1092 * NOTE: if the mapping is non-cacheable, it's the caller's responsibility
1093 * to flush entries that might still be in the cache, if applicable.
1096 pmap_kenter_flags(vm_offset_t va, vm_paddr_t pa, u_long flags)
1100 tp = tsb_kvtotte(va);
1101 CTR4(KTR_PMAP, "pmap_kenter_flags: va=%#lx pa=%#lx tp=%p data=%#lx",
1102 va, pa, tp, tp->tte_data);
1103 tp->tte_vpn = TV_VPN(va, TS_8K);
1104 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_P | flags;
1108 * Remove a wired page from kernel virtual address space.
1111 pmap_kremove(vm_offset_t va)
1116 rw_assert(&tte_list_global_lock, RA_WLOCKED);
1117 PMAP_STATS_INC(pmap_nkremove);
1118 tp = tsb_kvtotte(va);
1119 CTR3(KTR_PMAP, "pmap_kremove: va=%#lx tp=%p data=%#lx", va, tp,
1121 if ((tp->tte_data & TD_V) == 0)
1123 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
1124 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1125 pmap_cache_remove(m, va);
1130 * Inverse of pmap_kenter_flags, used by bus_space_unmap().
1133 pmap_kremove_flags(vm_offset_t va)
1137 tp = tsb_kvtotte(va);
1138 CTR3(KTR_PMAP, "pmap_kremove_flags: va=%#lx tp=%p data=%#lx", va, tp,
1144 * Map a range of physical addresses into kernel virtual address space.
1146 * The value passed in *virt is a suggested virtual address for the mapping.
1147 * Architectures which can support a direct-mapped physical to virtual region
1148 * can return the appropriate address within that region, leaving '*virt'
1152 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1155 return (TLB_PHYS_TO_DIRECT(start));
1159 * Map a list of wired pages into kernel virtual address space. This is
1160 * intended for temporary mappings which do not need page modification or
1161 * references recorded. Existing mappings in the region are overwritten.
1164 pmap_qenter(vm_offset_t sva, vm_page_t *m, int count)
1168 PMAP_STATS_INC(pmap_nqenter);
1170 rw_wlock(&tte_list_global_lock);
1171 while (count-- > 0) {
1172 pmap_kenter(va, *m);
1176 rw_wunlock(&tte_list_global_lock);
1177 tlb_range_demap(kernel_pmap, sva, va);
1181 * Remove page mappings from kernel virtual address space. Intended for
1182 * temporary mappings entered by pmap_qenter.
1185 pmap_qremove(vm_offset_t sva, int count)
1189 PMAP_STATS_INC(pmap_nqremove);
1191 rw_wlock(&tte_list_global_lock);
1192 while (count-- > 0) {
1196 rw_wunlock(&tte_list_global_lock);
1197 tlb_range_demap(kernel_pmap, sva, va);
1201 * Initialize the pmap associated with process 0.
1204 pmap_pinit0(pmap_t pm)
1209 for (i = 0; i < MAXCPU; i++)
1210 pm->pm_context[i] = TLB_CTX_KERNEL;
1211 CPU_ZERO(&pm->pm_active);
1213 pm->pm_tsb_obj = NULL;
1214 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1218 * Initialize a preallocated and zeroed pmap structure, such as one in a
1219 * vmspace structure.
1222 pmap_pinit(pmap_t pm)
1224 vm_page_t ma[TSB_PAGES];
1228 * Allocate KVA space for the TSB.
1230 if (pm->pm_tsb == NULL) {
1231 pm->pm_tsb = (struct tte *)kva_alloc(TSB_BSIZE);
1232 if (pm->pm_tsb == NULL)
1237 * Allocate an object for it.
1239 if (pm->pm_tsb_obj == NULL)
1240 pm->pm_tsb_obj = vm_object_allocate(OBJT_PHYS, TSB_PAGES);
1242 for (i = 0; i < MAXCPU; i++)
1243 pm->pm_context[i] = -1;
1244 CPU_ZERO(&pm->pm_active);
1246 VM_OBJECT_WLOCK(pm->pm_tsb_obj);
1247 (void)vm_page_grab_pages(pm->pm_tsb_obj, 0, VM_ALLOC_NORMAL |
1248 VM_ALLOC_NOBUSY | VM_ALLOC_WIRED | VM_ALLOC_ZERO, ma, TSB_PAGES);
1249 VM_OBJECT_WUNLOCK(pm->pm_tsb_obj);
1250 for (i = 0; i < TSB_PAGES; i++)
1251 ma[i]->md.pmap = pm;
1252 pmap_qenter((vm_offset_t)pm->pm_tsb, ma, TSB_PAGES);
1254 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1259 * Release any resources held by the given physical map.
1260 * Called when a pmap initialized by pmap_pinit is being released.
1261 * Should only be called if the map contains no valid mappings.
1264 pmap_release(pmap_t pm)
1272 CTR2(KTR_PMAP, "pmap_release: ctx=%#x tsb=%p",
1273 pm->pm_context[curcpu], pm->pm_tsb);
1274 KASSERT(pmap_resident_count(pm) == 0,
1275 ("pmap_release: resident pages %ld != 0",
1276 pmap_resident_count(pm)));
1279 * After the pmap was freed, it might be reallocated to a new process.
1280 * When switching, this might lead us to wrongly assume that we need
1281 * not switch contexts because old and new pmap pointer are equal.
1282 * Therefore, make sure that this pmap is not referenced by any PCPU
1283 * pointer any more. This could happen in two cases:
1284 * - A process that referenced the pmap is currently exiting on a CPU.
1285 * However, it is guaranteed to not switch in any more after setting
1286 * its state to PRS_ZOMBIE.
1287 * - A process that referenced this pmap ran on a CPU, but we switched
1288 * to a kernel thread, leaving the pmap pointer unchanged.
1292 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu)
1293 atomic_cmpset_rel_ptr((uintptr_t *)&pc->pc_pmap,
1294 (uintptr_t)pm, (uintptr_t)NULL);
1298 if (PCPU_GET(pmap) == pm)
1299 PCPU_SET(pmap, NULL);
1303 pmap_qremove((vm_offset_t)pm->pm_tsb, TSB_PAGES);
1304 obj = pm->pm_tsb_obj;
1305 VM_OBJECT_WLOCK(obj);
1306 KASSERT(obj->ref_count == 1, ("pmap_release: tsbobj ref count != 1"));
1307 while (!TAILQ_EMPTY(&obj->memq)) {
1308 m = TAILQ_FIRST(&obj->memq);
1310 vm_page_unwire_noq(m);
1311 vm_page_free_zero(m);
1313 VM_OBJECT_WUNLOCK(obj);
1317 * Grow the number of kernel page table entries. Unneeded.
1320 pmap_growkernel(vm_offset_t addr)
1323 panic("pmap_growkernel: can't grow kernel");
1327 pmap_remove_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp,
1333 rw_assert(&tte_list_global_lock, RA_WLOCKED);
1334 data = atomic_readandclear_long(&tp->tte_data);
1335 if ((data & TD_FAKE) == 0) {
1336 m = PHYS_TO_VM_PAGE(TD_PA(data));
1337 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1338 if ((data & TD_WIRED) != 0)
1339 pm->pm_stats.wired_count--;
1340 if ((data & TD_PV) != 0) {
1341 if ((data & TD_W) != 0)
1343 if ((data & TD_REF) != 0)
1344 vm_page_aflag_set(m, PGA_REFERENCED);
1345 if (TAILQ_EMPTY(&m->md.tte_list))
1346 vm_page_aflag_clear(m, PGA_WRITEABLE);
1347 pm->pm_stats.resident_count--;
1349 pmap_cache_remove(m, va);
1352 if (PMAP_REMOVE_DONE(pm))
1358 * Remove the given range of addresses from the specified map.
1361 pmap_remove(pmap_t pm, vm_offset_t start, vm_offset_t end)
1366 CTR3(KTR_PMAP, "pmap_remove: ctx=%#lx start=%#lx end=%#lx",
1367 pm->pm_context[curcpu], start, end);
1368 if (PMAP_REMOVE_DONE(pm))
1370 rw_wlock(&tte_list_global_lock);
1372 if (end - start > PMAP_TSB_THRESH) {
1373 tsb_foreach(pm, NULL, start, end, pmap_remove_tte);
1374 tlb_context_demap(pm);
1376 for (va = start; va < end; va += PAGE_SIZE)
1377 if ((tp = tsb_tte_lookup(pm, va)) != NULL &&
1378 !pmap_remove_tte(pm, NULL, tp, va))
1380 tlb_range_demap(pm, start, end - 1);
1383 rw_wunlock(&tte_list_global_lock);
1387 pmap_remove_all(vm_page_t m)
1394 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1395 ("pmap_remove_all: page %p is not managed", m));
1396 rw_wlock(&tte_list_global_lock);
1397 for (tp = TAILQ_FIRST(&m->md.tte_list); tp != NULL; tp = tpn) {
1398 tpn = TAILQ_NEXT(tp, tte_link);
1399 if ((tp->tte_data & TD_PV) == 0)
1401 pm = TTE_GET_PMAP(tp);
1402 va = TTE_GET_VA(tp);
1404 if ((tp->tte_data & TD_WIRED) != 0)
1405 pm->pm_stats.wired_count--;
1406 if ((tp->tte_data & TD_REF) != 0)
1407 vm_page_aflag_set(m, PGA_REFERENCED);
1408 if ((tp->tte_data & TD_W) != 0)
1410 tp->tte_data &= ~TD_V;
1411 tlb_page_demap(pm, va);
1412 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1413 pm->pm_stats.resident_count--;
1414 pmap_cache_remove(m, va);
1418 vm_page_aflag_clear(m, PGA_WRITEABLE);
1419 rw_wunlock(&tte_list_global_lock);
1423 pmap_protect_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp,
1429 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1430 data = atomic_clear_long(&tp->tte_data, TD_SW | TD_W);
1431 if ((data & (TD_PV | TD_W)) == (TD_PV | TD_W)) {
1432 m = PHYS_TO_VM_PAGE(TD_PA(data));
1439 * Set the physical protection on the specified range of this map as requested.
1442 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
1447 CTR4(KTR_PMAP, "pmap_protect: ctx=%#lx sva=%#lx eva=%#lx prot=%#lx",
1448 pm->pm_context[curcpu], sva, eva, prot);
1450 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1451 pmap_remove(pm, sva, eva);
1455 if (prot & VM_PROT_WRITE)
1459 if (eva - sva > PMAP_TSB_THRESH) {
1460 tsb_foreach(pm, NULL, sva, eva, pmap_protect_tte);
1461 tlb_context_demap(pm);
1463 for (va = sva; va < eva; va += PAGE_SIZE)
1464 if ((tp = tsb_tte_lookup(pm, va)) != NULL)
1465 pmap_protect_tte(pm, NULL, tp, va);
1466 tlb_range_demap(pm, sva, eva - 1);
1472 * Map the given physical page at the specified virtual address in the
1473 * target pmap with the protection requested. If specified the page
1474 * will be wired down.
1477 pmap_enter(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1478 u_int flags, int8_t psind)
1482 rw_wlock(&tte_list_global_lock);
1484 rv = pmap_enter_locked(pm, va, m, prot, flags, psind);
1485 rw_wunlock(&tte_list_global_lock);
1491 * Map the given physical page at the specified virtual address in the
1492 * target pmap with the protection requested. If specified the page
1493 * will be wired down.
1495 * The page queues and pmap must be locked.
1498 pmap_enter_locked(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1499 u_int flags, int8_t psind __unused)
1507 rw_assert(&tte_list_global_lock, RA_WLOCKED);
1508 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1509 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1510 VM_OBJECT_ASSERT_LOCKED(m->object);
1511 PMAP_STATS_INC(pmap_nenter);
1512 pa = VM_PAGE_TO_PHYS(m);
1513 wired = (flags & PMAP_ENTER_WIRED) != 0;
1516 * If this is a fake page from the device_pager, but it covers actual
1517 * physical memory, convert to the real backing page.
1519 if ((m->flags & PG_FICTITIOUS) != 0) {
1520 real = vm_phys_paddr_to_vm_page(pa);
1526 "pmap_enter_locked: ctx=%p m=%p va=%#lx pa=%#lx prot=%#x wired=%d",
1527 pm->pm_context[curcpu], m, va, pa, prot, wired);
1530 * If there is an existing mapping, and the physical address has not
1531 * changed, must be protection or wiring change.
1533 if ((tp = tsb_tte_lookup(pm, va)) != NULL && TTE_GET_PA(tp) == pa) {
1534 CTR0(KTR_PMAP, "pmap_enter_locked: update");
1535 PMAP_STATS_INC(pmap_nenter_update);
1538 * Wiring change, just update stats.
1541 if ((tp->tte_data & TD_WIRED) == 0) {
1542 tp->tte_data |= TD_WIRED;
1543 pm->pm_stats.wired_count++;
1546 if ((tp->tte_data & TD_WIRED) != 0) {
1547 tp->tte_data &= ~TD_WIRED;
1548 pm->pm_stats.wired_count--;
1553 * Save the old bits and clear the ones we're interested in.
1555 data = tp->tte_data;
1556 tp->tte_data &= ~(TD_EXEC | TD_SW | TD_W);
1559 * If we're turning off write permissions, sense modify status.
1561 if ((prot & VM_PROT_WRITE) != 0) {
1562 tp->tte_data |= TD_SW;
1564 tp->tte_data |= TD_W;
1565 if ((m->oflags & VPO_UNMANAGED) == 0)
1566 vm_page_aflag_set(m, PGA_WRITEABLE);
1567 } else if ((data & TD_W) != 0)
1571 * If we're turning on execute permissions, flush the icache.
1573 if ((prot & VM_PROT_EXECUTE) != 0) {
1574 if ((data & TD_EXEC) == 0)
1575 icache_page_inval(pa);
1576 tp->tte_data |= TD_EXEC;
1580 * Delete the old mapping.
1582 tlb_page_demap(pm, TTE_GET_VA(tp));
1585 * If there is an existing mapping, but its for a different
1586 * physical address, delete the old mapping.
1589 CTR0(KTR_PMAP, "pmap_enter_locked: replace");
1590 PMAP_STATS_INC(pmap_nenter_replace);
1591 pmap_remove_tte(pm, NULL, tp, va);
1592 tlb_page_demap(pm, va);
1594 CTR0(KTR_PMAP, "pmap_enter_locked: new");
1595 PMAP_STATS_INC(pmap_nenter_new);
1599 * Now set up the data and install the new mapping.
1601 data = TD_V | TD_8K | TD_PA(pa);
1602 if (pm == kernel_pmap)
1604 if ((prot & VM_PROT_WRITE) != 0) {
1606 if ((m->oflags & VPO_UNMANAGED) == 0)
1607 vm_page_aflag_set(m, PGA_WRITEABLE);
1609 if (prot & VM_PROT_EXECUTE) {
1611 icache_page_inval(pa);
1615 * If its wired update stats. We also don't need reference or
1616 * modify tracking for wired mappings, so set the bits now.
1619 pm->pm_stats.wired_count++;
1620 data |= TD_REF | TD_WIRED;
1621 if ((prot & VM_PROT_WRITE) != 0)
1625 tsb_tte_enter(pm, m, va, TS_8K, data);
1628 return (KERN_SUCCESS);
1632 * Maps a sequence of resident pages belonging to the same object.
1633 * The sequence begins with the given page m_start. This page is
1634 * mapped at the given virtual address start. Each subsequent page is
1635 * mapped at a virtual address that is offset from start by the same
1636 * amount as the page is offset from m_start within the object. The
1637 * last page in the sequence is the page with the largest offset from
1638 * m_start that can be mapped at a virtual address less than the given
1639 * virtual address end. Not every virtual page between start and end
1640 * is mapped; only those for which a resident page exists with the
1641 * corresponding offset from m_start are mapped.
1644 pmap_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end,
1645 vm_page_t m_start, vm_prot_t prot)
1648 vm_pindex_t diff, psize;
1650 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1652 psize = atop(end - start);
1654 rw_wlock(&tte_list_global_lock);
1656 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1657 pmap_enter_locked(pm, start + ptoa(diff), m, prot &
1658 (VM_PROT_READ | VM_PROT_EXECUTE), 0, 0);
1659 m = TAILQ_NEXT(m, listq);
1661 rw_wunlock(&tte_list_global_lock);
1666 pmap_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot)
1669 rw_wlock(&tte_list_global_lock);
1671 pmap_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1673 rw_wunlock(&tte_list_global_lock);
1678 pmap_object_init_pt(pmap_t pm, vm_offset_t addr, vm_object_t object,
1679 vm_pindex_t pindex, vm_size_t size)
1682 VM_OBJECT_ASSERT_WLOCKED(object);
1683 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
1684 ("pmap_object_init_pt: non-device object"));
1688 pmap_unwire_tte(pmap_t pm, pmap_t pm2, struct tte *tp, vm_offset_t va)
1691 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1692 if ((tp->tte_data & TD_WIRED) == 0)
1693 panic("pmap_unwire_tte: tp %p is missing TD_WIRED", tp);
1694 atomic_clear_long(&tp->tte_data, TD_WIRED);
1695 pm->pm_stats.wired_count--;
1700 * Clear the wired attribute from the mappings for the specified range of
1701 * addresses in the given pmap. Every valid mapping within that range must
1702 * have the wired attribute set. In contrast, invalid mappings cannot have
1703 * the wired attribute set, so they are ignored.
1705 * The wired attribute of the translation table entry is not a hardware
1706 * feature, so there is no need to invalidate any TLB entries.
1709 pmap_unwire(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1715 if (eva - sva > PMAP_TSB_THRESH)
1716 tsb_foreach(pm, NULL, sva, eva, pmap_unwire_tte);
1718 for (va = sva; va < eva; va += PAGE_SIZE)
1719 if ((tp = tsb_tte_lookup(pm, va)) != NULL)
1720 pmap_unwire_tte(pm, NULL, tp, va);
1726 pmap_copy_tte(pmap_t src_pmap, pmap_t dst_pmap, struct tte *tp,
1732 if ((tp->tte_data & TD_FAKE) != 0)
1734 if (tsb_tte_lookup(dst_pmap, va) == NULL) {
1735 data = tp->tte_data &
1736 ~(TD_PV | TD_REF | TD_SW | TD_CV | TD_W);
1737 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
1738 tsb_tte_enter(dst_pmap, m, va, TS_8K, data);
1744 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
1745 vm_size_t len, vm_offset_t src_addr)
1750 if (dst_addr != src_addr)
1752 rw_wlock(&tte_list_global_lock);
1753 if (dst_pmap < src_pmap) {
1754 PMAP_LOCK(dst_pmap);
1755 PMAP_LOCK(src_pmap);
1757 PMAP_LOCK(src_pmap);
1758 PMAP_LOCK(dst_pmap);
1760 if (len > PMAP_TSB_THRESH) {
1761 tsb_foreach(src_pmap, dst_pmap, src_addr, src_addr + len,
1763 tlb_context_demap(dst_pmap);
1765 for (va = src_addr; va < src_addr + len; va += PAGE_SIZE)
1766 if ((tp = tsb_tte_lookup(src_pmap, va)) != NULL)
1767 pmap_copy_tte(src_pmap, dst_pmap, tp, va);
1768 tlb_range_demap(dst_pmap, src_addr, src_addr + len - 1);
1770 rw_wunlock(&tte_list_global_lock);
1771 PMAP_UNLOCK(src_pmap);
1772 PMAP_UNLOCK(dst_pmap);
1776 pmap_zero_page(vm_page_t m)
1782 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1783 ("pmap_zero_page: fake page"));
1784 PMAP_STATS_INC(pmap_nzero_page);
1785 pa = VM_PAGE_TO_PHYS(m);
1786 if (dcache_color_ignore != 0 || m->md.color == DCACHE_COLOR(pa)) {
1787 PMAP_STATS_INC(pmap_nzero_page_c);
1788 va = TLB_PHYS_TO_DIRECT(pa);
1789 cpu_block_zero((void *)va, PAGE_SIZE);
1790 } else if (m->md.color == -1) {
1791 PMAP_STATS_INC(pmap_nzero_page_nc);
1792 aszero(ASI_PHYS_USE_EC, pa, PAGE_SIZE);
1794 PMAP_STATS_INC(pmap_nzero_page_oc);
1795 PMAP_LOCK(kernel_pmap);
1796 va = pmap_temp_map_1 + (m->md.color * PAGE_SIZE);
1797 tp = tsb_kvtotte(va);
1798 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1799 tp->tte_vpn = TV_VPN(va, TS_8K);
1800 cpu_block_zero((void *)va, PAGE_SIZE);
1801 tlb_page_demap(kernel_pmap, va);
1802 PMAP_UNLOCK(kernel_pmap);
1807 pmap_zero_page_area(vm_page_t m, int off, int size)
1813 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1814 ("pmap_zero_page_area: fake page"));
1815 KASSERT(off + size <= PAGE_SIZE, ("pmap_zero_page_area: bad off/size"));
1816 PMAP_STATS_INC(pmap_nzero_page_area);
1817 pa = VM_PAGE_TO_PHYS(m);
1818 if (dcache_color_ignore != 0 || m->md.color == DCACHE_COLOR(pa)) {
1819 PMAP_STATS_INC(pmap_nzero_page_area_c);
1820 va = TLB_PHYS_TO_DIRECT(pa);
1821 bzero((void *)(va + off), size);
1822 } else if (m->md.color == -1) {
1823 PMAP_STATS_INC(pmap_nzero_page_area_nc);
1824 aszero(ASI_PHYS_USE_EC, pa + off, size);
1826 PMAP_STATS_INC(pmap_nzero_page_area_oc);
1827 PMAP_LOCK(kernel_pmap);
1828 va = pmap_temp_map_1 + (m->md.color * PAGE_SIZE);
1829 tp = tsb_kvtotte(va);
1830 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1831 tp->tte_vpn = TV_VPN(va, TS_8K);
1832 bzero((void *)(va + off), size);
1833 tlb_page_demap(kernel_pmap, va);
1834 PMAP_UNLOCK(kernel_pmap);
1839 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
1847 KASSERT((mdst->flags & PG_FICTITIOUS) == 0,
1848 ("pmap_copy_page: fake dst page"));
1849 KASSERT((msrc->flags & PG_FICTITIOUS) == 0,
1850 ("pmap_copy_page: fake src page"));
1851 PMAP_STATS_INC(pmap_ncopy_page);
1852 pdst = VM_PAGE_TO_PHYS(mdst);
1853 psrc = VM_PAGE_TO_PHYS(msrc);
1854 if (dcache_color_ignore != 0 ||
1855 (msrc->md.color == DCACHE_COLOR(psrc) &&
1856 mdst->md.color == DCACHE_COLOR(pdst))) {
1857 PMAP_STATS_INC(pmap_ncopy_page_c);
1858 vdst = TLB_PHYS_TO_DIRECT(pdst);
1859 vsrc = TLB_PHYS_TO_DIRECT(psrc);
1860 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE);
1861 } else if (msrc->md.color == -1 && mdst->md.color == -1) {
1862 PMAP_STATS_INC(pmap_ncopy_page_nc);
1863 ascopy(ASI_PHYS_USE_EC, psrc, pdst, PAGE_SIZE);
1864 } else if (msrc->md.color == -1) {
1865 if (mdst->md.color == DCACHE_COLOR(pdst)) {
1866 PMAP_STATS_INC(pmap_ncopy_page_dc);
1867 vdst = TLB_PHYS_TO_DIRECT(pdst);
1868 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst,
1871 PMAP_STATS_INC(pmap_ncopy_page_doc);
1872 PMAP_LOCK(kernel_pmap);
1873 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE);
1874 tp = tsb_kvtotte(vdst);
1876 TD_V | TD_8K | TD_PA(pdst) | TD_CP | TD_CV | TD_W;
1877 tp->tte_vpn = TV_VPN(vdst, TS_8K);
1878 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst,
1880 tlb_page_demap(kernel_pmap, vdst);
1881 PMAP_UNLOCK(kernel_pmap);
1883 } else if (mdst->md.color == -1) {
1884 if (msrc->md.color == DCACHE_COLOR(psrc)) {
1885 PMAP_STATS_INC(pmap_ncopy_page_sc);
1886 vsrc = TLB_PHYS_TO_DIRECT(psrc);
1887 ascopyto((void *)vsrc, ASI_PHYS_USE_EC, pdst,
1890 PMAP_STATS_INC(pmap_ncopy_page_soc);
1891 PMAP_LOCK(kernel_pmap);
1892 vsrc = pmap_temp_map_1 + (msrc->md.color * PAGE_SIZE);
1893 tp = tsb_kvtotte(vsrc);
1895 TD_V | TD_8K | TD_PA(psrc) | TD_CP | TD_CV | TD_W;
1896 tp->tte_vpn = TV_VPN(vsrc, TS_8K);
1897 ascopyto((void *)vsrc, ASI_PHYS_USE_EC, pdst,
1899 tlb_page_demap(kernel_pmap, vsrc);
1900 PMAP_UNLOCK(kernel_pmap);
1903 PMAP_STATS_INC(pmap_ncopy_page_oc);
1904 PMAP_LOCK(kernel_pmap);
1905 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE);
1906 tp = tsb_kvtotte(vdst);
1908 TD_V | TD_8K | TD_PA(pdst) | TD_CP | TD_CV | TD_W;
1909 tp->tte_vpn = TV_VPN(vdst, TS_8K);
1910 vsrc = pmap_temp_map_2 + (msrc->md.color * PAGE_SIZE);
1911 tp = tsb_kvtotte(vsrc);
1913 TD_V | TD_8K | TD_PA(psrc) | TD_CP | TD_CV | TD_W;
1914 tp->tte_vpn = TV_VPN(vsrc, TS_8K);
1915 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE);
1916 tlb_page_demap(kernel_pmap, vdst);
1917 tlb_page_demap(kernel_pmap, vsrc);
1918 PMAP_UNLOCK(kernel_pmap);
1923 pmap_quick_enter_page(vm_page_t m)
1929 pa = VM_PAGE_TO_PHYS(m);
1930 if (dcache_color_ignore != 0 || m->md.color == DCACHE_COLOR(pa))
1931 return (TLB_PHYS_TO_DIRECT(pa));
1934 qaddr = PCPU_GET(qmap_addr);
1935 qaddr += (PAGE_SIZE * ((DCACHE_COLORS + DCACHE_COLOR(pa) -
1936 DCACHE_COLOR(qaddr)) % DCACHE_COLORS));
1937 tp = tsb_kvtotte(qaddr);
1939 KASSERT(tp->tte_data == 0, ("pmap_quick_enter_page: PTE busy"));
1941 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1942 tp->tte_vpn = TV_VPN(qaddr, TS_8K);
1948 pmap_quick_remove_page(vm_offset_t addr)
1953 if (addr >= VM_MIN_DIRECT_ADDRESS)
1956 tp = tsb_kvtotte(addr);
1957 qaddr = PCPU_GET(qmap_addr);
1959 KASSERT((addr >= qaddr) && (addr < (qaddr + (PAGE_SIZE * DCACHE_COLORS))),
1960 ("pmap_quick_remove_page: invalid address"));
1961 KASSERT(tp->tte_data != 0, ("pmap_quick_remove_page: PTE not in use"));
1963 stxa(TLB_DEMAP_VA(addr) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE, ASI_DMMU_DEMAP, 0);
1964 stxa(TLB_DEMAP_VA(addr) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE, ASI_IMMU_DEMAP, 0);
1970 int unmapped_buf_allowed;
1973 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
1974 vm_offset_t b_offset, int xfersize)
1977 panic("pmap_copy_pages: not implemented");
1981 * Returns true if the pmap's pv is one of the first
1982 * 16 pvs linked to from this page. This count may
1983 * be changed upwards or downwards in the future; it
1984 * is only necessary that true be returned for a small
1985 * subset of pmaps for proper page aging.
1988 pmap_page_exists_quick(pmap_t pm, vm_page_t m)
1994 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1995 ("pmap_page_exists_quick: page %p is not managed", m));
1998 rw_wlock(&tte_list_global_lock);
1999 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2000 if ((tp->tte_data & TD_PV) == 0)
2002 if (TTE_GET_PMAP(tp) == pm) {
2009 rw_wunlock(&tte_list_global_lock);
2014 * Return the number of managed mappings to the given physical page
2018 pmap_page_wired_mappings(vm_page_t m)
2024 if ((m->oflags & VPO_UNMANAGED) != 0)
2026 rw_wlock(&tte_list_global_lock);
2027 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link)
2028 if ((tp->tte_data & (TD_PV | TD_WIRED)) == (TD_PV | TD_WIRED))
2030 rw_wunlock(&tte_list_global_lock);
2035 * Remove all pages from specified address space, this aids process exit
2036 * speeds. This is much faster than pmap_remove in the case of running down
2037 * an entire address space. Only works for the current pmap.
2040 pmap_remove_pages(pmap_t pm)
2046 * Returns TRUE if the given page has a managed mapping.
2049 pmap_page_is_mapped(vm_page_t m)
2055 if ((m->oflags & VPO_UNMANAGED) != 0)
2057 rw_wlock(&tte_list_global_lock);
2058 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link)
2059 if ((tp->tte_data & TD_PV) != 0) {
2063 rw_wunlock(&tte_list_global_lock);
2068 * Return a count of reference bits for a page, clearing those bits.
2069 * It is not necessary for every reference bit to be cleared, but it
2070 * is necessary that 0 only be returned when there are truly no
2071 * reference bits set.
2073 * As an optimization, update the page's dirty field if a modified bit is
2074 * found while counting reference bits. This opportunistic update can be
2075 * performed at low cost and can eliminate the need for some future calls
2076 * to pmap_is_modified(). However, since this function stops after
2077 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
2078 * dirty pages. Those dirty pages will only be detected by a future call
2079 * to pmap_is_modified().
2082 pmap_ts_referenced(vm_page_t m)
2090 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2091 ("pmap_ts_referenced: page %p is not managed", m));
2093 rw_wlock(&tte_list_global_lock);
2094 if ((tp = TAILQ_FIRST(&m->md.tte_list)) != NULL) {
2097 tpn = TAILQ_NEXT(tp, tte_link);
2098 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
2099 TAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link);
2100 if ((tp->tte_data & TD_PV) == 0)
2102 data = atomic_clear_long(&tp->tte_data, TD_REF);
2103 if ((data & TD_W) != 0)
2105 if ((data & TD_REF) != 0 && ++count >=
2106 PMAP_TS_REFERENCED_MAX)
2108 } while ((tp = tpn) != NULL && tp != tpf);
2110 rw_wunlock(&tte_list_global_lock);
2115 pmap_is_modified(vm_page_t m)
2120 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2121 ("pmap_is_modified: page %p is not managed", m));
2125 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2126 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
2127 * is clear, no TTEs can have TD_W set.
2129 VM_OBJECT_ASSERT_WLOCKED(m->object);
2130 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2132 rw_wlock(&tte_list_global_lock);
2133 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2134 if ((tp->tte_data & TD_PV) == 0)
2136 if ((tp->tte_data & TD_W) != 0) {
2141 rw_wunlock(&tte_list_global_lock);
2146 * pmap_is_prefaultable:
2148 * Return whether or not the specified virtual address is elgible
2152 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
2157 rv = tsb_tte_lookup(pmap, addr) == NULL;
2163 * Return whether or not the specified physical page was referenced
2164 * in any physical maps.
2167 pmap_is_referenced(vm_page_t m)
2172 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2173 ("pmap_is_referenced: page %p is not managed", m));
2175 rw_wlock(&tte_list_global_lock);
2176 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2177 if ((tp->tte_data & TD_PV) == 0)
2179 if ((tp->tte_data & TD_REF) != 0) {
2184 rw_wunlock(&tte_list_global_lock);
2189 * This function is advisory.
2192 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
2197 pmap_clear_modify(vm_page_t m)
2202 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2203 ("pmap_clear_modify: page %p is not managed", m));
2204 VM_OBJECT_ASSERT_WLOCKED(m->object);
2205 KASSERT(!vm_page_xbusied(m),
2206 ("pmap_clear_modify: page %p is exclusive busied", m));
2209 * If the page is not PGA_WRITEABLE, then no TTEs can have TD_W set.
2210 * If the object containing the page is locked and the page is not
2211 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
2213 if ((m->aflags & PGA_WRITEABLE) == 0)
2215 rw_wlock(&tte_list_global_lock);
2216 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2217 if ((tp->tte_data & TD_PV) == 0)
2219 data = atomic_clear_long(&tp->tte_data, TD_W);
2220 if ((data & TD_W) != 0)
2221 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
2223 rw_wunlock(&tte_list_global_lock);
2227 pmap_remove_write(vm_page_t m)
2232 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2233 ("pmap_remove_write: page %p is not managed", m));
2236 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2237 * set by another thread while the object is locked. Thus,
2238 * if PGA_WRITEABLE is clear, no page table entries need updating.
2240 VM_OBJECT_ASSERT_WLOCKED(m->object);
2241 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2243 rw_wlock(&tte_list_global_lock);
2244 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2245 if ((tp->tte_data & TD_PV) == 0)
2247 data = atomic_clear_long(&tp->tte_data, TD_SW | TD_W);
2248 if ((data & TD_W) != 0) {
2250 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
2253 vm_page_aflag_clear(m, PGA_WRITEABLE);
2254 rw_wunlock(&tte_list_global_lock);
2258 pmap_mincore(pmap_t pm, vm_offset_t addr, vm_paddr_t *locked_pa)
2266 * Activate a user pmap. The pmap must be activated before its address space
2267 * can be accessed in any way.
2270 pmap_activate(struct thread *td)
2277 vm = td->td_proc->p_vmspace;
2278 pm = vmspace_pmap(vm);
2280 context = PCPU_GET(tlb_ctx);
2281 if (context == PCPU_GET(tlb_ctx_max)) {
2283 context = PCPU_GET(tlb_ctx_min);
2285 PCPU_SET(tlb_ctx, context + 1);
2287 pm->pm_context[curcpu] = context;
2289 CPU_SET_ATOMIC(PCPU_GET(cpuid), &pm->pm_active);
2290 atomic_store_acq_ptr((uintptr_t *)PCPU_PTR(pmap), (uintptr_t)pm);
2292 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
2296 stxa(AA_DMMU_TSB, ASI_DMMU, pm->pm_tsb);
2297 stxa(AA_IMMU_TSB, ASI_IMMU, pm->pm_tsb);
2298 stxa(AA_DMMU_PCXR, ASI_DMMU, (ldxa(AA_DMMU_PCXR, ASI_DMMU) &
2299 TLB_CXR_PGSZ_MASK) | context);
2305 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
2311 * Increase the starting virtual address of the given mapping if a
2312 * different alignment might result in more superpage mappings.
2315 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
2316 vm_offset_t *addr, vm_size_t size)
2322 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2325 return (mode == VM_MEMATTR_DEFAULT);