2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
9 * This code is derived from software contributed to Berkeley by
10 * the Systems Programming Group of the University of Utah Computer
11 * Science Department and William Jolitz of UUNET Technologies Inc.
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
40 #include <sys/cdefs.h>
41 __FBSDID("$FreeBSD$");
44 * Manages physical address maps.
46 * Since the information managed by this module is also stored by the
47 * logical address mapping module, this module may throw away valid virtual
48 * to physical mappings at almost any time. However, invalidations of
49 * mappings must be done as requested.
51 * In order to cope with hardware architectures which make virtual to
52 * physical map invalidates expensive, this module may delay invalidate
53 * reduced protection operations until such time as they are actually
54 * necessary. This module is given full information as to which processors
55 * are currently using which maps, and to when physical maps must be made
59 #include "opt_kstack_pages.h"
62 #include <sys/param.h>
63 #include <sys/kernel.h>
66 #include <sys/msgbuf.h>
67 #include <sys/mutex.h>
69 #include <sys/rwlock.h>
71 #include <sys/sysctl.h>
72 #include <sys/systm.h>
73 #include <sys/vmmeter.h>
75 #include <dev/ofw/openfirm.h>
78 #include <vm/vm_param.h>
79 #include <vm/vm_kern.h>
80 #include <vm/vm_page.h>
81 #include <vm/vm_map.h>
82 #include <vm/vm_object.h>
83 #include <vm/vm_extern.h>
84 #include <vm/vm_pageout.h>
85 #include <vm/vm_pager.h>
86 #include <vm/vm_phys.h>
88 #include <machine/cache.h>
89 #include <machine/frame.h>
90 #include <machine/instr.h>
91 #include <machine/md_var.h>
92 #include <machine/metadata.h>
93 #include <machine/ofw_mem.h>
94 #include <machine/smp.h>
95 #include <machine/tlb.h>
96 #include <machine/tte.h>
97 #include <machine/tsb.h>
98 #include <machine/ver.h>
101 * Virtual address of message buffer
103 struct msgbuf *msgbufp;
106 * Map of physical memory reagions
108 vm_paddr_t phys_avail[128];
109 static struct ofw_mem_region mra[128];
110 struct ofw_mem_region sparc64_memreg[128];
112 static struct ofw_map translations[128];
113 static int translations_size;
115 static vm_offset_t pmap_idle_map;
116 static vm_offset_t pmap_temp_map_1;
117 static vm_offset_t pmap_temp_map_2;
120 * First and last available kernel virtual addresses
122 vm_offset_t virtual_avail;
123 vm_offset_t virtual_end;
124 vm_offset_t kernel_vm_end;
126 vm_offset_t vm_max_kernel_address;
131 struct pmap kernel_pmap_store;
133 struct rwlock_padalign tte_list_global_lock;
136 * Allocate physical memory for use in pmap_bootstrap.
138 static vm_paddr_t pmap_bootstrap_alloc(vm_size_t size, uint32_t colors);
140 static void pmap_bootstrap_set_tte(struct tte *tp, u_long vpn, u_long data);
141 static void pmap_cache_remove(vm_page_t m, vm_offset_t va);
142 static int pmap_protect_tte(struct pmap *pm1, struct pmap *pm2,
143 struct tte *tp, vm_offset_t va);
144 static int pmap_unwire_tte(pmap_t pm, pmap_t pm2, struct tte *tp,
146 static void pmap_init_qpages(void);
149 * Map the given physical page at the specified virtual address in the
150 * target pmap with the protection requested. If specified the page
151 * will be wired down.
153 * The page queues and pmap must be locked.
155 static int pmap_enter_locked(pmap_t pm, vm_offset_t va, vm_page_t m,
156 vm_prot_t prot, u_int flags, int8_t psind);
158 extern int tl1_dmmu_miss_direct_patch_tsb_phys_1[];
159 extern int tl1_dmmu_miss_direct_patch_tsb_phys_end_1[];
160 extern int tl1_dmmu_miss_patch_asi_1[];
161 extern int tl1_dmmu_miss_patch_quad_ldd_1[];
162 extern int tl1_dmmu_miss_patch_tsb_1[];
163 extern int tl1_dmmu_miss_patch_tsb_2[];
164 extern int tl1_dmmu_miss_patch_tsb_mask_1[];
165 extern int tl1_dmmu_miss_patch_tsb_mask_2[];
166 extern int tl1_dmmu_prot_patch_asi_1[];
167 extern int tl1_dmmu_prot_patch_quad_ldd_1[];
168 extern int tl1_dmmu_prot_patch_tsb_1[];
169 extern int tl1_dmmu_prot_patch_tsb_2[];
170 extern int tl1_dmmu_prot_patch_tsb_mask_1[];
171 extern int tl1_dmmu_prot_patch_tsb_mask_2[];
172 extern int tl1_immu_miss_patch_asi_1[];
173 extern int tl1_immu_miss_patch_quad_ldd_1[];
174 extern int tl1_immu_miss_patch_tsb_1[];
175 extern int tl1_immu_miss_patch_tsb_2[];
176 extern int tl1_immu_miss_patch_tsb_mask_1[];
177 extern int tl1_immu_miss_patch_tsb_mask_2[];
180 * If user pmap is processed with pmap_remove and with pmap_remove and the
181 * resident count drops to 0, there are no more pages to remove, so we
184 #define PMAP_REMOVE_DONE(pm) \
185 ((pm) != kernel_pmap && (pm)->pm_stats.resident_count == 0)
188 * The threshold (in bytes) above which tsb_foreach() is used in pmap_remove()
189 * and pmap_protect() instead of trying each virtual address.
191 #define PMAP_TSB_THRESH ((TSB_SIZE / 2) * PAGE_SIZE)
193 SYSCTL_NODE(_debug, OID_AUTO, pmap_stats, CTLFLAG_RD, 0, "");
195 PMAP_STATS_VAR(pmap_nenter);
196 PMAP_STATS_VAR(pmap_nenter_update);
197 PMAP_STATS_VAR(pmap_nenter_replace);
198 PMAP_STATS_VAR(pmap_nenter_new);
199 PMAP_STATS_VAR(pmap_nkenter);
200 PMAP_STATS_VAR(pmap_nkenter_oc);
201 PMAP_STATS_VAR(pmap_nkenter_stupid);
202 PMAP_STATS_VAR(pmap_nkremove);
203 PMAP_STATS_VAR(pmap_nqenter);
204 PMAP_STATS_VAR(pmap_nqremove);
205 PMAP_STATS_VAR(pmap_ncache_enter);
206 PMAP_STATS_VAR(pmap_ncache_enter_c);
207 PMAP_STATS_VAR(pmap_ncache_enter_oc);
208 PMAP_STATS_VAR(pmap_ncache_enter_cc);
209 PMAP_STATS_VAR(pmap_ncache_enter_coc);
210 PMAP_STATS_VAR(pmap_ncache_enter_nc);
211 PMAP_STATS_VAR(pmap_ncache_enter_cnc);
212 PMAP_STATS_VAR(pmap_ncache_remove);
213 PMAP_STATS_VAR(pmap_ncache_remove_c);
214 PMAP_STATS_VAR(pmap_ncache_remove_oc);
215 PMAP_STATS_VAR(pmap_ncache_remove_cc);
216 PMAP_STATS_VAR(pmap_ncache_remove_coc);
217 PMAP_STATS_VAR(pmap_ncache_remove_nc);
218 PMAP_STATS_VAR(pmap_nzero_page);
219 PMAP_STATS_VAR(pmap_nzero_page_c);
220 PMAP_STATS_VAR(pmap_nzero_page_oc);
221 PMAP_STATS_VAR(pmap_nzero_page_nc);
222 PMAP_STATS_VAR(pmap_nzero_page_area);
223 PMAP_STATS_VAR(pmap_nzero_page_area_c);
224 PMAP_STATS_VAR(pmap_nzero_page_area_oc);
225 PMAP_STATS_VAR(pmap_nzero_page_area_nc);
226 PMAP_STATS_VAR(pmap_ncopy_page);
227 PMAP_STATS_VAR(pmap_ncopy_page_c);
228 PMAP_STATS_VAR(pmap_ncopy_page_oc);
229 PMAP_STATS_VAR(pmap_ncopy_page_nc);
230 PMAP_STATS_VAR(pmap_ncopy_page_dc);
231 PMAP_STATS_VAR(pmap_ncopy_page_doc);
232 PMAP_STATS_VAR(pmap_ncopy_page_sc);
233 PMAP_STATS_VAR(pmap_ncopy_page_soc);
235 PMAP_STATS_VAR(pmap_nnew_thread);
236 PMAP_STATS_VAR(pmap_nnew_thread_oc);
238 static inline u_long dtlb_get_data(u_int tlb, u_int slot);
241 * Quick sort callout for comparing memory regions
243 static int mr_cmp(const void *a, const void *b);
244 static int om_cmp(const void *a, const void *b);
247 mr_cmp(const void *a, const void *b)
249 const struct ofw_mem_region *mra;
250 const struct ofw_mem_region *mrb;
254 if (mra->mr_start < mrb->mr_start)
256 else if (mra->mr_start > mrb->mr_start)
263 om_cmp(const void *a, const void *b)
265 const struct ofw_map *oma;
266 const struct ofw_map *omb;
270 if (oma->om_start < omb->om_start)
272 else if (oma->om_start > omb->om_start)
279 dtlb_get_data(u_int tlb, u_int slot)
284 slot = TLB_DAR_SLOT(tlb, slot);
286 * We read ASI_DTLB_DATA_ACCESS_REG twice back-to-back in order to
287 * work around errata of USIII and beyond.
290 (void)ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
291 data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
297 * Bootstrap the system enough to run with virtual memory.
300 pmap_bootstrap(u_int cpu_impl)
313 u_int dtlb_slots_avail;
322 * Set the kernel context.
326 colors = dcache_color_ignore != 0 ? 1 : DCACHE_COLORS;
329 * Find out what physical memory is available from the PROM and
330 * initialize the phys_avail array. This must be done before
331 * pmap_bootstrap_alloc is called.
333 if ((pmem = OF_finddevice("/memory")) == -1)
334 OF_panic("%s: finddevice /memory", __func__);
335 if ((sz = OF_getproplen(pmem, "available")) == -1)
336 OF_panic("%s: getproplen /memory/available", __func__);
337 if (sizeof(phys_avail) < sz)
338 OF_panic("%s: phys_avail too small", __func__);
339 if (sizeof(mra) < sz)
340 OF_panic("%s: mra too small", __func__);
342 if (OF_getprop(pmem, "available", mra, sz) == -1)
343 OF_panic("%s: getprop /memory/available", __func__);
346 OF_printf("pmap_bootstrap: physical memory\n");
348 qsort(mra, sz, sizeof (*mra), mr_cmp);
350 getenv_quad("hw.physmem", &physmem);
351 physmem = btoc(physmem);
352 for (i = 0, j = 0; i < sz; i++, j += 2) {
354 OF_printf("start=%#lx size=%#lx\n", mra[i].mr_start,
357 if (physmem != 0 && btoc(physsz + mra[i].mr_size) >= physmem) {
358 if (btoc(physsz) < physmem) {
359 phys_avail[j] = mra[i].mr_start;
360 phys_avail[j + 1] = mra[i].mr_start +
361 (ctob(physmem) - physsz);
362 physsz = ctob(physmem);
366 phys_avail[j] = mra[i].mr_start;
367 phys_avail[j + 1] = mra[i].mr_start + mra[i].mr_size;
368 physsz += mra[i].mr_size;
370 physmem = btoc(physsz);
373 * Calculate the size of kernel virtual memory, and the size and mask
374 * for the kernel TSB based on the phsyical memory size but limited
375 * by the amount of dTLB slots available for locked entries if we have
376 * to lock the TSB in the TLB (given that for spitfire-class CPUs all
377 * of the dt64 slots can hold locked entries but there is no large
378 * dTLB for unlocked ones, we don't use more than half of it for the
380 * Note that for reasons unknown OpenSolaris doesn't take advantage of
381 * ASI_ATOMIC_QUAD_LDD_PHYS on UltraSPARC-III. However, given that no
382 * public documentation is available for these, the latter just might
383 * not support it, yet.
385 if (cpu_impl == CPU_IMPL_SPARC64V ||
386 cpu_impl >= CPU_IMPL_ULTRASPARCIIIp) {
387 tsb_kernel_ldd_phys = 1;
388 virtsz = roundup(5 / 3 * physsz, PAGE_SIZE_4M <<
389 (PAGE_SHIFT - TTE_SHIFT));
391 dtlb_slots_avail = 0;
392 for (i = 0; i < dtlb_slots; i++) {
393 data = dtlb_get_data(cpu_impl ==
394 CPU_IMPL_ULTRASPARCIII ? TLB_DAR_T16 :
396 if ((data & (TD_V | TD_L)) != (TD_V | TD_L))
400 dtlb_slots_avail -= PCPU_PAGES;
402 if (cpu_impl >= CPU_IMPL_ULTRASPARCI &&
403 cpu_impl < CPU_IMPL_ULTRASPARCIII)
404 dtlb_slots_avail /= 2;
405 virtsz = roundup(physsz, PAGE_SIZE_4M <<
406 (PAGE_SHIFT - TTE_SHIFT));
407 virtsz = MIN(virtsz, (dtlb_slots_avail * PAGE_SIZE_4M) <<
408 (PAGE_SHIFT - TTE_SHIFT));
410 vm_max_kernel_address = VM_MIN_KERNEL_ADDRESS + virtsz;
411 tsb_kernel_size = virtsz >> (PAGE_SHIFT - TTE_SHIFT);
412 tsb_kernel_mask = (tsb_kernel_size >> TTE_SHIFT) - 1;
415 * Allocate the kernel TSB and lock it in the TLB if necessary.
417 pa = pmap_bootstrap_alloc(tsb_kernel_size, colors);
418 if (pa & PAGE_MASK_4M)
419 OF_panic("%s: TSB unaligned", __func__);
420 tsb_kernel_phys = pa;
421 if (tsb_kernel_ldd_phys == 0) {
423 (struct tte *)(VM_MIN_KERNEL_ADDRESS - tsb_kernel_size);
425 bzero(tsb_kernel, tsb_kernel_size);
428 (struct tte *)TLB_PHYS_TO_DIRECT(tsb_kernel_phys);
429 aszero(ASI_PHYS_USE_EC, tsb_kernel_phys, tsb_kernel_size);
433 * Allocate and map the dynamic per-CPU area for the BSP.
435 pa = pmap_bootstrap_alloc(DPCPU_SIZE, colors);
436 dpcpu0 = (void *)TLB_PHYS_TO_DIRECT(pa);
439 * Allocate and map the message buffer.
441 pa = pmap_bootstrap_alloc(msgbufsize, colors);
442 msgbufp = (struct msgbuf *)TLB_PHYS_TO_DIRECT(pa);
445 * Patch the TSB addresses and mask as well as the ASIs used to load
446 * it into the trap table.
449 #define LDDA_R_I_R(rd, imm_asi, rs1, rs2) \
450 (EIF_OP(IOP_LDST) | EIF_F3_RD(rd) | EIF_F3_OP3(INS3_LDDA) | \
451 EIF_F3_RS1(rs1) | EIF_F3_I(0) | EIF_F3_IMM_ASI(imm_asi) | \
453 #define OR_R_I_R(rd, imm13, rs1) \
454 (EIF_OP(IOP_MISC) | EIF_F3_RD(rd) | EIF_F3_OP3(INS2_OR) | \
455 EIF_F3_RS1(rs1) | EIF_F3_I(1) | EIF_IMM(imm13, 13))
456 #define SETHI(rd, imm22) \
457 (EIF_OP(IOP_FORM2) | EIF_F2_RD(rd) | EIF_F2_OP2(INS0_SETHI) | \
458 EIF_IMM((imm22) >> 10, 22))
459 #define WR_R_I(rd, imm13, rs1) \
460 (EIF_OP(IOP_MISC) | EIF_F3_RD(rd) | EIF_F3_OP3(INS2_WR) | \
461 EIF_F3_RS1(rs1) | EIF_F3_I(1) | EIF_IMM(imm13, 13))
463 #define PATCH_ASI(addr, asi) do { \
464 if (addr[0] != WR_R_I(IF_F3_RD(addr[0]), 0x0, \
465 IF_F3_RS1(addr[0]))) \
466 OF_panic("%s: patched instructions have changed", \
468 addr[0] |= EIF_IMM((asi), 13); \
472 #define PATCH_LDD(addr, asi) do { \
473 if (addr[0] != LDDA_R_I_R(IF_F3_RD(addr[0]), 0x0, \
474 IF_F3_RS1(addr[0]), IF_F3_RS2(addr[0]))) \
475 OF_panic("%s: patched instructions have changed", \
477 addr[0] |= EIF_F3_IMM_ASI(asi); \
481 #define PATCH_TSB(addr, val) do { \
482 if (addr[0] != SETHI(IF_F2_RD(addr[0]), 0x0) || \
483 addr[1] != OR_R_I_R(IF_F3_RD(addr[1]), 0x0, \
484 IF_F3_RS1(addr[1])) || \
485 addr[3] != SETHI(IF_F2_RD(addr[3]), 0x0)) \
486 OF_panic("%s: patched instructions have changed", \
488 addr[0] |= EIF_IMM((val) >> 42, 22); \
489 addr[1] |= EIF_IMM((val) >> 32, 10); \
490 addr[3] |= EIF_IMM((val) >> 10, 22); \
496 #define PATCH_TSB_MASK(addr, val) do { \
497 if (addr[0] != SETHI(IF_F2_RD(addr[0]), 0x0) || \
498 addr[1] != OR_R_I_R(IF_F3_RD(addr[1]), 0x0, \
499 IF_F3_RS1(addr[1]))) \
500 OF_panic("%s: patched instructions have changed", \
502 addr[0] |= EIF_IMM((val) >> 10, 22); \
503 addr[1] |= EIF_IMM((val), 10); \
508 if (tsb_kernel_ldd_phys == 0) {
510 ldd = ASI_NUCLEUS_QUAD_LDD;
511 off = (vm_offset_t)tsb_kernel;
513 asi = ASI_PHYS_USE_EC;
514 ldd = ASI_ATOMIC_QUAD_LDD_PHYS;
515 off = (vm_offset_t)tsb_kernel_phys;
517 PATCH_TSB(tl1_dmmu_miss_direct_patch_tsb_phys_1, tsb_kernel_phys);
518 PATCH_TSB(tl1_dmmu_miss_direct_patch_tsb_phys_end_1,
519 tsb_kernel_phys + tsb_kernel_size - 1);
520 PATCH_ASI(tl1_dmmu_miss_patch_asi_1, asi);
521 PATCH_LDD(tl1_dmmu_miss_patch_quad_ldd_1, ldd);
522 PATCH_TSB(tl1_dmmu_miss_patch_tsb_1, off);
523 PATCH_TSB(tl1_dmmu_miss_patch_tsb_2, off);
524 PATCH_TSB_MASK(tl1_dmmu_miss_patch_tsb_mask_1, tsb_kernel_mask);
525 PATCH_TSB_MASK(tl1_dmmu_miss_patch_tsb_mask_2, tsb_kernel_mask);
526 PATCH_ASI(tl1_dmmu_prot_patch_asi_1, asi);
527 PATCH_LDD(tl1_dmmu_prot_patch_quad_ldd_1, ldd);
528 PATCH_TSB(tl1_dmmu_prot_patch_tsb_1, off);
529 PATCH_TSB(tl1_dmmu_prot_patch_tsb_2, off);
530 PATCH_TSB_MASK(tl1_dmmu_prot_patch_tsb_mask_1, tsb_kernel_mask);
531 PATCH_TSB_MASK(tl1_dmmu_prot_patch_tsb_mask_2, tsb_kernel_mask);
532 PATCH_ASI(tl1_immu_miss_patch_asi_1, asi);
533 PATCH_LDD(tl1_immu_miss_patch_quad_ldd_1, ldd);
534 PATCH_TSB(tl1_immu_miss_patch_tsb_1, off);
535 PATCH_TSB(tl1_immu_miss_patch_tsb_2, off);
536 PATCH_TSB_MASK(tl1_immu_miss_patch_tsb_mask_1, tsb_kernel_mask);
537 PATCH_TSB_MASK(tl1_immu_miss_patch_tsb_mask_2, tsb_kernel_mask);
540 * Enter fake 8k pages for the 4MB kernel pages, so that
541 * pmap_kextract() will work for them.
543 for (i = 0; i < kernel_tlb_slots; i++) {
544 pa = kernel_tlbs[i].te_pa;
545 va = kernel_tlbs[i].te_va;
546 for (off = 0; off < PAGE_SIZE_4M; off += PAGE_SIZE) {
547 tp = tsb_kvtotte(va + off);
548 vpn = TV_VPN(va + off, TS_8K);
549 data = TD_V | TD_8K | TD_PA(pa + off) | TD_REF |
550 TD_SW | TD_CP | TD_CV | TD_P | TD_W;
551 pmap_bootstrap_set_tte(tp, vpn, data);
556 * Set the start and end of KVA. The kernel is loaded starting
557 * at the first available 4MB super page, so we advance to the
558 * end of the last one used for it.
560 virtual_avail = KERNBASE + kernel_tlb_slots * PAGE_SIZE_4M;
561 virtual_end = vm_max_kernel_address;
562 kernel_vm_end = vm_max_kernel_address;
565 * Allocate kva space for temporary mappings.
567 pmap_idle_map = virtual_avail;
568 virtual_avail += PAGE_SIZE * colors;
569 pmap_temp_map_1 = virtual_avail;
570 virtual_avail += PAGE_SIZE * colors;
571 pmap_temp_map_2 = virtual_avail;
572 virtual_avail += PAGE_SIZE * colors;
575 * Allocate a kernel stack with guard page for thread0 and map it
576 * into the kernel TSB. We must ensure that the virtual address is
577 * colored properly for corresponding CPUs, since we're allocating
578 * from phys_avail so the memory won't have an associated vm_page_t.
580 pa = pmap_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, colors);
582 virtual_avail += roundup(KSTACK_GUARD_PAGES, colors) * PAGE_SIZE;
583 kstack0 = virtual_avail;
584 virtual_avail += roundup(KSTACK_PAGES, colors) * PAGE_SIZE;
585 if (dcache_color_ignore == 0)
586 KASSERT(DCACHE_COLOR(kstack0) == DCACHE_COLOR(kstack0_phys),
587 ("pmap_bootstrap: kstack0 miscolored"));
588 for (i = 0; i < KSTACK_PAGES; i++) {
589 pa = kstack0_phys + i * PAGE_SIZE;
590 va = kstack0 + i * PAGE_SIZE;
591 tp = tsb_kvtotte(va);
592 vpn = TV_VPN(va, TS_8K);
593 data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_SW | TD_CP |
595 pmap_bootstrap_set_tte(tp, vpn, data);
599 * Calculate the last available physical address.
601 for (i = 0; phys_avail[i + 2] != 0; i += 2)
603 Maxmem = sparc64_btop(phys_avail[i + 1]);
606 * Add the PROM mappings to the kernel TSB.
608 if ((vmem = OF_finddevice("/virtual-memory")) == -1)
609 OF_panic("%s: finddevice /virtual-memory", __func__);
610 if ((sz = OF_getproplen(vmem, "translations")) == -1)
611 OF_panic("%s: getproplen translations", __func__);
612 if (sizeof(translations) < sz)
613 OF_panic("%s: translations too small", __func__);
614 bzero(translations, sz);
615 if (OF_getprop(vmem, "translations", translations, sz) == -1)
616 OF_panic("%s: getprop /virtual-memory/translations",
618 sz /= sizeof(*translations);
619 translations_size = sz;
621 OF_printf("pmap_bootstrap: translations\n");
623 qsort(translations, sz, sizeof (*translations), om_cmp);
624 for (i = 0; i < sz; i++) {
626 OF_printf("translation: start=%#lx size=%#lx tte=%#lx\n",
627 translations[i].om_start, translations[i].om_size,
628 translations[i].om_tte);
630 if ((translations[i].om_tte & TD_V) == 0)
632 if (translations[i].om_start < VM_MIN_PROM_ADDRESS ||
633 translations[i].om_start > VM_MAX_PROM_ADDRESS)
635 for (off = 0; off < translations[i].om_size;
637 va = translations[i].om_start + off;
638 tp = tsb_kvtotte(va);
639 vpn = TV_VPN(va, TS_8K);
640 data = ((translations[i].om_tte &
641 ~((TD_SOFT2_MASK << TD_SOFT2_SHIFT) |
642 (cpu_impl >= CPU_IMPL_ULTRASPARCI &&
643 cpu_impl < CPU_IMPL_ULTRASPARCIII ?
644 (TD_DIAG_SF_MASK << TD_DIAG_SF_SHIFT) :
645 (TD_RSVD_CH_MASK << TD_RSVD_CH_SHIFT)) |
646 (TD_SOFT_MASK << TD_SOFT_SHIFT))) | TD_EXEC) +
648 pmap_bootstrap_set_tte(tp, vpn, data);
653 * Get the available physical memory ranges from /memory/reg. These
654 * are only used for kernel dumps, but it may not be wise to do PROM
655 * calls in that situation.
657 if ((sz = OF_getproplen(pmem, "reg")) == -1)
658 OF_panic("%s: getproplen /memory/reg", __func__);
659 if (sizeof(sparc64_memreg) < sz)
660 OF_panic("%s: sparc64_memreg too small", __func__);
661 if (OF_getprop(pmem, "reg", sparc64_memreg, sz) == -1)
662 OF_panic("%s: getprop /memory/reg", __func__);
663 sparc64_nmemreg = sz / sizeof(*sparc64_memreg);
666 * Initialize the kernel pmap (which is statically allocated).
670 for (i = 0; i < MAXCPU; i++)
671 pm->pm_context[i] = TLB_CTX_KERNEL;
672 CPU_FILL(&pm->pm_active);
675 * Initialize the global tte list lock, which is more commonly
676 * known as the pmap pv global lock.
678 rw_init(&tte_list_global_lock, "pmap pv global");
681 * Flush all non-locked TLB entries possibly left over by the
684 tlb_flush_nonlocked();
688 pmap_init_qpages(void)
693 if (dcache_color_ignore != 0)
698 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE * DCACHE_COLORS);
699 if (pc->pc_qmap_addr == 0)
700 panic("pmap_init_qpages: unable to allocate KVA");
704 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_qpages, NULL);
707 * Map the 4MB kernel TSB pages.
717 for (i = 0; i < tsb_kernel_size; i += PAGE_SIZE_4M) {
718 va = (vm_offset_t)tsb_kernel + i;
719 pa = tsb_kernel_phys + i;
720 data = TD_V | TD_4M | TD_PA(pa) | TD_L | TD_CP | TD_CV |
722 stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) |
723 TLB_TAR_CTX(TLB_CTX_KERNEL));
724 stxa_sync(0, ASI_DTLB_DATA_IN_REG, data);
729 * Set the secondary context to be the kernel context (needed for FP block
730 * operations in the kernel).
736 stxa(AA_DMMU_SCXR, ASI_DMMU, (ldxa(AA_DMMU_SCXR, ASI_DMMU) &
737 TLB_CXR_PGSZ_MASK) | TLB_CTX_KERNEL);
742 * Allocate a physical page of memory directly from the phys_avail map.
743 * Can only be called from pmap_bootstrap before avail start and end are
747 pmap_bootstrap_alloc(vm_size_t size, uint32_t colors)
752 size = roundup(size, PAGE_SIZE * colors);
753 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
754 if (phys_avail[i + 1] - phys_avail[i] < size)
757 phys_avail[i] += size;
760 OF_panic("%s: no suitable region found", __func__);
764 * Set a TTE. This function is intended as a helper when tsb_kernel is
765 * direct-mapped but we haven't taken over the trap table, yet, as it's the
766 * case when we are taking advantage of ASI_ATOMIC_QUAD_LDD_PHYS to access
770 pmap_bootstrap_set_tte(struct tte *tp, u_long vpn, u_long data)
773 if (tsb_kernel_ldd_phys == 0) {
777 stxa((vm_paddr_t)tp + offsetof(struct tte, tte_vpn),
778 ASI_PHYS_USE_EC, vpn);
779 stxa((vm_paddr_t)tp + offsetof(struct tte, tte_data),
780 ASI_PHYS_USE_EC, data);
785 * Initialize a vm_page's machine-dependent fields.
788 pmap_page_init(vm_page_t m)
791 TAILQ_INIT(&m->md.tte_list);
792 m->md.color = DCACHE_COLOR(VM_PAGE_TO_PHYS(m));
797 * Initialize the pmap module.
807 for (i = 0; i < translations_size; i++) {
808 addr = translations[i].om_start;
809 size = translations[i].om_size;
810 if ((translations[i].om_tte & TD_V) == 0)
812 if (addr < VM_MIN_PROM_ADDRESS || addr > VM_MAX_PROM_ADDRESS)
814 result = vm_map_find(kernel_map, NULL, 0, &addr, size, 0,
815 VMFS_NO_SPACE, VM_PROT_ALL, VM_PROT_ALL, MAP_NOFAULT);
816 if (result != KERN_SUCCESS || addr != translations[i].om_start)
817 panic("pmap_init: vm_map_find");
822 * Extract the physical page address associated with the given
823 * map/virtual_address pair.
826 pmap_extract(pmap_t pm, vm_offset_t va)
831 if (pm == kernel_pmap)
832 return (pmap_kextract(va));
834 tp = tsb_tte_lookup(pm, va);
838 pa = TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp));
844 * Atomically extract and hold the physical page with the given
845 * pmap and virtual address pair if that mapping permits the given
849 pmap_extract_and_hold(pmap_t pm, vm_offset_t va, vm_prot_t prot)
859 if (pm == kernel_pmap) {
860 if (va >= VM_MIN_DIRECT_ADDRESS) {
862 m = PHYS_TO_VM_PAGE(TLB_DIRECT_TO_PHYS(va));
863 (void)vm_page_pa_tryrelock(pm, TLB_DIRECT_TO_PHYS(va),
867 tp = tsb_kvtotte(va);
868 if ((tp->tte_data & TD_V) == 0)
872 tp = tsb_tte_lookup(pm, va);
873 if (tp != NULL && ((tp->tte_data & TD_SW) ||
874 (prot & VM_PROT_WRITE) == 0)) {
875 if (vm_page_pa_tryrelock(pm, TTE_GET_PA(tp), &pa))
877 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
886 * Extract the physical page address associated with the given kernel virtual
890 pmap_kextract(vm_offset_t va)
894 if (va >= VM_MIN_DIRECT_ADDRESS)
895 return (TLB_DIRECT_TO_PHYS(va));
896 tp = tsb_kvtotte(va);
897 if ((tp->tte_data & TD_V) == 0)
899 return (TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp)));
903 pmap_cache_enter(vm_page_t m, vm_offset_t va)
908 rw_assert(&tte_list_global_lock, RA_WLOCKED);
909 KASSERT((m->flags & PG_FICTITIOUS) == 0,
910 ("pmap_cache_enter: fake page"));
911 PMAP_STATS_INC(pmap_ncache_enter);
913 if (dcache_color_ignore != 0)
917 * Find the color for this virtual address and note the added mapping.
919 color = DCACHE_COLOR(va);
920 m->md.colors[color]++;
923 * If all existing mappings have the same color, the mapping is
926 if (m->md.color == color) {
927 KASSERT(m->md.colors[DCACHE_OTHER_COLOR(color)] == 0,
928 ("pmap_cache_enter: cacheable, mappings of other color"));
929 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
930 PMAP_STATS_INC(pmap_ncache_enter_c);
932 PMAP_STATS_INC(pmap_ncache_enter_oc);
937 * If there are no mappings of the other color, and the page still has
938 * the wrong color, this must be a new mapping. Change the color to
939 * match the new mapping, which is cacheable. We must flush the page
940 * from the cache now.
942 if (m->md.colors[DCACHE_OTHER_COLOR(color)] == 0) {
943 KASSERT(m->md.colors[color] == 1,
944 ("pmap_cache_enter: changing color, not new mapping"));
945 dcache_page_inval(VM_PAGE_TO_PHYS(m));
947 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
948 PMAP_STATS_INC(pmap_ncache_enter_cc);
950 PMAP_STATS_INC(pmap_ncache_enter_coc);
955 * If the mapping is already non-cacheable, just return.
957 if (m->md.color == -1) {
958 PMAP_STATS_INC(pmap_ncache_enter_nc);
962 PMAP_STATS_INC(pmap_ncache_enter_cnc);
965 * Mark all mappings as uncacheable, flush any lines with the other
966 * color out of the dcache, and set the color to none (-1).
968 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
969 atomic_clear_long(&tp->tte_data, TD_CV);
970 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
972 dcache_page_inval(VM_PAGE_TO_PHYS(m));
978 pmap_cache_remove(vm_page_t m, vm_offset_t va)
983 rw_assert(&tte_list_global_lock, RA_WLOCKED);
984 CTR3(KTR_PMAP, "pmap_cache_remove: m=%p va=%#lx c=%d", m, va,
985 m->md.colors[DCACHE_COLOR(va)]);
986 KASSERT((m->flags & PG_FICTITIOUS) == 0,
987 ("pmap_cache_remove: fake page"));
988 PMAP_STATS_INC(pmap_ncache_remove);
990 if (dcache_color_ignore != 0)
993 KASSERT(m->md.colors[DCACHE_COLOR(va)] > 0,
994 ("pmap_cache_remove: no mappings %d <= 0",
995 m->md.colors[DCACHE_COLOR(va)]));
998 * Find the color for this virtual address and note the removal of
1001 color = DCACHE_COLOR(va);
1002 m->md.colors[color]--;
1005 * If the page is cacheable, just return and keep the same color, even
1006 * if there are no longer any mappings.
1008 if (m->md.color != -1) {
1009 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
1010 PMAP_STATS_INC(pmap_ncache_remove_c);
1012 PMAP_STATS_INC(pmap_ncache_remove_oc);
1016 KASSERT(m->md.colors[DCACHE_OTHER_COLOR(color)] != 0,
1017 ("pmap_cache_remove: uncacheable, no mappings of other color"));
1020 * If the page is not cacheable (color is -1), and the number of
1021 * mappings for this color is not zero, just return. There are
1022 * mappings of the other color still, so remain non-cacheable.
1024 if (m->md.colors[color] != 0) {
1025 PMAP_STATS_INC(pmap_ncache_remove_nc);
1030 * The number of mappings for this color is now zero. Recache the
1031 * other colored mappings, and change the page color to the other
1032 * color. There should be no lines in the data cache for this page,
1033 * so flushing should not be needed.
1035 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1036 atomic_set_long(&tp->tte_data, TD_CV);
1037 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1039 m->md.color = DCACHE_OTHER_COLOR(color);
1041 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
1042 PMAP_STATS_INC(pmap_ncache_remove_cc);
1044 PMAP_STATS_INC(pmap_ncache_remove_coc);
1048 * Map a wired page into kernel virtual address space.
1051 pmap_kenter(vm_offset_t va, vm_page_t m)
1058 rw_assert(&tte_list_global_lock, RA_WLOCKED);
1059 PMAP_STATS_INC(pmap_nkenter);
1060 tp = tsb_kvtotte(va);
1061 CTR4(KTR_PMAP, "pmap_kenter: va=%#lx pa=%#lx tp=%p data=%#lx",
1062 va, VM_PAGE_TO_PHYS(m), tp, tp->tte_data);
1063 if (DCACHE_COLOR(VM_PAGE_TO_PHYS(m)) != DCACHE_COLOR(va)) {
1065 "pmap_kenter: off color va=%#lx pa=%#lx o=%p ot=%d pi=%#lx",
1066 va, VM_PAGE_TO_PHYS(m), m->object,
1067 m->object ? m->object->type : -1,
1069 PMAP_STATS_INC(pmap_nkenter_oc);
1071 if ((tp->tte_data & TD_V) != 0) {
1072 om = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
1073 ova = TTE_GET_VA(tp);
1074 if (m == om && va == ova) {
1075 PMAP_STATS_INC(pmap_nkenter_stupid);
1078 TAILQ_REMOVE(&om->md.tte_list, tp, tte_link);
1079 pmap_cache_remove(om, ova);
1081 tlb_page_demap(kernel_pmap, ova);
1083 data = TD_V | TD_8K | VM_PAGE_TO_PHYS(m) | TD_REF | TD_SW | TD_CP |
1085 if (pmap_cache_enter(m, va) != 0)
1087 tp->tte_vpn = TV_VPN(va, TS_8K);
1088 tp->tte_data = data;
1089 TAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link);
1093 * Map a wired page into kernel virtual address space. This additionally
1094 * takes a flag argument which is or'ed to the TTE data. This is used by
1095 * sparc64_bus_mem_map().
1096 * NOTE: if the mapping is non-cacheable, it's the caller's responsibility
1097 * to flush entries that might still be in the cache, if applicable.
1100 pmap_kenter_flags(vm_offset_t va, vm_paddr_t pa, u_long flags)
1104 tp = tsb_kvtotte(va);
1105 CTR4(KTR_PMAP, "pmap_kenter_flags: va=%#lx pa=%#lx tp=%p data=%#lx",
1106 va, pa, tp, tp->tte_data);
1107 tp->tte_vpn = TV_VPN(va, TS_8K);
1108 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_P | flags;
1112 * Remove a wired page from kernel virtual address space.
1115 pmap_kremove(vm_offset_t va)
1120 rw_assert(&tte_list_global_lock, RA_WLOCKED);
1121 PMAP_STATS_INC(pmap_nkremove);
1122 tp = tsb_kvtotte(va);
1123 CTR3(KTR_PMAP, "pmap_kremove: va=%#lx tp=%p data=%#lx", va, tp,
1125 if ((tp->tte_data & TD_V) == 0)
1127 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
1128 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1129 pmap_cache_remove(m, va);
1134 * Inverse of pmap_kenter_flags, used by bus_space_unmap().
1137 pmap_kremove_flags(vm_offset_t va)
1141 tp = tsb_kvtotte(va);
1142 CTR3(KTR_PMAP, "pmap_kremove_flags: va=%#lx tp=%p data=%#lx", va, tp,
1148 * Map a range of physical addresses into kernel virtual address space.
1150 * The value passed in *virt is a suggested virtual address for the mapping.
1151 * Architectures which can support a direct-mapped physical to virtual region
1152 * can return the appropriate address within that region, leaving '*virt'
1156 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1159 return (TLB_PHYS_TO_DIRECT(start));
1163 * Map a list of wired pages into kernel virtual address space. This is
1164 * intended for temporary mappings which do not need page modification or
1165 * references recorded. Existing mappings in the region are overwritten.
1168 pmap_qenter(vm_offset_t sva, vm_page_t *m, int count)
1172 PMAP_STATS_INC(pmap_nqenter);
1174 rw_wlock(&tte_list_global_lock);
1175 while (count-- > 0) {
1176 pmap_kenter(va, *m);
1180 rw_wunlock(&tte_list_global_lock);
1181 tlb_range_demap(kernel_pmap, sva, va);
1185 * Remove page mappings from kernel virtual address space. Intended for
1186 * temporary mappings entered by pmap_qenter.
1189 pmap_qremove(vm_offset_t sva, int count)
1193 PMAP_STATS_INC(pmap_nqremove);
1195 rw_wlock(&tte_list_global_lock);
1196 while (count-- > 0) {
1200 rw_wunlock(&tte_list_global_lock);
1201 tlb_range_demap(kernel_pmap, sva, va);
1205 * Initialize the pmap associated with process 0.
1208 pmap_pinit0(pmap_t pm)
1213 for (i = 0; i < MAXCPU; i++)
1214 pm->pm_context[i] = TLB_CTX_KERNEL;
1215 CPU_ZERO(&pm->pm_active);
1217 pm->pm_tsb_obj = NULL;
1218 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1222 * Initialize a preallocated and zeroed pmap structure, such as one in a
1223 * vmspace structure.
1226 pmap_pinit(pmap_t pm)
1228 vm_page_t ma[TSB_PAGES];
1232 * Allocate KVA space for the TSB.
1234 if (pm->pm_tsb == NULL) {
1235 pm->pm_tsb = (struct tte *)kva_alloc(TSB_BSIZE);
1236 if (pm->pm_tsb == NULL)
1241 * Allocate an object for it.
1243 if (pm->pm_tsb_obj == NULL)
1244 pm->pm_tsb_obj = vm_object_allocate(OBJT_PHYS, TSB_PAGES);
1246 for (i = 0; i < MAXCPU; i++)
1247 pm->pm_context[i] = -1;
1248 CPU_ZERO(&pm->pm_active);
1250 VM_OBJECT_WLOCK(pm->pm_tsb_obj);
1251 (void)vm_page_grab_pages(pm->pm_tsb_obj, 0, VM_ALLOC_NORMAL |
1252 VM_ALLOC_NOBUSY | VM_ALLOC_WIRED | VM_ALLOC_ZERO, ma, TSB_PAGES);
1253 VM_OBJECT_WUNLOCK(pm->pm_tsb_obj);
1254 for (i = 0; i < TSB_PAGES; i++)
1255 ma[i]->md.pmap = pm;
1256 pmap_qenter((vm_offset_t)pm->pm_tsb, ma, TSB_PAGES);
1258 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1263 * Release any resources held by the given physical map.
1264 * Called when a pmap initialized by pmap_pinit is being released.
1265 * Should only be called if the map contains no valid mappings.
1268 pmap_release(pmap_t pm)
1276 CTR2(KTR_PMAP, "pmap_release: ctx=%#x tsb=%p",
1277 pm->pm_context[curcpu], pm->pm_tsb);
1278 KASSERT(pmap_resident_count(pm) == 0,
1279 ("pmap_release: resident pages %ld != 0",
1280 pmap_resident_count(pm)));
1283 * After the pmap was freed, it might be reallocated to a new process.
1284 * When switching, this might lead us to wrongly assume that we need
1285 * not switch contexts because old and new pmap pointer are equal.
1286 * Therefore, make sure that this pmap is not referenced by any PCPU
1287 * pointer any more. This could happen in two cases:
1288 * - A process that referenced the pmap is currently exiting on a CPU.
1289 * However, it is guaranteed to not switch in any more after setting
1290 * its state to PRS_ZOMBIE.
1291 * - A process that referenced this pmap ran on a CPU, but we switched
1292 * to a kernel thread, leaving the pmap pointer unchanged.
1296 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu)
1297 atomic_cmpset_rel_ptr((uintptr_t *)&pc->pc_pmap,
1298 (uintptr_t)pm, (uintptr_t)NULL);
1302 if (PCPU_GET(pmap) == pm)
1303 PCPU_SET(pmap, NULL);
1307 pmap_qremove((vm_offset_t)pm->pm_tsb, TSB_PAGES);
1308 obj = pm->pm_tsb_obj;
1309 VM_OBJECT_WLOCK(obj);
1310 KASSERT(obj->ref_count == 1, ("pmap_release: tsbobj ref count != 1"));
1311 while (!TAILQ_EMPTY(&obj->memq)) {
1312 m = TAILQ_FIRST(&obj->memq);
1315 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1316 vm_page_free_zero(m);
1318 VM_OBJECT_WUNLOCK(obj);
1322 * Grow the number of kernel page table entries. Unneeded.
1325 pmap_growkernel(vm_offset_t addr)
1328 panic("pmap_growkernel: can't grow kernel");
1332 pmap_remove_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp,
1338 rw_assert(&tte_list_global_lock, RA_WLOCKED);
1339 data = atomic_readandclear_long(&tp->tte_data);
1340 if ((data & TD_FAKE) == 0) {
1341 m = PHYS_TO_VM_PAGE(TD_PA(data));
1342 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1343 if ((data & TD_WIRED) != 0)
1344 pm->pm_stats.wired_count--;
1345 if ((data & TD_PV) != 0) {
1346 if ((data & TD_W) != 0)
1348 if ((data & TD_REF) != 0)
1349 vm_page_aflag_set(m, PGA_REFERENCED);
1350 if (TAILQ_EMPTY(&m->md.tte_list))
1351 vm_page_aflag_clear(m, PGA_WRITEABLE);
1352 pm->pm_stats.resident_count--;
1354 pmap_cache_remove(m, va);
1357 if (PMAP_REMOVE_DONE(pm))
1363 * Remove the given range of addresses from the specified map.
1366 pmap_remove(pmap_t pm, vm_offset_t start, vm_offset_t end)
1371 CTR3(KTR_PMAP, "pmap_remove: ctx=%#lx start=%#lx end=%#lx",
1372 pm->pm_context[curcpu], start, end);
1373 if (PMAP_REMOVE_DONE(pm))
1375 rw_wlock(&tte_list_global_lock);
1377 if (end - start > PMAP_TSB_THRESH) {
1378 tsb_foreach(pm, NULL, start, end, pmap_remove_tte);
1379 tlb_context_demap(pm);
1381 for (va = start; va < end; va += PAGE_SIZE)
1382 if ((tp = tsb_tte_lookup(pm, va)) != NULL &&
1383 !pmap_remove_tte(pm, NULL, tp, va))
1385 tlb_range_demap(pm, start, end - 1);
1388 rw_wunlock(&tte_list_global_lock);
1392 pmap_remove_all(vm_page_t m)
1399 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1400 ("pmap_remove_all: page %p is not managed", m));
1401 rw_wlock(&tte_list_global_lock);
1402 for (tp = TAILQ_FIRST(&m->md.tte_list); tp != NULL; tp = tpn) {
1403 tpn = TAILQ_NEXT(tp, tte_link);
1404 if ((tp->tte_data & TD_PV) == 0)
1406 pm = TTE_GET_PMAP(tp);
1407 va = TTE_GET_VA(tp);
1409 if ((tp->tte_data & TD_WIRED) != 0)
1410 pm->pm_stats.wired_count--;
1411 if ((tp->tte_data & TD_REF) != 0)
1412 vm_page_aflag_set(m, PGA_REFERENCED);
1413 if ((tp->tte_data & TD_W) != 0)
1415 tp->tte_data &= ~TD_V;
1416 tlb_page_demap(pm, va);
1417 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1418 pm->pm_stats.resident_count--;
1419 pmap_cache_remove(m, va);
1423 vm_page_aflag_clear(m, PGA_WRITEABLE);
1424 rw_wunlock(&tte_list_global_lock);
1428 pmap_protect_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp,
1434 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1435 data = atomic_clear_long(&tp->tte_data, TD_SW | TD_W);
1436 if ((data & (TD_PV | TD_W)) == (TD_PV | TD_W)) {
1437 m = PHYS_TO_VM_PAGE(TD_PA(data));
1444 * Set the physical protection on the specified range of this map as requested.
1447 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
1452 CTR4(KTR_PMAP, "pmap_protect: ctx=%#lx sva=%#lx eva=%#lx prot=%#lx",
1453 pm->pm_context[curcpu], sva, eva, prot);
1455 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1456 pmap_remove(pm, sva, eva);
1460 if (prot & VM_PROT_WRITE)
1464 if (eva - sva > PMAP_TSB_THRESH) {
1465 tsb_foreach(pm, NULL, sva, eva, pmap_protect_tte);
1466 tlb_context_demap(pm);
1468 for (va = sva; va < eva; va += PAGE_SIZE)
1469 if ((tp = tsb_tte_lookup(pm, va)) != NULL)
1470 pmap_protect_tte(pm, NULL, tp, va);
1471 tlb_range_demap(pm, sva, eva - 1);
1477 * Map the given physical page at the specified virtual address in the
1478 * target pmap with the protection requested. If specified the page
1479 * will be wired down.
1482 pmap_enter(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1483 u_int flags, int8_t psind)
1487 rw_wlock(&tte_list_global_lock);
1489 rv = pmap_enter_locked(pm, va, m, prot, flags, psind);
1490 rw_wunlock(&tte_list_global_lock);
1496 * Map the given physical page at the specified virtual address in the
1497 * target pmap with the protection requested. If specified the page
1498 * will be wired down.
1500 * The page queues and pmap must be locked.
1503 pmap_enter_locked(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1504 u_int flags, int8_t psind __unused)
1512 rw_assert(&tte_list_global_lock, RA_WLOCKED);
1513 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1514 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1515 VM_OBJECT_ASSERT_LOCKED(m->object);
1516 PMAP_STATS_INC(pmap_nenter);
1517 pa = VM_PAGE_TO_PHYS(m);
1518 wired = (flags & PMAP_ENTER_WIRED) != 0;
1521 * If this is a fake page from the device_pager, but it covers actual
1522 * physical memory, convert to the real backing page.
1524 if ((m->flags & PG_FICTITIOUS) != 0) {
1525 real = vm_phys_paddr_to_vm_page(pa);
1531 "pmap_enter_locked: ctx=%p m=%p va=%#lx pa=%#lx prot=%#x wired=%d",
1532 pm->pm_context[curcpu], m, va, pa, prot, wired);
1535 * If there is an existing mapping, and the physical address has not
1536 * changed, must be protection or wiring change.
1538 if ((tp = tsb_tte_lookup(pm, va)) != NULL && TTE_GET_PA(tp) == pa) {
1539 CTR0(KTR_PMAP, "pmap_enter_locked: update");
1540 PMAP_STATS_INC(pmap_nenter_update);
1543 * Wiring change, just update stats.
1546 if ((tp->tte_data & TD_WIRED) == 0) {
1547 tp->tte_data |= TD_WIRED;
1548 pm->pm_stats.wired_count++;
1551 if ((tp->tte_data & TD_WIRED) != 0) {
1552 tp->tte_data &= ~TD_WIRED;
1553 pm->pm_stats.wired_count--;
1558 * Save the old bits and clear the ones we're interested in.
1560 data = tp->tte_data;
1561 tp->tte_data &= ~(TD_EXEC | TD_SW | TD_W);
1564 * If we're turning off write permissions, sense modify status.
1566 if ((prot & VM_PROT_WRITE) != 0) {
1567 tp->tte_data |= TD_SW;
1569 tp->tte_data |= TD_W;
1570 if ((m->oflags & VPO_UNMANAGED) == 0)
1571 vm_page_aflag_set(m, PGA_WRITEABLE);
1572 } else if ((data & TD_W) != 0)
1576 * If we're turning on execute permissions, flush the icache.
1578 if ((prot & VM_PROT_EXECUTE) != 0) {
1579 if ((data & TD_EXEC) == 0)
1580 icache_page_inval(pa);
1581 tp->tte_data |= TD_EXEC;
1585 * Delete the old mapping.
1587 tlb_page_demap(pm, TTE_GET_VA(tp));
1590 * If there is an existing mapping, but its for a different
1591 * physical address, delete the old mapping.
1594 CTR0(KTR_PMAP, "pmap_enter_locked: replace");
1595 PMAP_STATS_INC(pmap_nenter_replace);
1596 pmap_remove_tte(pm, NULL, tp, va);
1597 tlb_page_demap(pm, va);
1599 CTR0(KTR_PMAP, "pmap_enter_locked: new");
1600 PMAP_STATS_INC(pmap_nenter_new);
1604 * Now set up the data and install the new mapping.
1606 data = TD_V | TD_8K | TD_PA(pa);
1607 if (pm == kernel_pmap)
1609 if ((prot & VM_PROT_WRITE) != 0) {
1611 if ((m->oflags & VPO_UNMANAGED) == 0)
1612 vm_page_aflag_set(m, PGA_WRITEABLE);
1614 if (prot & VM_PROT_EXECUTE) {
1616 icache_page_inval(pa);
1620 * If its wired update stats. We also don't need reference or
1621 * modify tracking for wired mappings, so set the bits now.
1624 pm->pm_stats.wired_count++;
1625 data |= TD_REF | TD_WIRED;
1626 if ((prot & VM_PROT_WRITE) != 0)
1630 tsb_tte_enter(pm, m, va, TS_8K, data);
1633 return (KERN_SUCCESS);
1637 * Maps a sequence of resident pages belonging to the same object.
1638 * The sequence begins with the given page m_start. This page is
1639 * mapped at the given virtual address start. Each subsequent page is
1640 * mapped at a virtual address that is offset from start by the same
1641 * amount as the page is offset from m_start within the object. The
1642 * last page in the sequence is the page with the largest offset from
1643 * m_start that can be mapped at a virtual address less than the given
1644 * virtual address end. Not every virtual page between start and end
1645 * is mapped; only those for which a resident page exists with the
1646 * corresponding offset from m_start are mapped.
1649 pmap_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end,
1650 vm_page_t m_start, vm_prot_t prot)
1653 vm_pindex_t diff, psize;
1655 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1657 psize = atop(end - start);
1659 rw_wlock(&tte_list_global_lock);
1661 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1662 pmap_enter_locked(pm, start + ptoa(diff), m, prot &
1663 (VM_PROT_READ | VM_PROT_EXECUTE), 0, 0);
1664 m = TAILQ_NEXT(m, listq);
1666 rw_wunlock(&tte_list_global_lock);
1671 pmap_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot)
1674 rw_wlock(&tte_list_global_lock);
1676 pmap_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1678 rw_wunlock(&tte_list_global_lock);
1683 pmap_object_init_pt(pmap_t pm, vm_offset_t addr, vm_object_t object,
1684 vm_pindex_t pindex, vm_size_t size)
1687 VM_OBJECT_ASSERT_WLOCKED(object);
1688 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
1689 ("pmap_object_init_pt: non-device object"));
1693 pmap_unwire_tte(pmap_t pm, pmap_t pm2, struct tte *tp, vm_offset_t va)
1696 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1697 if ((tp->tte_data & TD_WIRED) == 0)
1698 panic("pmap_unwire_tte: tp %p is missing TD_WIRED", tp);
1699 atomic_clear_long(&tp->tte_data, TD_WIRED);
1700 pm->pm_stats.wired_count--;
1705 * Clear the wired attribute from the mappings for the specified range of
1706 * addresses in the given pmap. Every valid mapping within that range must
1707 * have the wired attribute set. In contrast, invalid mappings cannot have
1708 * the wired attribute set, so they are ignored.
1710 * The wired attribute of the translation table entry is not a hardware
1711 * feature, so there is no need to invalidate any TLB entries.
1714 pmap_unwire(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1720 if (eva - sva > PMAP_TSB_THRESH)
1721 tsb_foreach(pm, NULL, sva, eva, pmap_unwire_tte);
1723 for (va = sva; va < eva; va += PAGE_SIZE)
1724 if ((tp = tsb_tte_lookup(pm, va)) != NULL)
1725 pmap_unwire_tte(pm, NULL, tp, va);
1731 pmap_copy_tte(pmap_t src_pmap, pmap_t dst_pmap, struct tte *tp,
1737 if ((tp->tte_data & TD_FAKE) != 0)
1739 if (tsb_tte_lookup(dst_pmap, va) == NULL) {
1740 data = tp->tte_data &
1741 ~(TD_PV | TD_REF | TD_SW | TD_CV | TD_W);
1742 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
1743 tsb_tte_enter(dst_pmap, m, va, TS_8K, data);
1749 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
1750 vm_size_t len, vm_offset_t src_addr)
1755 if (dst_addr != src_addr)
1757 rw_wlock(&tte_list_global_lock);
1758 if (dst_pmap < src_pmap) {
1759 PMAP_LOCK(dst_pmap);
1760 PMAP_LOCK(src_pmap);
1762 PMAP_LOCK(src_pmap);
1763 PMAP_LOCK(dst_pmap);
1765 if (len > PMAP_TSB_THRESH) {
1766 tsb_foreach(src_pmap, dst_pmap, src_addr, src_addr + len,
1768 tlb_context_demap(dst_pmap);
1770 for (va = src_addr; va < src_addr + len; va += PAGE_SIZE)
1771 if ((tp = tsb_tte_lookup(src_pmap, va)) != NULL)
1772 pmap_copy_tte(src_pmap, dst_pmap, tp, va);
1773 tlb_range_demap(dst_pmap, src_addr, src_addr + len - 1);
1775 rw_wunlock(&tte_list_global_lock);
1776 PMAP_UNLOCK(src_pmap);
1777 PMAP_UNLOCK(dst_pmap);
1781 pmap_zero_page(vm_page_t m)
1787 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1788 ("pmap_zero_page: fake page"));
1789 PMAP_STATS_INC(pmap_nzero_page);
1790 pa = VM_PAGE_TO_PHYS(m);
1791 if (dcache_color_ignore != 0 || m->md.color == DCACHE_COLOR(pa)) {
1792 PMAP_STATS_INC(pmap_nzero_page_c);
1793 va = TLB_PHYS_TO_DIRECT(pa);
1794 cpu_block_zero((void *)va, PAGE_SIZE);
1795 } else if (m->md.color == -1) {
1796 PMAP_STATS_INC(pmap_nzero_page_nc);
1797 aszero(ASI_PHYS_USE_EC, pa, PAGE_SIZE);
1799 PMAP_STATS_INC(pmap_nzero_page_oc);
1800 PMAP_LOCK(kernel_pmap);
1801 va = pmap_temp_map_1 + (m->md.color * PAGE_SIZE);
1802 tp = tsb_kvtotte(va);
1803 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1804 tp->tte_vpn = TV_VPN(va, TS_8K);
1805 cpu_block_zero((void *)va, PAGE_SIZE);
1806 tlb_page_demap(kernel_pmap, va);
1807 PMAP_UNLOCK(kernel_pmap);
1812 pmap_zero_page_area(vm_page_t m, int off, int size)
1818 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1819 ("pmap_zero_page_area: fake page"));
1820 KASSERT(off + size <= PAGE_SIZE, ("pmap_zero_page_area: bad off/size"));
1821 PMAP_STATS_INC(pmap_nzero_page_area);
1822 pa = VM_PAGE_TO_PHYS(m);
1823 if (dcache_color_ignore != 0 || m->md.color == DCACHE_COLOR(pa)) {
1824 PMAP_STATS_INC(pmap_nzero_page_area_c);
1825 va = TLB_PHYS_TO_DIRECT(pa);
1826 bzero((void *)(va + off), size);
1827 } else if (m->md.color == -1) {
1828 PMAP_STATS_INC(pmap_nzero_page_area_nc);
1829 aszero(ASI_PHYS_USE_EC, pa + off, size);
1831 PMAP_STATS_INC(pmap_nzero_page_area_oc);
1832 PMAP_LOCK(kernel_pmap);
1833 va = pmap_temp_map_1 + (m->md.color * PAGE_SIZE);
1834 tp = tsb_kvtotte(va);
1835 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1836 tp->tte_vpn = TV_VPN(va, TS_8K);
1837 bzero((void *)(va + off), size);
1838 tlb_page_demap(kernel_pmap, va);
1839 PMAP_UNLOCK(kernel_pmap);
1844 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
1852 KASSERT((mdst->flags & PG_FICTITIOUS) == 0,
1853 ("pmap_copy_page: fake dst page"));
1854 KASSERT((msrc->flags & PG_FICTITIOUS) == 0,
1855 ("pmap_copy_page: fake src page"));
1856 PMAP_STATS_INC(pmap_ncopy_page);
1857 pdst = VM_PAGE_TO_PHYS(mdst);
1858 psrc = VM_PAGE_TO_PHYS(msrc);
1859 if (dcache_color_ignore != 0 ||
1860 (msrc->md.color == DCACHE_COLOR(psrc) &&
1861 mdst->md.color == DCACHE_COLOR(pdst))) {
1862 PMAP_STATS_INC(pmap_ncopy_page_c);
1863 vdst = TLB_PHYS_TO_DIRECT(pdst);
1864 vsrc = TLB_PHYS_TO_DIRECT(psrc);
1865 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE);
1866 } else if (msrc->md.color == -1 && mdst->md.color == -1) {
1867 PMAP_STATS_INC(pmap_ncopy_page_nc);
1868 ascopy(ASI_PHYS_USE_EC, psrc, pdst, PAGE_SIZE);
1869 } else if (msrc->md.color == -1) {
1870 if (mdst->md.color == DCACHE_COLOR(pdst)) {
1871 PMAP_STATS_INC(pmap_ncopy_page_dc);
1872 vdst = TLB_PHYS_TO_DIRECT(pdst);
1873 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst,
1876 PMAP_STATS_INC(pmap_ncopy_page_doc);
1877 PMAP_LOCK(kernel_pmap);
1878 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE);
1879 tp = tsb_kvtotte(vdst);
1881 TD_V | TD_8K | TD_PA(pdst) | TD_CP | TD_CV | TD_W;
1882 tp->tte_vpn = TV_VPN(vdst, TS_8K);
1883 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst,
1885 tlb_page_demap(kernel_pmap, vdst);
1886 PMAP_UNLOCK(kernel_pmap);
1888 } else if (mdst->md.color == -1) {
1889 if (msrc->md.color == DCACHE_COLOR(psrc)) {
1890 PMAP_STATS_INC(pmap_ncopy_page_sc);
1891 vsrc = TLB_PHYS_TO_DIRECT(psrc);
1892 ascopyto((void *)vsrc, ASI_PHYS_USE_EC, pdst,
1895 PMAP_STATS_INC(pmap_ncopy_page_soc);
1896 PMAP_LOCK(kernel_pmap);
1897 vsrc = pmap_temp_map_1 + (msrc->md.color * PAGE_SIZE);
1898 tp = tsb_kvtotte(vsrc);
1900 TD_V | TD_8K | TD_PA(psrc) | TD_CP | TD_CV | TD_W;
1901 tp->tte_vpn = TV_VPN(vsrc, TS_8K);
1902 ascopyto((void *)vsrc, ASI_PHYS_USE_EC, pdst,
1904 tlb_page_demap(kernel_pmap, vsrc);
1905 PMAP_UNLOCK(kernel_pmap);
1908 PMAP_STATS_INC(pmap_ncopy_page_oc);
1909 PMAP_LOCK(kernel_pmap);
1910 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE);
1911 tp = tsb_kvtotte(vdst);
1913 TD_V | TD_8K | TD_PA(pdst) | TD_CP | TD_CV | TD_W;
1914 tp->tte_vpn = TV_VPN(vdst, TS_8K);
1915 vsrc = pmap_temp_map_2 + (msrc->md.color * PAGE_SIZE);
1916 tp = tsb_kvtotte(vsrc);
1918 TD_V | TD_8K | TD_PA(psrc) | TD_CP | TD_CV | TD_W;
1919 tp->tte_vpn = TV_VPN(vsrc, TS_8K);
1920 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE);
1921 tlb_page_demap(kernel_pmap, vdst);
1922 tlb_page_demap(kernel_pmap, vsrc);
1923 PMAP_UNLOCK(kernel_pmap);
1928 pmap_quick_enter_page(vm_page_t m)
1934 pa = VM_PAGE_TO_PHYS(m);
1935 if (dcache_color_ignore != 0 || m->md.color == DCACHE_COLOR(pa))
1936 return (TLB_PHYS_TO_DIRECT(pa));
1939 qaddr = PCPU_GET(qmap_addr);
1940 qaddr += (PAGE_SIZE * ((DCACHE_COLORS + DCACHE_COLOR(pa) -
1941 DCACHE_COLOR(qaddr)) % DCACHE_COLORS));
1942 tp = tsb_kvtotte(qaddr);
1944 KASSERT(tp->tte_data == 0, ("pmap_quick_enter_page: PTE busy"));
1946 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1947 tp->tte_vpn = TV_VPN(qaddr, TS_8K);
1953 pmap_quick_remove_page(vm_offset_t addr)
1958 if (addr >= VM_MIN_DIRECT_ADDRESS)
1961 tp = tsb_kvtotte(addr);
1962 qaddr = PCPU_GET(qmap_addr);
1964 KASSERT((addr >= qaddr) && (addr < (qaddr + (PAGE_SIZE * DCACHE_COLORS))),
1965 ("pmap_quick_remove_page: invalid address"));
1966 KASSERT(tp->tte_data != 0, ("pmap_quick_remove_page: PTE not in use"));
1968 stxa(TLB_DEMAP_VA(addr) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE, ASI_DMMU_DEMAP, 0);
1969 stxa(TLB_DEMAP_VA(addr) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE, ASI_IMMU_DEMAP, 0);
1975 int unmapped_buf_allowed;
1978 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
1979 vm_offset_t b_offset, int xfersize)
1982 panic("pmap_copy_pages: not implemented");
1986 * Returns true if the pmap's pv is one of the first
1987 * 16 pvs linked to from this page. This count may
1988 * be changed upwards or downwards in the future; it
1989 * is only necessary that true be returned for a small
1990 * subset of pmaps for proper page aging.
1993 pmap_page_exists_quick(pmap_t pm, vm_page_t m)
1999 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2000 ("pmap_page_exists_quick: page %p is not managed", m));
2003 rw_wlock(&tte_list_global_lock);
2004 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2005 if ((tp->tte_data & TD_PV) == 0)
2007 if (TTE_GET_PMAP(tp) == pm) {
2014 rw_wunlock(&tte_list_global_lock);
2019 * Return the number of managed mappings to the given physical page
2023 pmap_page_wired_mappings(vm_page_t m)
2029 if ((m->oflags & VPO_UNMANAGED) != 0)
2031 rw_wlock(&tte_list_global_lock);
2032 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link)
2033 if ((tp->tte_data & (TD_PV | TD_WIRED)) == (TD_PV | TD_WIRED))
2035 rw_wunlock(&tte_list_global_lock);
2040 * Remove all pages from specified address space, this aids process exit
2041 * speeds. This is much faster than pmap_remove in the case of running down
2042 * an entire address space. Only works for the current pmap.
2045 pmap_remove_pages(pmap_t pm)
2051 * Returns TRUE if the given page has a managed mapping.
2054 pmap_page_is_mapped(vm_page_t m)
2060 if ((m->oflags & VPO_UNMANAGED) != 0)
2062 rw_wlock(&tte_list_global_lock);
2063 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link)
2064 if ((tp->tte_data & TD_PV) != 0) {
2068 rw_wunlock(&tte_list_global_lock);
2073 * Return a count of reference bits for a page, clearing those bits.
2074 * It is not necessary for every reference bit to be cleared, but it
2075 * is necessary that 0 only be returned when there are truly no
2076 * reference bits set.
2078 * As an optimization, update the page's dirty field if a modified bit is
2079 * found while counting reference bits. This opportunistic update can be
2080 * performed at low cost and can eliminate the need for some future calls
2081 * to pmap_is_modified(). However, since this function stops after
2082 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
2083 * dirty pages. Those dirty pages will only be detected by a future call
2084 * to pmap_is_modified().
2087 pmap_ts_referenced(vm_page_t m)
2095 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2096 ("pmap_ts_referenced: page %p is not managed", m));
2098 rw_wlock(&tte_list_global_lock);
2099 if ((tp = TAILQ_FIRST(&m->md.tte_list)) != NULL) {
2102 tpn = TAILQ_NEXT(tp, tte_link);
2103 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
2104 TAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link);
2105 if ((tp->tte_data & TD_PV) == 0)
2107 data = atomic_clear_long(&tp->tte_data, TD_REF);
2108 if ((data & TD_W) != 0)
2110 if ((data & TD_REF) != 0 && ++count >=
2111 PMAP_TS_REFERENCED_MAX)
2113 } while ((tp = tpn) != NULL && tp != tpf);
2115 rw_wunlock(&tte_list_global_lock);
2120 pmap_is_modified(vm_page_t m)
2125 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2126 ("pmap_is_modified: page %p is not managed", m));
2130 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2131 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
2132 * is clear, no TTEs can have TD_W set.
2134 VM_OBJECT_ASSERT_WLOCKED(m->object);
2135 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2137 rw_wlock(&tte_list_global_lock);
2138 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2139 if ((tp->tte_data & TD_PV) == 0)
2141 if ((tp->tte_data & TD_W) != 0) {
2146 rw_wunlock(&tte_list_global_lock);
2151 * pmap_is_prefaultable:
2153 * Return whether or not the specified virtual address is elgible
2157 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
2162 rv = tsb_tte_lookup(pmap, addr) == NULL;
2168 * Return whether or not the specified physical page was referenced
2169 * in any physical maps.
2172 pmap_is_referenced(vm_page_t m)
2177 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2178 ("pmap_is_referenced: page %p is not managed", m));
2180 rw_wlock(&tte_list_global_lock);
2181 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2182 if ((tp->tte_data & TD_PV) == 0)
2184 if ((tp->tte_data & TD_REF) != 0) {
2189 rw_wunlock(&tte_list_global_lock);
2194 * This function is advisory.
2197 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
2202 pmap_clear_modify(vm_page_t m)
2207 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2208 ("pmap_clear_modify: page %p is not managed", m));
2209 VM_OBJECT_ASSERT_WLOCKED(m->object);
2210 KASSERT(!vm_page_xbusied(m),
2211 ("pmap_clear_modify: page %p is exclusive busied", m));
2214 * If the page is not PGA_WRITEABLE, then no TTEs can have TD_W set.
2215 * If the object containing the page is locked and the page is not
2216 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
2218 if ((m->aflags & PGA_WRITEABLE) == 0)
2220 rw_wlock(&tte_list_global_lock);
2221 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2222 if ((tp->tte_data & TD_PV) == 0)
2224 data = atomic_clear_long(&tp->tte_data, TD_W);
2225 if ((data & TD_W) != 0)
2226 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
2228 rw_wunlock(&tte_list_global_lock);
2232 pmap_remove_write(vm_page_t m)
2237 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2238 ("pmap_remove_write: page %p is not managed", m));
2241 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2242 * set by another thread while the object is locked. Thus,
2243 * if PGA_WRITEABLE is clear, no page table entries need updating.
2245 VM_OBJECT_ASSERT_WLOCKED(m->object);
2246 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2248 rw_wlock(&tte_list_global_lock);
2249 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2250 if ((tp->tte_data & TD_PV) == 0)
2252 data = atomic_clear_long(&tp->tte_data, TD_SW | TD_W);
2253 if ((data & TD_W) != 0) {
2255 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
2258 vm_page_aflag_clear(m, PGA_WRITEABLE);
2259 rw_wunlock(&tte_list_global_lock);
2263 pmap_mincore(pmap_t pm, vm_offset_t addr, vm_paddr_t *locked_pa)
2271 * Activate a user pmap. The pmap must be activated before its address space
2272 * can be accessed in any way.
2275 pmap_activate(struct thread *td)
2282 vm = td->td_proc->p_vmspace;
2283 pm = vmspace_pmap(vm);
2285 context = PCPU_GET(tlb_ctx);
2286 if (context == PCPU_GET(tlb_ctx_max)) {
2288 context = PCPU_GET(tlb_ctx_min);
2290 PCPU_SET(tlb_ctx, context + 1);
2292 pm->pm_context[curcpu] = context;
2294 CPU_SET_ATOMIC(PCPU_GET(cpuid), &pm->pm_active);
2295 atomic_store_acq_ptr((uintptr_t *)PCPU_PTR(pmap), (uintptr_t)pm);
2297 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
2301 stxa(AA_DMMU_TSB, ASI_DMMU, pm->pm_tsb);
2302 stxa(AA_IMMU_TSB, ASI_IMMU, pm->pm_tsb);
2303 stxa(AA_DMMU_PCXR, ASI_DMMU, (ldxa(AA_DMMU_PCXR, ASI_DMMU) &
2304 TLB_CXR_PGSZ_MASK) | context);
2310 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
2316 * Increase the starting virtual address of the given mapping if a
2317 * different alignment might result in more superpage mappings.
2320 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
2321 vm_offset_t *addr, vm_size_t size)