2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
9 * This code is derived from software contributed to Berkeley by
10 * the Systems Programming Group of the University of Utah Computer
11 * Science Department and William Jolitz of UUNET Technologies Inc.
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
40 #include <sys/cdefs.h>
41 __FBSDID("$FreeBSD$");
44 * Manages physical address maps.
46 * In addition to hardware address maps, this module is called upon to
47 * provide software-use-only maps which may or may not be stored in the
48 * same form as hardware maps. These pseudo-maps are used to store
49 * intermediate results from copy operations to and from address spaces.
51 * Since the information managed by this module is also stored by the
52 * logical address mapping module, this module may throw away valid virtual
53 * to physical mappings at almost any time. However, invalidations of
54 * mappings must be done as requested.
56 * In order to cope with hardware architectures which make virtual to
57 * physical map invalidates expensive, this module may delay invalidate
58 * reduced protection operations until such time as they are actually
59 * necessary. This module is given full information as to which processors
60 * are currently using which maps, and to when physical maps must be made
64 #include "opt_kstack_pages.h"
67 #include <sys/param.h>
68 #include <sys/kernel.h>
71 #include <sys/msgbuf.h>
72 #include <sys/mutex.h>
74 #include <sys/rwlock.h>
76 #include <sys/sysctl.h>
77 #include <sys/systm.h>
78 #include <sys/vmmeter.h>
80 #include <dev/ofw/openfirm.h>
83 #include <vm/vm_param.h>
84 #include <vm/vm_kern.h>
85 #include <vm/vm_page.h>
86 #include <vm/vm_map.h>
87 #include <vm/vm_object.h>
88 #include <vm/vm_extern.h>
89 #include <vm/vm_pageout.h>
90 #include <vm/vm_pager.h>
92 #include <machine/cache.h>
93 #include <machine/frame.h>
94 #include <machine/instr.h>
95 #include <machine/md_var.h>
96 #include <machine/metadata.h>
97 #include <machine/ofw_mem.h>
98 #include <machine/smp.h>
99 #include <machine/tlb.h>
100 #include <machine/tte.h>
101 #include <machine/tsb.h>
102 #include <machine/ver.h>
105 * Virtual address of message buffer
107 struct msgbuf *msgbufp;
110 * Map of physical memory reagions
112 vm_paddr_t phys_avail[128];
113 static struct ofw_mem_region mra[128];
114 struct ofw_mem_region sparc64_memreg[128];
116 static struct ofw_map translations[128];
117 static int translations_size;
119 static vm_offset_t pmap_idle_map;
120 static vm_offset_t pmap_temp_map_1;
121 static vm_offset_t pmap_temp_map_2;
124 * First and last available kernel virtual addresses
126 vm_offset_t virtual_avail;
127 vm_offset_t virtual_end;
128 vm_offset_t kernel_vm_end;
130 vm_offset_t vm_max_kernel_address;
135 struct pmap kernel_pmap_store;
138 * Global tte list lock
140 struct rwlock tte_list_global_lock;
143 * Allocate physical memory for use in pmap_bootstrap.
145 static vm_paddr_t pmap_bootstrap_alloc(vm_size_t size, uint32_t colors);
147 static void pmap_bootstrap_set_tte(struct tte *tp, u_long vpn, u_long data);
148 static void pmap_cache_remove(vm_page_t m, vm_offset_t va);
149 static int pmap_protect_tte(struct pmap *pm1, struct pmap *pm2,
150 struct tte *tp, vm_offset_t va);
153 * Map the given physical page at the specified virtual address in the
154 * target pmap with the protection requested. If specified the page
155 * will be wired down.
157 * The page queues and pmap must be locked.
159 static void pmap_enter_locked(pmap_t pm, vm_offset_t va, vm_page_t m,
160 vm_prot_t prot, boolean_t wired);
162 extern int tl1_dmmu_miss_direct_patch_tsb_phys_1[];
163 extern int tl1_dmmu_miss_direct_patch_tsb_phys_end_1[];
164 extern int tl1_dmmu_miss_patch_asi_1[];
165 extern int tl1_dmmu_miss_patch_quad_ldd_1[];
166 extern int tl1_dmmu_miss_patch_tsb_1[];
167 extern int tl1_dmmu_miss_patch_tsb_2[];
168 extern int tl1_dmmu_miss_patch_tsb_mask_1[];
169 extern int tl1_dmmu_miss_patch_tsb_mask_2[];
170 extern int tl1_dmmu_prot_patch_asi_1[];
171 extern int tl1_dmmu_prot_patch_quad_ldd_1[];
172 extern int tl1_dmmu_prot_patch_tsb_1[];
173 extern int tl1_dmmu_prot_patch_tsb_2[];
174 extern int tl1_dmmu_prot_patch_tsb_mask_1[];
175 extern int tl1_dmmu_prot_patch_tsb_mask_2[];
176 extern int tl1_immu_miss_patch_asi_1[];
177 extern int tl1_immu_miss_patch_quad_ldd_1[];
178 extern int tl1_immu_miss_patch_tsb_1[];
179 extern int tl1_immu_miss_patch_tsb_2[];
180 extern int tl1_immu_miss_patch_tsb_mask_1[];
181 extern int tl1_immu_miss_patch_tsb_mask_2[];
184 * If user pmap is processed with pmap_remove and with pmap_remove and the
185 * resident count drops to 0, there are no more pages to remove, so we
188 #define PMAP_REMOVE_DONE(pm) \
189 ((pm) != kernel_pmap && (pm)->pm_stats.resident_count == 0)
192 * The threshold (in bytes) above which tsb_foreach() is used in pmap_remove()
193 * and pmap_protect() instead of trying each virtual address.
195 #define PMAP_TSB_THRESH ((TSB_SIZE / 2) * PAGE_SIZE)
197 SYSCTL_NODE(_debug, OID_AUTO, pmap_stats, CTLFLAG_RD, 0, "");
199 PMAP_STATS_VAR(pmap_nenter);
200 PMAP_STATS_VAR(pmap_nenter_update);
201 PMAP_STATS_VAR(pmap_nenter_replace);
202 PMAP_STATS_VAR(pmap_nenter_new);
203 PMAP_STATS_VAR(pmap_nkenter);
204 PMAP_STATS_VAR(pmap_nkenter_oc);
205 PMAP_STATS_VAR(pmap_nkenter_stupid);
206 PMAP_STATS_VAR(pmap_nkremove);
207 PMAP_STATS_VAR(pmap_nqenter);
208 PMAP_STATS_VAR(pmap_nqremove);
209 PMAP_STATS_VAR(pmap_ncache_enter);
210 PMAP_STATS_VAR(pmap_ncache_enter_c);
211 PMAP_STATS_VAR(pmap_ncache_enter_oc);
212 PMAP_STATS_VAR(pmap_ncache_enter_cc);
213 PMAP_STATS_VAR(pmap_ncache_enter_coc);
214 PMAP_STATS_VAR(pmap_ncache_enter_nc);
215 PMAP_STATS_VAR(pmap_ncache_enter_cnc);
216 PMAP_STATS_VAR(pmap_ncache_remove);
217 PMAP_STATS_VAR(pmap_ncache_remove_c);
218 PMAP_STATS_VAR(pmap_ncache_remove_oc);
219 PMAP_STATS_VAR(pmap_ncache_remove_cc);
220 PMAP_STATS_VAR(pmap_ncache_remove_coc);
221 PMAP_STATS_VAR(pmap_ncache_remove_nc);
222 PMAP_STATS_VAR(pmap_nzero_page);
223 PMAP_STATS_VAR(pmap_nzero_page_c);
224 PMAP_STATS_VAR(pmap_nzero_page_oc);
225 PMAP_STATS_VAR(pmap_nzero_page_nc);
226 PMAP_STATS_VAR(pmap_nzero_page_area);
227 PMAP_STATS_VAR(pmap_nzero_page_area_c);
228 PMAP_STATS_VAR(pmap_nzero_page_area_oc);
229 PMAP_STATS_VAR(pmap_nzero_page_area_nc);
230 PMAP_STATS_VAR(pmap_nzero_page_idle);
231 PMAP_STATS_VAR(pmap_nzero_page_idle_c);
232 PMAP_STATS_VAR(pmap_nzero_page_idle_oc);
233 PMAP_STATS_VAR(pmap_nzero_page_idle_nc);
234 PMAP_STATS_VAR(pmap_ncopy_page);
235 PMAP_STATS_VAR(pmap_ncopy_page_c);
236 PMAP_STATS_VAR(pmap_ncopy_page_oc);
237 PMAP_STATS_VAR(pmap_ncopy_page_nc);
238 PMAP_STATS_VAR(pmap_ncopy_page_dc);
239 PMAP_STATS_VAR(pmap_ncopy_page_doc);
240 PMAP_STATS_VAR(pmap_ncopy_page_sc);
241 PMAP_STATS_VAR(pmap_ncopy_page_soc);
243 PMAP_STATS_VAR(pmap_nnew_thread);
244 PMAP_STATS_VAR(pmap_nnew_thread_oc);
246 static inline u_long dtlb_get_data(u_int tlb, u_int slot);
249 * Quick sort callout for comparing memory regions
251 static int mr_cmp(const void *a, const void *b);
252 static int om_cmp(const void *a, const void *b);
255 mr_cmp(const void *a, const void *b)
257 const struct ofw_mem_region *mra;
258 const struct ofw_mem_region *mrb;
262 if (mra->mr_start < mrb->mr_start)
264 else if (mra->mr_start > mrb->mr_start)
271 om_cmp(const void *a, const void *b)
273 const struct ofw_map *oma;
274 const struct ofw_map *omb;
278 if (oma->om_start < omb->om_start)
280 else if (oma->om_start > omb->om_start)
287 dtlb_get_data(u_int tlb, u_int slot)
292 slot = TLB_DAR_SLOT(tlb, slot);
294 * We read ASI_DTLB_DATA_ACCESS_REG twice back-to-back in order to
295 * work around errata of USIII and beyond.
298 (void)ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
299 data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
305 * Bootstrap the system enough to run with virtual memory.
308 pmap_bootstrap(u_int cpu_impl)
321 u_int dtlb_slots_avail;
330 * Set the kernel context.
334 colors = dcache_color_ignore != 0 ? 1 : DCACHE_COLORS;
337 * Find out what physical memory is available from the PROM and
338 * initialize the phys_avail array. This must be done before
339 * pmap_bootstrap_alloc is called.
341 if ((pmem = OF_finddevice("/memory")) == -1)
342 OF_panic("%s: finddevice /memory", __func__);
343 if ((sz = OF_getproplen(pmem, "available")) == -1)
344 OF_panic("%s: getproplen /memory/available", __func__);
345 if (sizeof(phys_avail) < sz)
346 OF_panic("%s: phys_avail too small", __func__);
347 if (sizeof(mra) < sz)
348 OF_panic("%s: mra too small", __func__);
350 if (OF_getprop(pmem, "available", mra, sz) == -1)
351 OF_panic("%s: getprop /memory/available", __func__);
353 CTR0(KTR_PMAP, "pmap_bootstrap: physical memory");
354 qsort(mra, sz, sizeof (*mra), mr_cmp);
356 getenv_quad("hw.physmem", &physmem);
357 physmem = btoc(physmem);
358 for (i = 0, j = 0; i < sz; i++, j += 2) {
359 CTR2(KTR_PMAP, "start=%#lx size=%#lx", mra[i].mr_start,
361 if (physmem != 0 && btoc(physsz + mra[i].mr_size) >= physmem) {
362 if (btoc(physsz) < physmem) {
363 phys_avail[j] = mra[i].mr_start;
364 phys_avail[j + 1] = mra[i].mr_start +
365 (ctob(physmem) - physsz);
366 physsz = ctob(physmem);
370 phys_avail[j] = mra[i].mr_start;
371 phys_avail[j + 1] = mra[i].mr_start + mra[i].mr_size;
372 physsz += mra[i].mr_size;
374 physmem = btoc(physsz);
377 * Calculate the size of kernel virtual memory, and the size and mask
378 * for the kernel TSB based on the phsyical memory size but limited
379 * by the amount of dTLB slots available for locked entries if we have
380 * to lock the TSB in the TLB (given that for spitfire-class CPUs all
381 * of the dt64 slots can hold locked entries but there is no large
382 * dTLB for unlocked ones, we don't use more than half of it for the
384 * Note that for reasons unknown OpenSolaris doesn't take advantage of
385 * ASI_ATOMIC_QUAD_LDD_PHYS on UltraSPARC-III. However, given that no
386 * public documentation is available for these, the latter just might
387 * not support it, yet.
389 if (cpu_impl == CPU_IMPL_SPARC64V ||
390 cpu_impl >= CPU_IMPL_ULTRASPARCIIIp) {
391 tsb_kernel_ldd_phys = 1;
392 virtsz = roundup(5 / 3 * physsz, PAGE_SIZE_4M <<
393 (PAGE_SHIFT - TTE_SHIFT));
395 dtlb_slots_avail = 0;
396 for (i = 0; i < dtlb_slots; i++) {
397 data = dtlb_get_data(cpu_impl ==
398 CPU_IMPL_ULTRASPARCIII ? TLB_DAR_T16 :
400 if ((data & (TD_V | TD_L)) != (TD_V | TD_L))
404 dtlb_slots_avail -= PCPU_PAGES;
406 if (cpu_impl >= CPU_IMPL_ULTRASPARCI &&
407 cpu_impl < CPU_IMPL_ULTRASPARCIII)
408 dtlb_slots_avail /= 2;
409 virtsz = roundup(physsz, PAGE_SIZE_4M <<
410 (PAGE_SHIFT - TTE_SHIFT));
411 virtsz = MIN(virtsz, (dtlb_slots_avail * PAGE_SIZE_4M) <<
412 (PAGE_SHIFT - TTE_SHIFT));
414 vm_max_kernel_address = VM_MIN_KERNEL_ADDRESS + virtsz;
415 tsb_kernel_size = virtsz >> (PAGE_SHIFT - TTE_SHIFT);
416 tsb_kernel_mask = (tsb_kernel_size >> TTE_SHIFT) - 1;
419 * Allocate the kernel TSB and lock it in the TLB if necessary.
421 pa = pmap_bootstrap_alloc(tsb_kernel_size, colors);
422 if (pa & PAGE_MASK_4M)
423 OF_panic("%s: TSB unaligned", __func__);
424 tsb_kernel_phys = pa;
425 if (tsb_kernel_ldd_phys == 0) {
427 (struct tte *)(VM_MIN_KERNEL_ADDRESS - tsb_kernel_size);
429 bzero(tsb_kernel, tsb_kernel_size);
432 (struct tte *)TLB_PHYS_TO_DIRECT(tsb_kernel_phys);
433 aszero(ASI_PHYS_USE_EC, tsb_kernel_phys, tsb_kernel_size);
437 * Allocate and map the dynamic per-CPU area for the BSP.
439 pa = pmap_bootstrap_alloc(DPCPU_SIZE, colors);
440 dpcpu0 = (void *)TLB_PHYS_TO_DIRECT(pa);
443 * Allocate and map the message buffer.
445 pa = pmap_bootstrap_alloc(msgbufsize, colors);
446 msgbufp = (struct msgbuf *)TLB_PHYS_TO_DIRECT(pa);
449 * Patch the TSB addresses and mask as well as the ASIs used to load
450 * it into the trap table.
453 #define LDDA_R_I_R(rd, imm_asi, rs1, rs2) \
454 (EIF_OP(IOP_LDST) | EIF_F3_RD(rd) | EIF_F3_OP3(INS3_LDDA) | \
455 EIF_F3_RS1(rs1) | EIF_F3_I(0) | EIF_F3_IMM_ASI(imm_asi) | \
457 #define OR_R_I_R(rd, imm13, rs1) \
458 (EIF_OP(IOP_MISC) | EIF_F3_RD(rd) | EIF_F3_OP3(INS2_OR) | \
459 EIF_F3_RS1(rs1) | EIF_F3_I(1) | EIF_IMM(imm13, 13))
460 #define SETHI(rd, imm22) \
461 (EIF_OP(IOP_FORM2) | EIF_F2_RD(rd) | EIF_F2_OP2(INS0_SETHI) | \
462 EIF_IMM((imm22) >> 10, 22))
463 #define WR_R_I(rd, imm13, rs1) \
464 (EIF_OP(IOP_MISC) | EIF_F3_RD(rd) | EIF_F3_OP3(INS2_WR) | \
465 EIF_F3_RS1(rs1) | EIF_F3_I(1) | EIF_IMM(imm13, 13))
467 #define PATCH_ASI(addr, asi) do { \
468 if (addr[0] != WR_R_I(IF_F3_RD(addr[0]), 0x0, \
469 IF_F3_RS1(addr[0]))) \
470 OF_panic("%s: patched instructions have changed", \
472 addr[0] |= EIF_IMM((asi), 13); \
476 #define PATCH_LDD(addr, asi) do { \
477 if (addr[0] != LDDA_R_I_R(IF_F3_RD(addr[0]), 0x0, \
478 IF_F3_RS1(addr[0]), IF_F3_RS2(addr[0]))) \
479 OF_panic("%s: patched instructions have changed", \
481 addr[0] |= EIF_F3_IMM_ASI(asi); \
485 #define PATCH_TSB(addr, val) do { \
486 if (addr[0] != SETHI(IF_F2_RD(addr[0]), 0x0) || \
487 addr[1] != OR_R_I_R(IF_F3_RD(addr[1]), 0x0, \
488 IF_F3_RS1(addr[1])) || \
489 addr[3] != SETHI(IF_F2_RD(addr[3]), 0x0)) \
490 OF_panic("%s: patched instructions have changed", \
492 addr[0] |= EIF_IMM((val) >> 42, 22); \
493 addr[1] |= EIF_IMM((val) >> 32, 10); \
494 addr[3] |= EIF_IMM((val) >> 10, 22); \
500 #define PATCH_TSB_MASK(addr, val) do { \
501 if (addr[0] != SETHI(IF_F2_RD(addr[0]), 0x0) || \
502 addr[1] != OR_R_I_R(IF_F3_RD(addr[1]), 0x0, \
503 IF_F3_RS1(addr[1]))) \
504 OF_panic("%s: patched instructions have changed", \
506 addr[0] |= EIF_IMM((val) >> 10, 22); \
507 addr[1] |= EIF_IMM((val), 10); \
512 if (tsb_kernel_ldd_phys == 0) {
514 ldd = ASI_NUCLEUS_QUAD_LDD;
515 off = (vm_offset_t)tsb_kernel;
517 asi = ASI_PHYS_USE_EC;
518 ldd = ASI_ATOMIC_QUAD_LDD_PHYS;
519 off = (vm_offset_t)tsb_kernel_phys;
521 PATCH_TSB(tl1_dmmu_miss_direct_patch_tsb_phys_1, tsb_kernel_phys);
522 PATCH_TSB(tl1_dmmu_miss_direct_patch_tsb_phys_end_1,
523 tsb_kernel_phys + tsb_kernel_size - 1);
524 PATCH_ASI(tl1_dmmu_miss_patch_asi_1, asi);
525 PATCH_LDD(tl1_dmmu_miss_patch_quad_ldd_1, ldd);
526 PATCH_TSB(tl1_dmmu_miss_patch_tsb_1, off);
527 PATCH_TSB(tl1_dmmu_miss_patch_tsb_2, off);
528 PATCH_TSB_MASK(tl1_dmmu_miss_patch_tsb_mask_1, tsb_kernel_mask);
529 PATCH_TSB_MASK(tl1_dmmu_miss_patch_tsb_mask_2, tsb_kernel_mask);
530 PATCH_ASI(tl1_dmmu_prot_patch_asi_1, asi);
531 PATCH_LDD(tl1_dmmu_prot_patch_quad_ldd_1, ldd);
532 PATCH_TSB(tl1_dmmu_prot_patch_tsb_1, off);
533 PATCH_TSB(tl1_dmmu_prot_patch_tsb_2, off);
534 PATCH_TSB_MASK(tl1_dmmu_prot_patch_tsb_mask_1, tsb_kernel_mask);
535 PATCH_TSB_MASK(tl1_dmmu_prot_patch_tsb_mask_2, tsb_kernel_mask);
536 PATCH_ASI(tl1_immu_miss_patch_asi_1, asi);
537 PATCH_LDD(tl1_immu_miss_patch_quad_ldd_1, ldd);
538 PATCH_TSB(tl1_immu_miss_patch_tsb_1, off);
539 PATCH_TSB(tl1_immu_miss_patch_tsb_2, off);
540 PATCH_TSB_MASK(tl1_immu_miss_patch_tsb_mask_1, tsb_kernel_mask);
541 PATCH_TSB_MASK(tl1_immu_miss_patch_tsb_mask_2, tsb_kernel_mask);
544 * Enter fake 8k pages for the 4MB kernel pages, so that
545 * pmap_kextract() will work for them.
547 for (i = 0; i < kernel_tlb_slots; i++) {
548 pa = kernel_tlbs[i].te_pa;
549 va = kernel_tlbs[i].te_va;
550 for (off = 0; off < PAGE_SIZE_4M; off += PAGE_SIZE) {
551 tp = tsb_kvtotte(va + off);
552 vpn = TV_VPN(va + off, TS_8K);
553 data = TD_V | TD_8K | TD_PA(pa + off) | TD_REF |
554 TD_SW | TD_CP | TD_CV | TD_P | TD_W;
555 pmap_bootstrap_set_tte(tp, vpn, data);
560 * Set the start and end of KVA. The kernel is loaded starting
561 * at the first available 4MB super page, so we advance to the
562 * end of the last one used for it.
564 virtual_avail = KERNBASE + kernel_tlb_slots * PAGE_SIZE_4M;
565 virtual_end = vm_max_kernel_address;
566 kernel_vm_end = vm_max_kernel_address;
569 * Allocate kva space for temporary mappings.
571 pmap_idle_map = virtual_avail;
572 virtual_avail += PAGE_SIZE * colors;
573 pmap_temp_map_1 = virtual_avail;
574 virtual_avail += PAGE_SIZE * colors;
575 pmap_temp_map_2 = virtual_avail;
576 virtual_avail += PAGE_SIZE * colors;
579 * Allocate a kernel stack with guard page for thread0 and map it
580 * into the kernel TSB. We must ensure that the virtual address is
581 * colored properly for corresponding CPUs, since we're allocating
582 * from phys_avail so the memory won't have an associated vm_page_t.
584 pa = pmap_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, colors);
586 virtual_avail += roundup(KSTACK_GUARD_PAGES, colors) * PAGE_SIZE;
587 kstack0 = virtual_avail;
588 virtual_avail += roundup(KSTACK_PAGES, colors) * PAGE_SIZE;
589 if (dcache_color_ignore == 0)
590 KASSERT(DCACHE_COLOR(kstack0) == DCACHE_COLOR(kstack0_phys),
591 ("pmap_bootstrap: kstack0 miscolored"));
592 for (i = 0; i < KSTACK_PAGES; i++) {
593 pa = kstack0_phys + i * PAGE_SIZE;
594 va = kstack0 + i * PAGE_SIZE;
595 tp = tsb_kvtotte(va);
596 vpn = TV_VPN(va, TS_8K);
597 data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_SW | TD_CP |
599 pmap_bootstrap_set_tte(tp, vpn, data);
603 * Calculate the last available physical address.
605 for (i = 0; phys_avail[i + 2] != 0; i += 2)
607 Maxmem = sparc64_btop(phys_avail[i + 1]);
610 * Add the PROM mappings to the kernel TSB.
612 if ((vmem = OF_finddevice("/virtual-memory")) == -1)
613 OF_panic("%s: finddevice /virtual-memory", __func__);
614 if ((sz = OF_getproplen(vmem, "translations")) == -1)
615 OF_panic("%s: getproplen translations", __func__);
616 if (sizeof(translations) < sz)
617 OF_panic("%s: translations too small", __func__);
618 bzero(translations, sz);
619 if (OF_getprop(vmem, "translations", translations, sz) == -1)
620 OF_panic("%s: getprop /virtual-memory/translations",
622 sz /= sizeof(*translations);
623 translations_size = sz;
624 CTR0(KTR_PMAP, "pmap_bootstrap: translations");
625 qsort(translations, sz, sizeof (*translations), om_cmp);
626 for (i = 0; i < sz; i++) {
628 "translation: start=%#lx size=%#lx tte=%#lx",
629 translations[i].om_start, translations[i].om_size,
630 translations[i].om_tte);
631 if ((translations[i].om_tte & TD_V) == 0)
633 if (translations[i].om_start < VM_MIN_PROM_ADDRESS ||
634 translations[i].om_start > VM_MAX_PROM_ADDRESS)
636 for (off = 0; off < translations[i].om_size;
638 va = translations[i].om_start + off;
639 tp = tsb_kvtotte(va);
640 vpn = TV_VPN(va, TS_8K);
641 data = ((translations[i].om_tte &
642 ~((TD_SOFT2_MASK << TD_SOFT2_SHIFT) |
643 (cpu_impl >= CPU_IMPL_ULTRASPARCI &&
644 cpu_impl < CPU_IMPL_ULTRASPARCIII ?
645 (TD_DIAG_SF_MASK << TD_DIAG_SF_SHIFT) :
646 (TD_RSVD_CH_MASK << TD_RSVD_CH_SHIFT)) |
647 (TD_SOFT_MASK << TD_SOFT_SHIFT))) | TD_EXEC) +
649 pmap_bootstrap_set_tte(tp, vpn, data);
654 * Get the available physical memory ranges from /memory/reg. These
655 * are only used for kernel dumps, but it may not be wise to do PROM
656 * calls in that situation.
658 if ((sz = OF_getproplen(pmem, "reg")) == -1)
659 OF_panic("%s: getproplen /memory/reg", __func__);
660 if (sizeof(sparc64_memreg) < sz)
661 OF_panic("%s: sparc64_memreg too small", __func__);
662 if (OF_getprop(pmem, "reg", sparc64_memreg, sz) == -1)
663 OF_panic("%s: getprop /memory/reg", __func__);
664 sparc64_nmemreg = sz / sizeof(*sparc64_memreg);
667 * Initialize the kernel pmap (which is statically allocated).
671 for (i = 0; i < MAXCPU; i++)
672 pm->pm_context[i] = TLB_CTX_KERNEL;
673 CPU_FILL(&pm->pm_active);
676 * Initialize the global tte list lock.
678 rw_init(&tte_list_global_lock, "tte list global");
681 * Flush all non-locked TLB entries possibly left over by the
684 tlb_flush_nonlocked();
688 * Map the 4MB kernel TSB pages.
698 for (i = 0; i < tsb_kernel_size; i += PAGE_SIZE_4M) {
699 va = (vm_offset_t)tsb_kernel + i;
700 pa = tsb_kernel_phys + i;
701 data = TD_V | TD_4M | TD_PA(pa) | TD_L | TD_CP | TD_CV |
703 stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) |
704 TLB_TAR_CTX(TLB_CTX_KERNEL));
705 stxa_sync(0, ASI_DTLB_DATA_IN_REG, data);
710 * Set the secondary context to be the kernel context (needed for FP block
711 * operations in the kernel).
717 stxa(AA_DMMU_SCXR, ASI_DMMU, (ldxa(AA_DMMU_SCXR, ASI_DMMU) &
718 TLB_CXR_PGSZ_MASK) | TLB_CTX_KERNEL);
723 * Allocate a physical page of memory directly from the phys_avail map.
724 * Can only be called from pmap_bootstrap before avail start and end are
728 pmap_bootstrap_alloc(vm_size_t size, uint32_t colors)
733 size = roundup(size, PAGE_SIZE * colors);
734 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
735 if (phys_avail[i + 1] - phys_avail[i] < size)
738 phys_avail[i] += size;
741 OF_panic("%s: no suitable region found", __func__);
745 * Set a TTE. This function is intended as a helper when tsb_kernel is
746 * direct-mapped but we haven't taken over the trap table, yet, as it's the
747 * case when we are taking advantage of ASI_ATOMIC_QUAD_LDD_PHYS to access
751 pmap_bootstrap_set_tte(struct tte *tp, u_long vpn, u_long data)
754 if (tsb_kernel_ldd_phys == 0) {
758 stxa((vm_paddr_t)tp + offsetof(struct tte, tte_vpn),
759 ASI_PHYS_USE_EC, vpn);
760 stxa((vm_paddr_t)tp + offsetof(struct tte, tte_data),
761 ASI_PHYS_USE_EC, data);
766 * Initialize a vm_page's machine-dependent fields.
769 pmap_page_init(vm_page_t m)
772 TAILQ_INIT(&m->md.tte_list);
773 m->md.color = DCACHE_COLOR(VM_PAGE_TO_PHYS(m));
779 * Initialize the pmap module.
789 for (i = 0; i < translations_size; i++) {
790 addr = translations[i].om_start;
791 size = translations[i].om_size;
792 if ((translations[i].om_tte & TD_V) == 0)
794 if (addr < VM_MIN_PROM_ADDRESS || addr > VM_MAX_PROM_ADDRESS)
796 result = vm_map_find(kernel_map, NULL, 0, &addr, size,
797 VMFS_NO_SPACE, VM_PROT_ALL, VM_PROT_ALL, MAP_NOFAULT);
798 if (result != KERN_SUCCESS || addr != translations[i].om_start)
799 panic("pmap_init: vm_map_find");
804 * Extract the physical page address associated with the given
805 * map/virtual_address pair.
808 pmap_extract(pmap_t pm, vm_offset_t va)
813 if (pm == kernel_pmap)
814 return (pmap_kextract(va));
816 tp = tsb_tte_lookup(pm, va);
820 pa = TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp));
826 * Atomically extract and hold the physical page with the given
827 * pmap and virtual address pair if that mapping permits the given
831 pmap_extract_and_hold(pmap_t pm, vm_offset_t va, vm_prot_t prot)
841 if (pm == kernel_pmap) {
842 if (va >= VM_MIN_DIRECT_ADDRESS) {
844 m = PHYS_TO_VM_PAGE(TLB_DIRECT_TO_PHYS(va));
845 (void)vm_page_pa_tryrelock(pm, TLB_DIRECT_TO_PHYS(va),
849 tp = tsb_kvtotte(va);
850 if ((tp->tte_data & TD_V) == 0)
854 tp = tsb_tte_lookup(pm, va);
855 if (tp != NULL && ((tp->tte_data & TD_SW) ||
856 (prot & VM_PROT_WRITE) == 0)) {
857 if (vm_page_pa_tryrelock(pm, TTE_GET_PA(tp), &pa))
859 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
868 * Extract the physical page address associated with the given kernel virtual
872 pmap_kextract(vm_offset_t va)
876 if (va >= VM_MIN_DIRECT_ADDRESS)
877 return (TLB_DIRECT_TO_PHYS(va));
878 tp = tsb_kvtotte(va);
879 if ((tp->tte_data & TD_V) == 0)
881 return (TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp)));
885 pmap_cache_enter(vm_page_t m, vm_offset_t va)
890 rw_assert(&tte_list_global_lock, RA_WLOCKED);
891 KASSERT((m->flags & PG_FICTITIOUS) == 0,
892 ("pmap_cache_enter: fake page"));
893 PMAP_STATS_INC(pmap_ncache_enter);
895 if (dcache_color_ignore != 0)
899 * Find the color for this virtual address and note the added mapping.
901 color = DCACHE_COLOR(va);
902 m->md.colors[color]++;
905 * If all existing mappings have the same color, the mapping is
908 if (m->md.color == color) {
909 KASSERT(m->md.colors[DCACHE_OTHER_COLOR(color)] == 0,
910 ("pmap_cache_enter: cacheable, mappings of other color"));
911 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
912 PMAP_STATS_INC(pmap_ncache_enter_c);
914 PMAP_STATS_INC(pmap_ncache_enter_oc);
919 * If there are no mappings of the other color, and the page still has
920 * the wrong color, this must be a new mapping. Change the color to
921 * match the new mapping, which is cacheable. We must flush the page
922 * from the cache now.
924 if (m->md.colors[DCACHE_OTHER_COLOR(color)] == 0) {
925 KASSERT(m->md.colors[color] == 1,
926 ("pmap_cache_enter: changing color, not new mapping"));
927 dcache_page_inval(VM_PAGE_TO_PHYS(m));
929 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
930 PMAP_STATS_INC(pmap_ncache_enter_cc);
932 PMAP_STATS_INC(pmap_ncache_enter_coc);
937 * If the mapping is already non-cacheable, just return.
939 if (m->md.color == -1) {
940 PMAP_STATS_INC(pmap_ncache_enter_nc);
944 PMAP_STATS_INC(pmap_ncache_enter_cnc);
947 * Mark all mappings as uncacheable, flush any lines with the other
948 * color out of the dcache, and set the color to none (-1).
950 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
951 atomic_clear_long(&tp->tte_data, TD_CV);
952 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
954 dcache_page_inval(VM_PAGE_TO_PHYS(m));
960 pmap_cache_remove(vm_page_t m, vm_offset_t va)
965 rw_assert(&tte_list_global_lock, RA_WLOCKED);
966 CTR3(KTR_PMAP, "pmap_cache_remove: m=%p va=%#lx c=%d", m, va,
967 m->md.colors[DCACHE_COLOR(va)]);
968 KASSERT((m->flags & PG_FICTITIOUS) == 0,
969 ("pmap_cache_remove: fake page"));
970 PMAP_STATS_INC(pmap_ncache_remove);
972 if (dcache_color_ignore != 0)
975 KASSERT(m->md.colors[DCACHE_COLOR(va)] > 0,
976 ("pmap_cache_remove: no mappings %d <= 0",
977 m->md.colors[DCACHE_COLOR(va)]));
980 * Find the color for this virtual address and note the removal of
983 color = DCACHE_COLOR(va);
984 m->md.colors[color]--;
987 * If the page is cacheable, just return and keep the same color, even
988 * if there are no longer any mappings.
990 if (m->md.color != -1) {
991 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
992 PMAP_STATS_INC(pmap_ncache_remove_c);
994 PMAP_STATS_INC(pmap_ncache_remove_oc);
998 KASSERT(m->md.colors[DCACHE_OTHER_COLOR(color)] != 0,
999 ("pmap_cache_remove: uncacheable, no mappings of other color"));
1002 * If the page is not cacheable (color is -1), and the number of
1003 * mappings for this color is not zero, just return. There are
1004 * mappings of the other color still, so remain non-cacheable.
1006 if (m->md.colors[color] != 0) {
1007 PMAP_STATS_INC(pmap_ncache_remove_nc);
1012 * The number of mappings for this color is now zero. Recache the
1013 * other colored mappings, and change the page color to the other
1014 * color. There should be no lines in the data cache for this page,
1015 * so flushing should not be needed.
1017 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1018 atomic_set_long(&tp->tte_data, TD_CV);
1019 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1021 m->md.color = DCACHE_OTHER_COLOR(color);
1023 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
1024 PMAP_STATS_INC(pmap_ncache_remove_cc);
1026 PMAP_STATS_INC(pmap_ncache_remove_coc);
1030 * Map a wired page into kernel virtual address space.
1033 pmap_kenter(vm_offset_t va, vm_page_t m)
1040 rw_assert(&tte_list_global_lock, RA_WLOCKED);
1041 PMAP_STATS_INC(pmap_nkenter);
1042 tp = tsb_kvtotte(va);
1043 CTR4(KTR_PMAP, "pmap_kenter: va=%#lx pa=%#lx tp=%p data=%#lx",
1044 va, VM_PAGE_TO_PHYS(m), tp, tp->tte_data);
1045 if (DCACHE_COLOR(VM_PAGE_TO_PHYS(m)) != DCACHE_COLOR(va)) {
1047 "pmap_kenter: off color va=%#lx pa=%#lx o=%p ot=%d pi=%#lx",
1048 va, VM_PAGE_TO_PHYS(m), m->object,
1049 m->object ? m->object->type : -1,
1051 PMAP_STATS_INC(pmap_nkenter_oc);
1053 if ((tp->tte_data & TD_V) != 0) {
1054 om = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
1055 ova = TTE_GET_VA(tp);
1056 if (m == om && va == ova) {
1057 PMAP_STATS_INC(pmap_nkenter_stupid);
1060 TAILQ_REMOVE(&om->md.tte_list, tp, tte_link);
1061 pmap_cache_remove(om, ova);
1063 tlb_page_demap(kernel_pmap, ova);
1065 data = TD_V | TD_8K | VM_PAGE_TO_PHYS(m) | TD_REF | TD_SW | TD_CP |
1067 if (pmap_cache_enter(m, va) != 0)
1069 tp->tte_vpn = TV_VPN(va, TS_8K);
1070 tp->tte_data = data;
1071 TAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link);
1075 * Map a wired page into kernel virtual address space. This additionally
1076 * takes a flag argument which is or'ed to the TTE data. This is used by
1077 * sparc64_bus_mem_map().
1078 * NOTE: if the mapping is non-cacheable, it's the caller's responsibility
1079 * to flush entries that might still be in the cache, if applicable.
1082 pmap_kenter_flags(vm_offset_t va, vm_paddr_t pa, u_long flags)
1086 tp = tsb_kvtotte(va);
1087 CTR4(KTR_PMAP, "pmap_kenter_flags: va=%#lx pa=%#lx tp=%p data=%#lx",
1088 va, pa, tp, tp->tte_data);
1089 tp->tte_vpn = TV_VPN(va, TS_8K);
1090 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_P | flags;
1094 * Remove a wired page from kernel virtual address space.
1097 pmap_kremove(vm_offset_t va)
1102 rw_assert(&tte_list_global_lock, RA_WLOCKED);
1103 PMAP_STATS_INC(pmap_nkremove);
1104 tp = tsb_kvtotte(va);
1105 CTR3(KTR_PMAP, "pmap_kremove: va=%#lx tp=%p data=%#lx", va, tp,
1107 if ((tp->tte_data & TD_V) == 0)
1109 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
1110 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1111 pmap_cache_remove(m, va);
1116 * Inverse of pmap_kenter_flags, used by bus_space_unmap().
1119 pmap_kremove_flags(vm_offset_t va)
1123 tp = tsb_kvtotte(va);
1124 CTR3(KTR_PMAP, "pmap_kremove_flags: va=%#lx tp=%p data=%#lx", va, tp,
1130 * Map a range of physical addresses into kernel virtual address space.
1132 * The value passed in *virt is a suggested virtual address for the mapping.
1133 * Architectures which can support a direct-mapped physical to virtual region
1134 * can return the appropriate address within that region, leaving '*virt'
1138 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1141 return (TLB_PHYS_TO_DIRECT(start));
1145 * Map a list of wired pages into kernel virtual address space. This is
1146 * intended for temporary mappings which do not need page modification or
1147 * references recorded. Existing mappings in the region are overwritten.
1150 pmap_qenter(vm_offset_t sva, vm_page_t *m, int count)
1154 PMAP_STATS_INC(pmap_nqenter);
1156 rw_wlock(&tte_list_global_lock);
1157 while (count-- > 0) {
1158 pmap_kenter(va, *m);
1162 rw_wunlock(&tte_list_global_lock);
1163 tlb_range_demap(kernel_pmap, sva, va);
1167 * Remove page mappings from kernel virtual address space. Intended for
1168 * temporary mappings entered by pmap_qenter.
1171 pmap_qremove(vm_offset_t sva, int count)
1175 PMAP_STATS_INC(pmap_nqremove);
1177 rw_wlock(&tte_list_global_lock);
1178 while (count-- > 0) {
1182 rw_wunlock(&tte_list_global_lock);
1183 tlb_range_demap(kernel_pmap, sva, va);
1187 * Initialize the pmap associated with process 0.
1190 pmap_pinit0(pmap_t pm)
1195 for (i = 0; i < MAXCPU; i++)
1196 pm->pm_context[i] = TLB_CTX_KERNEL;
1197 CPU_ZERO(&pm->pm_active);
1199 pm->pm_tsb_obj = NULL;
1200 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1204 * Initialize a preallocated and zeroed pmap structure, such as one in a
1205 * vmspace structure.
1208 pmap_pinit(pmap_t pm)
1210 vm_page_t ma[TSB_PAGES];
1217 * Allocate KVA space for the TSB.
1219 if (pm->pm_tsb == NULL) {
1220 pm->pm_tsb = (struct tte *)kmem_alloc_nofault(kernel_map,
1222 if (pm->pm_tsb == NULL) {
1223 PMAP_LOCK_DESTROY(pm);
1229 * Allocate an object for it.
1231 if (pm->pm_tsb_obj == NULL)
1232 pm->pm_tsb_obj = vm_object_allocate(OBJT_PHYS, TSB_PAGES);
1234 for (i = 0; i < MAXCPU; i++)
1235 pm->pm_context[i] = -1;
1236 CPU_ZERO(&pm->pm_active);
1238 VM_OBJECT_LOCK(pm->pm_tsb_obj);
1239 for (i = 0; i < TSB_PAGES; i++) {
1240 m = vm_page_grab(pm->pm_tsb_obj, i, VM_ALLOC_NOBUSY |
1241 VM_ALLOC_RETRY | VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1242 m->valid = VM_PAGE_BITS_ALL;
1246 VM_OBJECT_UNLOCK(pm->pm_tsb_obj);
1247 pmap_qenter((vm_offset_t)pm->pm_tsb, ma, TSB_PAGES);
1249 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1254 * Release any resources held by the given physical map.
1255 * Called when a pmap initialized by pmap_pinit is being released.
1256 * Should only be called if the map contains no valid mappings.
1259 pmap_release(pmap_t pm)
1267 CTR2(KTR_PMAP, "pmap_release: ctx=%#x tsb=%p",
1268 pm->pm_context[curcpu], pm->pm_tsb);
1269 KASSERT(pmap_resident_count(pm) == 0,
1270 ("pmap_release: resident pages %ld != 0",
1271 pmap_resident_count(pm)));
1274 * After the pmap was freed, it might be reallocated to a new process.
1275 * When switching, this might lead us to wrongly assume that we need
1276 * not switch contexts because old and new pmap pointer are equal.
1277 * Therefore, make sure that this pmap is not referenced by any PCPU
1278 * pointer any more. This could happen in two cases:
1279 * - A process that referenced the pmap is currently exiting on a CPU.
1280 * However, it is guaranteed to not switch in any more after setting
1281 * its state to PRS_ZOMBIE.
1282 * - A process that referenced this pmap ran on a CPU, but we switched
1283 * to a kernel thread, leaving the pmap pointer unchanged.
1287 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu)
1288 atomic_cmpset_rel_ptr((uintptr_t *)&pc->pc_pmap,
1289 (uintptr_t)pm, (uintptr_t)NULL);
1293 if (PCPU_GET(pmap) == pm)
1294 PCPU_SET(pmap, NULL);
1298 pmap_qremove((vm_offset_t)pm->pm_tsb, TSB_PAGES);
1299 obj = pm->pm_tsb_obj;
1300 VM_OBJECT_LOCK(obj);
1301 KASSERT(obj->ref_count == 1, ("pmap_release: tsbobj ref count != 1"));
1302 while (!TAILQ_EMPTY(&obj->memq)) {
1303 m = TAILQ_FIRST(&obj->memq);
1306 atomic_subtract_int(&cnt.v_wire_count, 1);
1307 vm_page_free_zero(m);
1309 VM_OBJECT_UNLOCK(obj);
1310 PMAP_LOCK_DESTROY(pm);
1314 * Grow the number of kernel page table entries. Unneeded.
1317 pmap_growkernel(vm_offset_t addr)
1320 panic("pmap_growkernel: can't grow kernel");
1324 pmap_remove_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp,
1330 rw_assert(&tte_list_global_lock, RA_WLOCKED);
1331 data = atomic_readandclear_long(&tp->tte_data);
1332 if ((data & TD_FAKE) == 0) {
1333 m = PHYS_TO_VM_PAGE(TD_PA(data));
1334 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1335 if ((data & TD_WIRED) != 0)
1336 pm->pm_stats.wired_count--;
1337 if ((data & TD_PV) != 0) {
1338 if ((data & TD_W) != 0)
1340 if ((data & TD_REF) != 0)
1341 vm_page_aflag_set(m, PGA_REFERENCED);
1342 if (TAILQ_EMPTY(&m->md.tte_list))
1343 vm_page_aflag_clear(m, PGA_WRITEABLE);
1344 pm->pm_stats.resident_count--;
1346 pmap_cache_remove(m, va);
1349 if (PMAP_REMOVE_DONE(pm))
1355 * Remove the given range of addresses from the specified map.
1358 pmap_remove(pmap_t pm, vm_offset_t start, vm_offset_t end)
1363 CTR3(KTR_PMAP, "pmap_remove: ctx=%#lx start=%#lx end=%#lx",
1364 pm->pm_context[curcpu], start, end);
1365 if (PMAP_REMOVE_DONE(pm))
1367 rw_wlock(&tte_list_global_lock);
1369 if (end - start > PMAP_TSB_THRESH) {
1370 tsb_foreach(pm, NULL, start, end, pmap_remove_tte);
1371 tlb_context_demap(pm);
1373 for (va = start; va < end; va += PAGE_SIZE)
1374 if ((tp = tsb_tte_lookup(pm, va)) != NULL &&
1375 !pmap_remove_tte(pm, NULL, tp, va))
1377 tlb_range_demap(pm, start, end - 1);
1380 rw_wunlock(&tte_list_global_lock);
1384 pmap_remove_all(vm_page_t m)
1391 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1392 ("pmap_remove_all: page %p is not managed", m));
1393 rw_wlock(&tte_list_global_lock);
1394 for (tp = TAILQ_FIRST(&m->md.tte_list); tp != NULL; tp = tpn) {
1395 tpn = TAILQ_NEXT(tp, tte_link);
1396 if ((tp->tte_data & TD_PV) == 0)
1398 pm = TTE_GET_PMAP(tp);
1399 va = TTE_GET_VA(tp);
1401 if ((tp->tte_data & TD_WIRED) != 0)
1402 pm->pm_stats.wired_count--;
1403 if ((tp->tte_data & TD_REF) != 0)
1404 vm_page_aflag_set(m, PGA_REFERENCED);
1405 if ((tp->tte_data & TD_W) != 0)
1407 tp->tte_data &= ~TD_V;
1408 tlb_page_demap(pm, va);
1409 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1410 pm->pm_stats.resident_count--;
1411 pmap_cache_remove(m, va);
1415 vm_page_aflag_clear(m, PGA_WRITEABLE);
1416 rw_wunlock(&tte_list_global_lock);
1420 pmap_protect_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp,
1426 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1427 data = atomic_clear_long(&tp->tte_data, TD_SW | TD_W);
1428 if ((data & (TD_PV | TD_W)) == (TD_PV | TD_W)) {
1429 m = PHYS_TO_VM_PAGE(TD_PA(data));
1436 * Set the physical protection on the specified range of this map as requested.
1439 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
1444 CTR4(KTR_PMAP, "pmap_protect: ctx=%#lx sva=%#lx eva=%#lx prot=%#lx",
1445 pm->pm_context[curcpu], sva, eva, prot);
1447 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1448 pmap_remove(pm, sva, eva);
1452 if (prot & VM_PROT_WRITE)
1456 if (eva - sva > PMAP_TSB_THRESH) {
1457 tsb_foreach(pm, NULL, sva, eva, pmap_protect_tte);
1458 tlb_context_demap(pm);
1460 for (va = sva; va < eva; va += PAGE_SIZE)
1461 if ((tp = tsb_tte_lookup(pm, va)) != NULL)
1462 pmap_protect_tte(pm, NULL, tp, va);
1463 tlb_range_demap(pm, sva, eva - 1);
1469 * Map the given physical page at the specified virtual address in the
1470 * target pmap with the protection requested. If specified the page
1471 * will be wired down.
1474 pmap_enter(pmap_t pm, vm_offset_t va, vm_prot_t access, vm_page_t m,
1475 vm_prot_t prot, boolean_t wired)
1478 rw_wlock(&tte_list_global_lock);
1480 pmap_enter_locked(pm, va, m, prot, wired);
1481 rw_wunlock(&tte_list_global_lock);
1486 * Map the given physical page at the specified virtual address in the
1487 * target pmap with the protection requested. If specified the page
1488 * will be wired down.
1490 * The page queues and pmap must be locked.
1493 pmap_enter_locked(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1501 rw_assert(&tte_list_global_lock, RA_WLOCKED);
1502 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1503 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
1504 VM_OBJECT_LOCKED(m->object),
1505 ("pmap_enter_locked: page %p is not busy", m));
1506 PMAP_STATS_INC(pmap_nenter);
1507 pa = VM_PAGE_TO_PHYS(m);
1510 * If this is a fake page from the device_pager, but it covers actual
1511 * physical memory, convert to the real backing page.
1513 if ((m->flags & PG_FICTITIOUS) != 0) {
1514 real = vm_phys_paddr_to_vm_page(pa);
1520 "pmap_enter_locked: ctx=%p m=%p va=%#lx pa=%#lx prot=%#x wired=%d",
1521 pm->pm_context[curcpu], m, va, pa, prot, wired);
1524 * If there is an existing mapping, and the physical address has not
1525 * changed, must be protection or wiring change.
1527 if ((tp = tsb_tte_lookup(pm, va)) != NULL && TTE_GET_PA(tp) == pa) {
1528 CTR0(KTR_PMAP, "pmap_enter_locked: update");
1529 PMAP_STATS_INC(pmap_nenter_update);
1532 * Wiring change, just update stats.
1535 if ((tp->tte_data & TD_WIRED) == 0) {
1536 tp->tte_data |= TD_WIRED;
1537 pm->pm_stats.wired_count++;
1540 if ((tp->tte_data & TD_WIRED) != 0) {
1541 tp->tte_data &= ~TD_WIRED;
1542 pm->pm_stats.wired_count--;
1547 * Save the old bits and clear the ones we're interested in.
1549 data = tp->tte_data;
1550 tp->tte_data &= ~(TD_EXEC | TD_SW | TD_W);
1553 * If we're turning off write permissions, sense modify status.
1555 if ((prot & VM_PROT_WRITE) != 0) {
1556 tp->tte_data |= TD_SW;
1558 tp->tte_data |= TD_W;
1559 if ((m->oflags & VPO_UNMANAGED) == 0)
1560 vm_page_aflag_set(m, PGA_WRITEABLE);
1561 } else if ((data & TD_W) != 0)
1565 * If we're turning on execute permissions, flush the icache.
1567 if ((prot & VM_PROT_EXECUTE) != 0) {
1568 if ((data & TD_EXEC) == 0)
1569 icache_page_inval(pa);
1570 tp->tte_data |= TD_EXEC;
1574 * Delete the old mapping.
1576 tlb_page_demap(pm, TTE_GET_VA(tp));
1579 * If there is an existing mapping, but its for a different
1580 * physical address, delete the old mapping.
1583 CTR0(KTR_PMAP, "pmap_enter_locked: replace");
1584 PMAP_STATS_INC(pmap_nenter_replace);
1585 pmap_remove_tte(pm, NULL, tp, va);
1586 tlb_page_demap(pm, va);
1588 CTR0(KTR_PMAP, "pmap_enter_locked: new");
1589 PMAP_STATS_INC(pmap_nenter_new);
1593 * Now set up the data and install the new mapping.
1595 data = TD_V | TD_8K | TD_PA(pa);
1596 if (pm == kernel_pmap)
1598 if ((prot & VM_PROT_WRITE) != 0) {
1600 if ((m->oflags & VPO_UNMANAGED) == 0)
1601 vm_page_aflag_set(m, PGA_WRITEABLE);
1603 if (prot & VM_PROT_EXECUTE) {
1605 icache_page_inval(pa);
1609 * If its wired update stats. We also don't need reference or
1610 * modify tracking for wired mappings, so set the bits now.
1613 pm->pm_stats.wired_count++;
1614 data |= TD_REF | TD_WIRED;
1615 if ((prot & VM_PROT_WRITE) != 0)
1619 tsb_tte_enter(pm, m, va, TS_8K, data);
1624 * Maps a sequence of resident pages belonging to the same object.
1625 * The sequence begins with the given page m_start. This page is
1626 * mapped at the given virtual address start. Each subsequent page is
1627 * mapped at a virtual address that is offset from start by the same
1628 * amount as the page is offset from m_start within the object. The
1629 * last page in the sequence is the page with the largest offset from
1630 * m_start that can be mapped at a virtual address less than the given
1631 * virtual address end. Not every virtual page between start and end
1632 * is mapped; only those for which a resident page exists with the
1633 * corresponding offset from m_start are mapped.
1636 pmap_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end,
1637 vm_page_t m_start, vm_prot_t prot)
1640 vm_pindex_t diff, psize;
1642 psize = atop(end - start);
1644 rw_wlock(&tte_list_global_lock);
1646 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1647 pmap_enter_locked(pm, start + ptoa(diff), m, prot &
1648 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1649 m = TAILQ_NEXT(m, listq);
1651 rw_wunlock(&tte_list_global_lock);
1656 pmap_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot)
1659 rw_wlock(&tte_list_global_lock);
1661 pmap_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1663 rw_wunlock(&tte_list_global_lock);
1668 pmap_object_init_pt(pmap_t pm, vm_offset_t addr, vm_object_t object,
1669 vm_pindex_t pindex, vm_size_t size)
1672 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
1673 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
1674 ("pmap_object_init_pt: non-device object"));
1678 * Change the wiring attribute for a map/virtual-address pair.
1679 * The mapping must already exist in the pmap.
1682 pmap_change_wiring(pmap_t pm, vm_offset_t va, boolean_t wired)
1688 if ((tp = tsb_tte_lookup(pm, va)) != NULL) {
1690 data = atomic_set_long(&tp->tte_data, TD_WIRED);
1691 if ((data & TD_WIRED) == 0)
1692 pm->pm_stats.wired_count++;
1694 data = atomic_clear_long(&tp->tte_data, TD_WIRED);
1695 if ((data & TD_WIRED) != 0)
1696 pm->pm_stats.wired_count--;
1703 pmap_copy_tte(pmap_t src_pmap, pmap_t dst_pmap, struct tte *tp,
1709 if ((tp->tte_data & TD_FAKE) != 0)
1711 if (tsb_tte_lookup(dst_pmap, va) == NULL) {
1712 data = tp->tte_data &
1713 ~(TD_PV | TD_REF | TD_SW | TD_CV | TD_W);
1714 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
1715 tsb_tte_enter(dst_pmap, m, va, TS_8K, data);
1721 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
1722 vm_size_t len, vm_offset_t src_addr)
1727 if (dst_addr != src_addr)
1729 rw_wlock(&tte_list_global_lock);
1730 if (dst_pmap < src_pmap) {
1731 PMAP_LOCK(dst_pmap);
1732 PMAP_LOCK(src_pmap);
1734 PMAP_LOCK(src_pmap);
1735 PMAP_LOCK(dst_pmap);
1737 if (len > PMAP_TSB_THRESH) {
1738 tsb_foreach(src_pmap, dst_pmap, src_addr, src_addr + len,
1740 tlb_context_demap(dst_pmap);
1742 for (va = src_addr; va < src_addr + len; va += PAGE_SIZE)
1743 if ((tp = tsb_tte_lookup(src_pmap, va)) != NULL)
1744 pmap_copy_tte(src_pmap, dst_pmap, tp, va);
1745 tlb_range_demap(dst_pmap, src_addr, src_addr + len - 1);
1747 rw_wunlock(&tte_list_global_lock);
1748 PMAP_UNLOCK(src_pmap);
1749 PMAP_UNLOCK(dst_pmap);
1753 pmap_zero_page(vm_page_t m)
1759 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1760 ("pmap_zero_page: fake page"));
1761 PMAP_STATS_INC(pmap_nzero_page);
1762 pa = VM_PAGE_TO_PHYS(m);
1763 if (dcache_color_ignore != 0 || m->md.color == DCACHE_COLOR(pa)) {
1764 PMAP_STATS_INC(pmap_nzero_page_c);
1765 va = TLB_PHYS_TO_DIRECT(pa);
1766 cpu_block_zero((void *)va, PAGE_SIZE);
1767 } else if (m->md.color == -1) {
1768 PMAP_STATS_INC(pmap_nzero_page_nc);
1769 aszero(ASI_PHYS_USE_EC, pa, PAGE_SIZE);
1771 PMAP_STATS_INC(pmap_nzero_page_oc);
1772 PMAP_LOCK(kernel_pmap);
1773 va = pmap_temp_map_1 + (m->md.color * PAGE_SIZE);
1774 tp = tsb_kvtotte(va);
1775 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1776 tp->tte_vpn = TV_VPN(va, TS_8K);
1777 cpu_block_zero((void *)va, PAGE_SIZE);
1778 tlb_page_demap(kernel_pmap, va);
1779 PMAP_UNLOCK(kernel_pmap);
1784 pmap_zero_page_area(vm_page_t m, int off, int size)
1790 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1791 ("pmap_zero_page_area: fake page"));
1792 KASSERT(off + size <= PAGE_SIZE, ("pmap_zero_page_area: bad off/size"));
1793 PMAP_STATS_INC(pmap_nzero_page_area);
1794 pa = VM_PAGE_TO_PHYS(m);
1795 if (dcache_color_ignore != 0 || m->md.color == DCACHE_COLOR(pa)) {
1796 PMAP_STATS_INC(pmap_nzero_page_area_c);
1797 va = TLB_PHYS_TO_DIRECT(pa);
1798 bzero((void *)(va + off), size);
1799 } else if (m->md.color == -1) {
1800 PMAP_STATS_INC(pmap_nzero_page_area_nc);
1801 aszero(ASI_PHYS_USE_EC, pa + off, size);
1803 PMAP_STATS_INC(pmap_nzero_page_area_oc);
1804 PMAP_LOCK(kernel_pmap);
1805 va = pmap_temp_map_1 + (m->md.color * PAGE_SIZE);
1806 tp = tsb_kvtotte(va);
1807 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1808 tp->tte_vpn = TV_VPN(va, TS_8K);
1809 bzero((void *)(va + off), size);
1810 tlb_page_demap(kernel_pmap, va);
1811 PMAP_UNLOCK(kernel_pmap);
1816 pmap_zero_page_idle(vm_page_t m)
1822 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1823 ("pmap_zero_page_idle: fake page"));
1824 PMAP_STATS_INC(pmap_nzero_page_idle);
1825 pa = VM_PAGE_TO_PHYS(m);
1826 if (dcache_color_ignore != 0 || m->md.color == DCACHE_COLOR(pa)) {
1827 PMAP_STATS_INC(pmap_nzero_page_idle_c);
1828 va = TLB_PHYS_TO_DIRECT(pa);
1829 cpu_block_zero((void *)va, PAGE_SIZE);
1830 } else if (m->md.color == -1) {
1831 PMAP_STATS_INC(pmap_nzero_page_idle_nc);
1832 aszero(ASI_PHYS_USE_EC, pa, PAGE_SIZE);
1834 PMAP_STATS_INC(pmap_nzero_page_idle_oc);
1835 va = pmap_idle_map + (m->md.color * PAGE_SIZE);
1836 tp = tsb_kvtotte(va);
1837 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1838 tp->tte_vpn = TV_VPN(va, TS_8K);
1839 cpu_block_zero((void *)va, PAGE_SIZE);
1840 tlb_page_demap(kernel_pmap, va);
1845 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
1853 KASSERT((mdst->flags & PG_FICTITIOUS) == 0,
1854 ("pmap_copy_page: fake dst page"));
1855 KASSERT((msrc->flags & PG_FICTITIOUS) == 0,
1856 ("pmap_copy_page: fake src page"));
1857 PMAP_STATS_INC(pmap_ncopy_page);
1858 pdst = VM_PAGE_TO_PHYS(mdst);
1859 psrc = VM_PAGE_TO_PHYS(msrc);
1860 if (dcache_color_ignore != 0 ||
1861 (msrc->md.color == DCACHE_COLOR(psrc) &&
1862 mdst->md.color == DCACHE_COLOR(pdst))) {
1863 PMAP_STATS_INC(pmap_ncopy_page_c);
1864 vdst = TLB_PHYS_TO_DIRECT(pdst);
1865 vsrc = TLB_PHYS_TO_DIRECT(psrc);
1866 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE);
1867 } else if (msrc->md.color == -1 && mdst->md.color == -1) {
1868 PMAP_STATS_INC(pmap_ncopy_page_nc);
1869 ascopy(ASI_PHYS_USE_EC, psrc, pdst, PAGE_SIZE);
1870 } else if (msrc->md.color == -1) {
1871 if (mdst->md.color == DCACHE_COLOR(pdst)) {
1872 PMAP_STATS_INC(pmap_ncopy_page_dc);
1873 vdst = TLB_PHYS_TO_DIRECT(pdst);
1874 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst,
1877 PMAP_STATS_INC(pmap_ncopy_page_doc);
1878 PMAP_LOCK(kernel_pmap);
1879 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE);
1880 tp = tsb_kvtotte(vdst);
1882 TD_V | TD_8K | TD_PA(pdst) | TD_CP | TD_CV | TD_W;
1883 tp->tte_vpn = TV_VPN(vdst, TS_8K);
1884 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst,
1886 tlb_page_demap(kernel_pmap, vdst);
1887 PMAP_UNLOCK(kernel_pmap);
1889 } else if (mdst->md.color == -1) {
1890 if (msrc->md.color == DCACHE_COLOR(psrc)) {
1891 PMAP_STATS_INC(pmap_ncopy_page_sc);
1892 vsrc = TLB_PHYS_TO_DIRECT(psrc);
1893 ascopyto((void *)vsrc, ASI_PHYS_USE_EC, pdst,
1896 PMAP_STATS_INC(pmap_ncopy_page_soc);
1897 PMAP_LOCK(kernel_pmap);
1898 vsrc = pmap_temp_map_1 + (msrc->md.color * PAGE_SIZE);
1899 tp = tsb_kvtotte(vsrc);
1901 TD_V | TD_8K | TD_PA(psrc) | TD_CP | TD_CV | TD_W;
1902 tp->tte_vpn = TV_VPN(vsrc, TS_8K);
1903 ascopyto((void *)vsrc, ASI_PHYS_USE_EC, pdst,
1905 tlb_page_demap(kernel_pmap, vsrc);
1906 PMAP_UNLOCK(kernel_pmap);
1909 PMAP_STATS_INC(pmap_ncopy_page_oc);
1910 PMAP_LOCK(kernel_pmap);
1911 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE);
1912 tp = tsb_kvtotte(vdst);
1914 TD_V | TD_8K | TD_PA(pdst) | TD_CP | TD_CV | TD_W;
1915 tp->tte_vpn = TV_VPN(vdst, TS_8K);
1916 vsrc = pmap_temp_map_2 + (msrc->md.color * PAGE_SIZE);
1917 tp = tsb_kvtotte(vsrc);
1919 TD_V | TD_8K | TD_PA(psrc) | TD_CP | TD_CV | TD_W;
1920 tp->tte_vpn = TV_VPN(vsrc, TS_8K);
1921 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE);
1922 tlb_page_demap(kernel_pmap, vdst);
1923 tlb_page_demap(kernel_pmap, vsrc);
1924 PMAP_UNLOCK(kernel_pmap);
1929 * Returns true if the pmap's pv is one of the first
1930 * 16 pvs linked to from this page. This count may
1931 * be changed upwards or downwards in the future; it
1932 * is only necessary that true be returned for a small
1933 * subset of pmaps for proper page aging.
1936 pmap_page_exists_quick(pmap_t pm, vm_page_t m)
1942 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1943 ("pmap_page_exists_quick: page %p is not managed", m));
1946 rw_wlock(&tte_list_global_lock);
1947 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1948 if ((tp->tte_data & TD_PV) == 0)
1950 if (TTE_GET_PMAP(tp) == pm) {
1957 rw_wunlock(&tte_list_global_lock);
1962 * Return the number of managed mappings to the given physical page
1966 pmap_page_wired_mappings(vm_page_t m)
1972 if ((m->oflags & VPO_UNMANAGED) != 0)
1974 rw_wlock(&tte_list_global_lock);
1975 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link)
1976 if ((tp->tte_data & (TD_PV | TD_WIRED)) == (TD_PV | TD_WIRED))
1978 rw_wunlock(&tte_list_global_lock);
1983 * Remove all pages from specified address space, this aids process exit
1984 * speeds. This is much faster than pmap_remove in the case of running down
1985 * an entire address space. Only works for the current pmap.
1988 pmap_remove_pages(pmap_t pm)
1994 * Returns TRUE if the given page has a managed mapping.
1997 pmap_page_is_mapped(vm_page_t m)
2003 if ((m->oflags & VPO_UNMANAGED) != 0)
2005 rw_wlock(&tte_list_global_lock);
2006 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link)
2007 if ((tp->tte_data & TD_PV) != 0) {
2011 rw_wunlock(&tte_list_global_lock);
2016 * Return a count of reference bits for a page, clearing those bits.
2017 * It is not necessary for every reference bit to be cleared, but it
2018 * is necessary that 0 only be returned when there are truly no
2019 * reference bits set.
2021 * XXX: The exact number of bits to check and clear is a matter that
2022 * should be tested and standardized at some point in the future for
2023 * optimal aging of shared pages.
2026 pmap_ts_referenced(vm_page_t m)
2034 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2035 ("pmap_ts_referenced: page %p is not managed", m));
2037 rw_wlock(&tte_list_global_lock);
2038 if ((tp = TAILQ_FIRST(&m->md.tte_list)) != NULL) {
2041 tpn = TAILQ_NEXT(tp, tte_link);
2042 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
2043 TAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link);
2044 if ((tp->tte_data & TD_PV) == 0)
2046 data = atomic_clear_long(&tp->tte_data, TD_REF);
2047 if ((data & TD_REF) != 0 && ++count > 4)
2049 } while ((tp = tpn) != NULL && tp != tpf);
2051 rw_wunlock(&tte_list_global_lock);
2056 pmap_is_modified(vm_page_t m)
2061 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2062 ("pmap_is_modified: page %p is not managed", m));
2066 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
2067 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
2068 * is clear, no TTEs can have TD_W set.
2070 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
2071 if ((m->oflags & VPO_BUSY) == 0 &&
2072 (m->aflags & PGA_WRITEABLE) == 0)
2074 rw_wlock(&tte_list_global_lock);
2075 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2076 if ((tp->tte_data & TD_PV) == 0)
2078 if ((tp->tte_data & TD_W) != 0) {
2083 rw_wunlock(&tte_list_global_lock);
2088 * pmap_is_prefaultable:
2090 * Return whether or not the specified virtual address is elgible
2094 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
2099 rv = tsb_tte_lookup(pmap, addr) == NULL;
2105 * Return whether or not the specified physical page was referenced
2106 * in any physical maps.
2109 pmap_is_referenced(vm_page_t m)
2114 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2115 ("pmap_is_referenced: page %p is not managed", m));
2117 rw_wlock(&tte_list_global_lock);
2118 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2119 if ((tp->tte_data & TD_PV) == 0)
2121 if ((tp->tte_data & TD_REF) != 0) {
2126 rw_wunlock(&tte_list_global_lock);
2131 pmap_clear_modify(vm_page_t m)
2136 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2137 ("pmap_clear_modify: page %p is not managed", m));
2138 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
2139 KASSERT((m->oflags & VPO_BUSY) == 0,
2140 ("pmap_clear_modify: page %p is busy", m));
2143 * If the page is not PGA_WRITEABLE, then no TTEs can have TD_W set.
2144 * If the object containing the page is locked and the page is not
2145 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
2147 if ((m->aflags & PGA_WRITEABLE) == 0)
2149 rw_wlock(&tte_list_global_lock);
2150 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2151 if ((tp->tte_data & TD_PV) == 0)
2153 data = atomic_clear_long(&tp->tte_data, TD_W);
2154 if ((data & TD_W) != 0)
2155 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
2157 rw_wunlock(&tte_list_global_lock);
2161 pmap_clear_reference(vm_page_t m)
2166 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2167 ("pmap_clear_reference: page %p is not managed", m));
2168 rw_wlock(&tte_list_global_lock);
2169 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2170 if ((tp->tte_data & TD_PV) == 0)
2172 data = atomic_clear_long(&tp->tte_data, TD_REF);
2173 if ((data & TD_REF) != 0)
2174 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
2176 rw_wunlock(&tte_list_global_lock);
2180 pmap_remove_write(vm_page_t m)
2185 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2186 ("pmap_remove_write: page %p is not managed", m));
2189 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
2190 * another thread while the object is locked. Thus, if PGA_WRITEABLE
2191 * is clear, no page table entries need updating.
2193 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
2194 if ((m->oflags & VPO_BUSY) == 0 &&
2195 (m->aflags & PGA_WRITEABLE) == 0)
2197 rw_wlock(&tte_list_global_lock);
2198 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2199 if ((tp->tte_data & TD_PV) == 0)
2201 data = atomic_clear_long(&tp->tte_data, TD_SW | TD_W);
2202 if ((data & TD_W) != 0) {
2204 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
2207 vm_page_aflag_clear(m, PGA_WRITEABLE);
2208 rw_wunlock(&tte_list_global_lock);
2212 pmap_mincore(pmap_t pm, vm_offset_t addr, vm_paddr_t *locked_pa)
2220 * Activate a user pmap. The pmap must be activated before its address space
2221 * can be accessed in any way.
2224 pmap_activate(struct thread *td)
2231 vm = td->td_proc->p_vmspace;
2232 pm = vmspace_pmap(vm);
2234 context = PCPU_GET(tlb_ctx);
2235 if (context == PCPU_GET(tlb_ctx_max)) {
2237 context = PCPU_GET(tlb_ctx_min);
2239 PCPU_SET(tlb_ctx, context + 1);
2241 pm->pm_context[curcpu] = context;
2243 CPU_SET_ATOMIC(PCPU_GET(cpuid), &pm->pm_active);
2244 atomic_store_ptr((uintptr_t *)PCPU_PTR(pmap), (uintptr_t)pm);
2246 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
2250 stxa(AA_DMMU_TSB, ASI_DMMU, pm->pm_tsb);
2251 stxa(AA_IMMU_TSB, ASI_IMMU, pm->pm_tsb);
2252 stxa(AA_DMMU_PCXR, ASI_DMMU, (ldxa(AA_DMMU_PCXR, ASI_DMMU) &
2253 TLB_CXR_PGSZ_MASK) | context);
2259 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
2265 * Increase the starting virtual address of the given mapping if a
2266 * different alignment might result in more superpage mappings.
2269 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
2270 vm_offset_t *addr, vm_size_t size)