2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
9 * This code is derived from software contributed to Berkeley by
10 * the Systems Programming Group of the University of Utah Computer
11 * Science Department and William Jolitz of UUNET Technologies Inc.
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. All advertising materials mentioning features or use of this software
22 * must display the following acknowledgement:
23 * This product includes software developed by the University of
24 * California, Berkeley and its contributors.
25 * 4. Neither the name of the University nor the names of its contributors
26 * may be used to endorse or promote products derived from this software
27 * without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
44 #include <sys/cdefs.h>
45 __FBSDID("$FreeBSD$");
48 * Manages physical address maps.
50 * In addition to hardware address maps, this module is called upon to
51 * provide software-use-only maps which may or may not be stored in the
52 * same form as hardware maps. These pseudo-maps are used to store
53 * intermediate results from copy operations to and from address spaces.
55 * Since the information managed by this module is also stored by the
56 * logical address mapping module, this module may throw away valid virtual
57 * to physical mappings at almost any time. However, invalidations of
58 * mappings must be done as requested.
60 * In order to cope with hardware architectures which make virtual to
61 * physical map invalidates expensive, this module may delay invalidate
62 * reduced protection operations until such time as they are actually
63 * necessary. This module is given full information as to which processors
64 * are currently using which maps, and to when physical maps must be made
68 #include "opt_kstack_pages.h"
69 #include "opt_msgbuf.h"
72 #include <sys/param.h>
73 #include <sys/kernel.h>
76 #include <sys/msgbuf.h>
77 #include <sys/mutex.h>
80 #include <sys/sysctl.h>
81 #include <sys/systm.h>
82 #include <sys/vmmeter.h>
84 #include <dev/ofw/openfirm.h>
87 #include <vm/vm_param.h>
88 #include <vm/vm_kern.h>
89 #include <vm/vm_page.h>
90 #include <vm/vm_map.h>
91 #include <vm/vm_object.h>
92 #include <vm/vm_extern.h>
93 #include <vm/vm_pageout.h>
94 #include <vm/vm_pager.h>
96 #include <machine/cache.h>
97 #include <machine/frame.h>
98 #include <machine/instr.h>
99 #include <machine/md_var.h>
100 #include <machine/metadata.h>
101 #include <machine/ofw_mem.h>
102 #include <machine/smp.h>
103 #include <machine/tlb.h>
104 #include <machine/tte.h>
105 #include <machine/tsb.h>
109 #ifndef PMAP_SHPGPERPROC
110 #define PMAP_SHPGPERPROC 200
114 #include "opt_sched.h"
116 #error "sparc64 only works with SCHED_4BSD which uses a global scheduler lock."
118 extern struct mtx sched_lock;
121 * Virtual and physical address of message buffer.
123 struct msgbuf *msgbufp;
124 vm_paddr_t msgbuf_phys;
127 * Map of physical memory reagions.
129 vm_paddr_t phys_avail[128];
130 static struct ofw_mem_region mra[128];
131 struct ofw_mem_region sparc64_memreg[128];
133 static struct ofw_map translations[128];
134 static int translations_size;
136 static vm_offset_t pmap_idle_map;
137 static vm_offset_t pmap_temp_map_1;
138 static vm_offset_t pmap_temp_map_2;
141 * First and last available kernel virtual addresses.
143 vm_offset_t virtual_avail;
144 vm_offset_t virtual_end;
145 vm_offset_t kernel_vm_end;
147 vm_offset_t vm_max_kernel_address;
152 struct pmap kernel_pmap_store;
155 * Allocate physical memory for use in pmap_bootstrap.
157 static vm_paddr_t pmap_bootstrap_alloc(vm_size_t size);
160 * Map the given physical page at the specified virtual address in the
161 * target pmap with the protection requested. If specified the page
162 * will be wired down.
164 * The page queues and pmap must be locked.
166 static void pmap_enter_locked(pmap_t pm, vm_offset_t va, vm_page_t m,
167 vm_prot_t prot, boolean_t wired);
169 extern int tl1_immu_miss_patch_1[];
170 extern int tl1_immu_miss_patch_2[];
171 extern int tl1_dmmu_miss_patch_1[];
172 extern int tl1_dmmu_miss_patch_2[];
173 extern int tl1_dmmu_prot_patch_1[];
174 extern int tl1_dmmu_prot_patch_2[];
177 * If user pmap is processed with pmap_remove and with pmap_remove and the
178 * resident count drops to 0, there are no more pages to remove, so we
181 #define PMAP_REMOVE_DONE(pm) \
182 ((pm) != kernel_pmap && (pm)->pm_stats.resident_count == 0)
185 * The threshold (in bytes) above which tsb_foreach() is used in pmap_remove()
186 * and pmap_protect() instead of trying each virtual address.
188 #define PMAP_TSB_THRESH ((TSB_SIZE / 2) * PAGE_SIZE)
190 SYSCTL_NODE(_debug, OID_AUTO, pmap_stats, CTLFLAG_RD, 0, "");
192 PMAP_STATS_VAR(pmap_nenter);
193 PMAP_STATS_VAR(pmap_nenter_update);
194 PMAP_STATS_VAR(pmap_nenter_replace);
195 PMAP_STATS_VAR(pmap_nenter_new);
196 PMAP_STATS_VAR(pmap_nkenter);
197 PMAP_STATS_VAR(pmap_nkenter_oc);
198 PMAP_STATS_VAR(pmap_nkenter_stupid);
199 PMAP_STATS_VAR(pmap_nkremove);
200 PMAP_STATS_VAR(pmap_nqenter);
201 PMAP_STATS_VAR(pmap_nqremove);
202 PMAP_STATS_VAR(pmap_ncache_enter);
203 PMAP_STATS_VAR(pmap_ncache_enter_c);
204 PMAP_STATS_VAR(pmap_ncache_enter_oc);
205 PMAP_STATS_VAR(pmap_ncache_enter_cc);
206 PMAP_STATS_VAR(pmap_ncache_enter_coc);
207 PMAP_STATS_VAR(pmap_ncache_enter_nc);
208 PMAP_STATS_VAR(pmap_ncache_enter_cnc);
209 PMAP_STATS_VAR(pmap_ncache_remove);
210 PMAP_STATS_VAR(pmap_ncache_remove_c);
211 PMAP_STATS_VAR(pmap_ncache_remove_oc);
212 PMAP_STATS_VAR(pmap_ncache_remove_cc);
213 PMAP_STATS_VAR(pmap_ncache_remove_coc);
214 PMAP_STATS_VAR(pmap_ncache_remove_nc);
215 PMAP_STATS_VAR(pmap_nzero_page);
216 PMAP_STATS_VAR(pmap_nzero_page_c);
217 PMAP_STATS_VAR(pmap_nzero_page_oc);
218 PMAP_STATS_VAR(pmap_nzero_page_nc);
219 PMAP_STATS_VAR(pmap_nzero_page_area);
220 PMAP_STATS_VAR(pmap_nzero_page_area_c);
221 PMAP_STATS_VAR(pmap_nzero_page_area_oc);
222 PMAP_STATS_VAR(pmap_nzero_page_area_nc);
223 PMAP_STATS_VAR(pmap_nzero_page_idle);
224 PMAP_STATS_VAR(pmap_nzero_page_idle_c);
225 PMAP_STATS_VAR(pmap_nzero_page_idle_oc);
226 PMAP_STATS_VAR(pmap_nzero_page_idle_nc);
227 PMAP_STATS_VAR(pmap_ncopy_page);
228 PMAP_STATS_VAR(pmap_ncopy_page_c);
229 PMAP_STATS_VAR(pmap_ncopy_page_oc);
230 PMAP_STATS_VAR(pmap_ncopy_page_nc);
231 PMAP_STATS_VAR(pmap_ncopy_page_dc);
232 PMAP_STATS_VAR(pmap_ncopy_page_doc);
233 PMAP_STATS_VAR(pmap_ncopy_page_sc);
234 PMAP_STATS_VAR(pmap_ncopy_page_soc);
236 PMAP_STATS_VAR(pmap_nnew_thread);
237 PMAP_STATS_VAR(pmap_nnew_thread_oc);
240 * Quick sort callout for comparing memory regions.
242 static int mr_cmp(const void *a, const void *b);
243 static int om_cmp(const void *a, const void *b);
245 mr_cmp(const void *a, const void *b)
247 const struct ofw_mem_region *mra;
248 const struct ofw_mem_region *mrb;
252 if (mra->mr_start < mrb->mr_start)
254 else if (mra->mr_start > mrb->mr_start)
260 om_cmp(const void *a, const void *b)
262 const struct ofw_map *oma;
263 const struct ofw_map *omb;
267 if (oma->om_start < omb->om_start)
269 else if (oma->om_start > omb->om_start)
276 * Bootstrap the system enough to run with virtual memory.
279 pmap_bootstrap(vm_offset_t ekva)
295 * Find out what physical memory is available from the prom and
296 * initialize the phys_avail array. This must be done before
297 * pmap_bootstrap_alloc is called.
299 if ((pmem = OF_finddevice("/memory")) == -1)
300 panic("pmap_bootstrap: finddevice /memory");
301 if ((sz = OF_getproplen(pmem, "available")) == -1)
302 panic("pmap_bootstrap: getproplen /memory/available");
303 if (sizeof(phys_avail) < sz)
304 panic("pmap_bootstrap: phys_avail too small");
305 if (sizeof(mra) < sz)
306 panic("pmap_bootstrap: mra too small");
308 if (OF_getprop(pmem, "available", mra, sz) == -1)
309 panic("pmap_bootstrap: getprop /memory/available");
311 CTR0(KTR_PMAP, "pmap_bootstrap: physical memory");
312 qsort(mra, sz, sizeof (*mra), mr_cmp);
314 getenv_quad("hw.physmem", &physmem);
315 physmem = btoc(physmem);
316 for (i = 0, j = 0; i < sz; i++, j += 2) {
317 CTR2(KTR_PMAP, "start=%#lx size=%#lx", mra[i].mr_start,
319 if (physmem != 0 && btoc(physsz + mra[i].mr_size) >= physmem) {
320 if (btoc(physsz) < physmem) {
321 phys_avail[j] = mra[i].mr_start;
322 phys_avail[j + 1] = mra[i].mr_start +
323 (ctob(physmem) - physsz);
324 physsz = ctob(physmem);
328 phys_avail[j] = mra[i].mr_start;
329 phys_avail[j + 1] = mra[i].mr_start + mra[i].mr_size;
330 physsz += mra[i].mr_size;
332 physmem = btoc(physsz);
335 * Calculate the size of kernel virtual memory, and the size and mask
336 * for the kernel tsb.
338 virtsz = roundup(physsz, PAGE_SIZE_4M << (PAGE_SHIFT - TTE_SHIFT));
339 vm_max_kernel_address = VM_MIN_KERNEL_ADDRESS + virtsz;
340 tsb_kernel_size = virtsz >> (PAGE_SHIFT - TTE_SHIFT);
341 tsb_kernel_mask = (tsb_kernel_size >> TTE_SHIFT) - 1;
344 * Allocate the kernel tsb and lock it in the tlb.
346 pa = pmap_bootstrap_alloc(tsb_kernel_size);
347 if (pa & PAGE_MASK_4M)
348 panic("pmap_bootstrap: tsb unaligned\n");
349 tsb_kernel_phys = pa;
350 tsb_kernel = (struct tte *)(VM_MIN_KERNEL_ADDRESS - tsb_kernel_size);
352 bzero(tsb_kernel, tsb_kernel_size);
355 * Allocate and map the message buffer.
357 msgbuf_phys = pmap_bootstrap_alloc(MSGBUF_SIZE);
358 msgbufp = (struct msgbuf *)TLB_PHYS_TO_DIRECT(msgbuf_phys);
361 * Patch the virtual address and the tsb mask into the trap table.
364 #define SETHI(rd, imm22) \
365 (EIF_OP(IOP_FORM2) | EIF_F2_RD(rd) | EIF_F2_OP2(INS0_SETHI) | \
366 EIF_IMM((imm22) >> 10, 22))
367 #define OR_R_I_R(rd, imm13, rs1) \
368 (EIF_OP(IOP_MISC) | EIF_F3_RD(rd) | EIF_F3_OP3(INS2_OR) | \
369 EIF_F3_RS1(rs1) | EIF_F3_I(1) | EIF_IMM(imm13, 13))
371 #define PATCH(addr) do { \
372 if (addr[0] != SETHI(IF_F2_RD(addr[0]), 0x0) || \
373 addr[1] != OR_R_I_R(IF_F3_RD(addr[1]), 0x0, IF_F3_RS1(addr[1])) || \
374 addr[2] != SETHI(IF_F2_RD(addr[2]), 0x0)) \
375 panic("pmap_boostrap: patched instructions have changed"); \
376 addr[0] |= EIF_IMM((tsb_kernel_mask) >> 10, 22); \
377 addr[1] |= EIF_IMM(tsb_kernel_mask, 10); \
378 addr[2] |= EIF_IMM(((vm_offset_t)tsb_kernel) >> 10, 22); \
384 PATCH(tl1_immu_miss_patch_1);
385 PATCH(tl1_immu_miss_patch_2);
386 PATCH(tl1_dmmu_miss_patch_1);
387 PATCH(tl1_dmmu_miss_patch_2);
388 PATCH(tl1_dmmu_prot_patch_1);
389 PATCH(tl1_dmmu_prot_patch_2);
392 * Enter fake 8k pages for the 4MB kernel pages, so that
393 * pmap_kextract() will work for them.
395 for (i = 0; i < kernel_tlb_slots; i++) {
396 pa = kernel_tlbs[i].te_pa;
397 va = kernel_tlbs[i].te_va;
398 for (off = 0; off < PAGE_SIZE_4M; off += PAGE_SIZE) {
399 tp = tsb_kvtotte(va + off);
400 tp->tte_vpn = TV_VPN(va + off, TS_8K);
401 tp->tte_data = TD_V | TD_8K | TD_PA(pa + off) |
402 TD_REF | TD_SW | TD_CP | TD_CV | TD_P | TD_W;
407 * Set the start and end of kva. The kernel is loaded at the first
408 * available 4 meg super page, so round up to the end of the page.
410 virtual_avail = roundup2(ekva, PAGE_SIZE_4M);
411 virtual_end = vm_max_kernel_address;
412 kernel_vm_end = vm_max_kernel_address;
415 * Allocate kva space for temporary mappings.
417 pmap_idle_map = virtual_avail;
418 virtual_avail += PAGE_SIZE * DCACHE_COLORS;
419 pmap_temp_map_1 = virtual_avail;
420 virtual_avail += PAGE_SIZE * DCACHE_COLORS;
421 pmap_temp_map_2 = virtual_avail;
422 virtual_avail += PAGE_SIZE * DCACHE_COLORS;
425 * Allocate a kernel stack with guard page for thread0 and map it into
426 * the kernel tsb. We must ensure that the virtual address is coloured
427 * properly, since we're allocating from phys_avail so the memory won't
428 * have an associated vm_page_t.
430 pa = pmap_bootstrap_alloc(roundup(KSTACK_PAGES, DCACHE_COLORS) *
433 virtual_avail += roundup(KSTACK_GUARD_PAGES, DCACHE_COLORS) *
435 kstack0 = virtual_avail;
436 virtual_avail += roundup(KSTACK_PAGES, DCACHE_COLORS) * PAGE_SIZE;
437 KASSERT(DCACHE_COLOR(kstack0) == DCACHE_COLOR(kstack0_phys),
438 ("pmap_bootstrap: kstack0 miscoloured"));
439 for (i = 0; i < KSTACK_PAGES; i++) {
440 pa = kstack0_phys + i * PAGE_SIZE;
441 va = kstack0 + i * PAGE_SIZE;
442 tp = tsb_kvtotte(va);
443 tp->tte_vpn = TV_VPN(va, TS_8K);
444 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_SW |
445 TD_CP | TD_CV | TD_P | TD_W;
449 * Calculate the last available physical address.
451 for (i = 0; phys_avail[i + 2] != 0; i += 2)
453 Maxmem = sparc64_btop(phys_avail[i + 1]);
456 * Add the prom mappings to the kernel tsb.
458 if ((vmem = OF_finddevice("/virtual-memory")) == -1)
459 panic("pmap_bootstrap: finddevice /virtual-memory");
460 if ((sz = OF_getproplen(vmem, "translations")) == -1)
461 panic("pmap_bootstrap: getproplen translations");
462 if (sizeof(translations) < sz)
463 panic("pmap_bootstrap: translations too small");
464 bzero(translations, sz);
465 if (OF_getprop(vmem, "translations", translations, sz) == -1)
466 panic("pmap_bootstrap: getprop /virtual-memory/translations");
467 sz /= sizeof(*translations);
468 translations_size = sz;
469 CTR0(KTR_PMAP, "pmap_bootstrap: translations");
470 qsort(translations, sz, sizeof (*translations), om_cmp);
471 for (i = 0; i < sz; i++) {
473 "translation: start=%#lx size=%#lx tte=%#lx",
474 translations[i].om_start, translations[i].om_size,
475 translations[i].om_tte);
476 if (translations[i].om_start < VM_MIN_PROM_ADDRESS ||
477 translations[i].om_start > VM_MAX_PROM_ADDRESS)
479 for (off = 0; off < translations[i].om_size;
481 va = translations[i].om_start + off;
482 tp = tsb_kvtotte(va);
483 tp->tte_vpn = TV_VPN(va, TS_8K);
485 ((translations[i].om_tte &
486 ~(TD_SOFT_MASK << TD_SOFT_SHIFT)) | TD_EXEC) +
492 * Get the available physical memory ranges from /memory/reg. These
493 * are only used for kernel dumps, but it may not be wise to do prom
494 * calls in that situation.
496 if ((sz = OF_getproplen(pmem, "reg")) == -1)
497 panic("pmap_bootstrap: getproplen /memory/reg");
498 if (sizeof(sparc64_memreg) < sz)
499 panic("pmap_bootstrap: sparc64_memreg too small");
500 if (OF_getprop(pmem, "reg", sparc64_memreg, sz) == -1)
501 panic("pmap_bootstrap: getprop /memory/reg");
502 sparc64_nmemreg = sz / sizeof(*sparc64_memreg);
505 * Initialize the kernel pmap (which is statically allocated).
506 * NOTE: PMAP_LOCK_INIT() is needed as part of the initialization
507 * but sparc64 start up is not ready to initialize mutexes yet.
508 * It is called in machdep.c.
511 for (i = 0; i < MAXCPU; i++)
512 pm->pm_context[i] = TLB_CTX_KERNEL;
516 * Flush all non-locked TLB entries possibly left over by the
519 tlb_flush_nonlocked();
534 * Map the 4mb tsb pages.
536 for (i = 0; i < tsb_kernel_size; i += PAGE_SIZE_4M) {
537 va = (vm_offset_t)tsb_kernel + i;
538 pa = tsb_kernel_phys + i;
539 data = TD_V | TD_4M | TD_PA(pa) | TD_L | TD_CP | TD_CV |
542 stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) |
543 TLB_TAR_CTX(TLB_CTX_KERNEL));
544 stxa_sync(0, ASI_DTLB_DATA_IN_REG, data);
548 * Set the secondary context to be the kernel context (needed for
549 * fp block operations in the kernel and the cache code).
551 stxa(AA_DMMU_SCXR, ASI_DMMU, TLB_CTX_KERNEL);
558 * Allocate a physical page of memory directly from the phys_avail map.
559 * Can only be called from pmap_bootstrap before avail start and end are
563 pmap_bootstrap_alloc(vm_size_t size)
568 size = round_page(size);
569 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
570 if (phys_avail[i + 1] - phys_avail[i] < size)
573 phys_avail[i] += size;
576 panic("pmap_bootstrap_alloc");
580 * Initialize a vm_page's machine-dependent fields.
583 pmap_page_init(vm_page_t m)
586 TAILQ_INIT(&m->md.tte_list);
587 m->md.color = DCACHE_COLOR(VM_PAGE_TO_PHYS(m));
593 * Initialize the pmap module.
603 for (i = 0; i < translations_size; i++) {
604 addr = translations[i].om_start;
605 size = translations[i].om_size;
606 if (addr < VM_MIN_PROM_ADDRESS || addr > VM_MAX_PROM_ADDRESS)
608 result = vm_map_find(kernel_map, NULL, 0, &addr, size, FALSE,
609 VM_PROT_ALL, VM_PROT_ALL, 0);
610 if (result != KERN_SUCCESS || addr != translations[i].om_start)
611 panic("pmap_init: vm_map_find");
616 * Extract the physical page address associated with the given
617 * map/virtual_address pair.
620 pmap_extract(pmap_t pm, vm_offset_t va)
625 if (pm == kernel_pmap)
626 return (pmap_kextract(va));
628 tp = tsb_tte_lookup(pm, va);
632 pa = TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp));
638 * Atomically extract and hold the physical page with the given
639 * pmap and virtual address pair if that mapping permits the given
643 pmap_extract_and_hold(pmap_t pm, vm_offset_t va, vm_prot_t prot)
649 vm_page_lock_queues();
650 if (pm == kernel_pmap) {
651 if (va >= VM_MIN_DIRECT_ADDRESS) {
653 m = PHYS_TO_VM_PAGE(TLB_DIRECT_TO_PHYS(va));
656 tp = tsb_kvtotte(va);
657 if ((tp->tte_data & TD_V) == 0)
662 tp = tsb_tte_lookup(pm, va);
664 if (tp != NULL && ((tp->tte_data & TD_SW) ||
665 (prot & VM_PROT_WRITE) == 0)) {
666 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
669 vm_page_unlock_queues();
670 if (pm != kernel_pmap)
676 * Extract the physical page address associated with the given kernel virtual
680 pmap_kextract(vm_offset_t va)
684 if (va >= VM_MIN_DIRECT_ADDRESS)
685 return (TLB_DIRECT_TO_PHYS(va));
686 tp = tsb_kvtotte(va);
687 if ((tp->tte_data & TD_V) == 0)
689 return (TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp)));
693 pmap_cache_enter(vm_page_t m, vm_offset_t va)
698 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
699 KASSERT((m->flags & PG_FICTITIOUS) == 0,
700 ("pmap_cache_enter: fake page"));
701 PMAP_STATS_INC(pmap_ncache_enter);
704 * Find the color for this virtual address and note the added mapping.
706 color = DCACHE_COLOR(va);
707 m->md.colors[color]++;
710 * If all existing mappings have the same color, the mapping is
713 if (m->md.color == color) {
714 KASSERT(m->md.colors[DCACHE_OTHER_COLOR(color)] == 0,
715 ("pmap_cache_enter: cacheable, mappings of other color"));
716 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
717 PMAP_STATS_INC(pmap_ncache_enter_c);
719 PMAP_STATS_INC(pmap_ncache_enter_oc);
724 * If there are no mappings of the other color, and the page still has
725 * the wrong color, this must be a new mapping. Change the color to
726 * match the new mapping, which is cacheable. We must flush the page
727 * from the cache now.
729 if (m->md.colors[DCACHE_OTHER_COLOR(color)] == 0) {
730 KASSERT(m->md.colors[color] == 1,
731 ("pmap_cache_enter: changing color, not new mapping"));
732 dcache_page_inval(VM_PAGE_TO_PHYS(m));
734 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
735 PMAP_STATS_INC(pmap_ncache_enter_cc);
737 PMAP_STATS_INC(pmap_ncache_enter_coc);
742 * If the mapping is already non-cacheable, just return.
744 if (m->md.color == -1) {
745 PMAP_STATS_INC(pmap_ncache_enter_nc);
749 PMAP_STATS_INC(pmap_ncache_enter_cnc);
752 * Mark all mappings as uncacheable, flush any lines with the other
753 * color out of the dcache, and set the color to none (-1).
755 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
756 atomic_clear_long(&tp->tte_data, TD_CV);
757 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
759 dcache_page_inval(VM_PAGE_TO_PHYS(m));
765 pmap_cache_remove(vm_page_t m, vm_offset_t va)
770 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
771 CTR3(KTR_PMAP, "pmap_cache_remove: m=%p va=%#lx c=%d", m, va,
772 m->md.colors[DCACHE_COLOR(va)]);
773 KASSERT((m->flags & PG_FICTITIOUS) == 0,
774 ("pmap_cache_remove: fake page"));
775 KASSERT(m->md.colors[DCACHE_COLOR(va)] > 0,
776 ("pmap_cache_remove: no mappings %d <= 0",
777 m->md.colors[DCACHE_COLOR(va)]));
778 PMAP_STATS_INC(pmap_ncache_remove);
781 * Find the color for this virtual address and note the removal of
784 color = DCACHE_COLOR(va);
785 m->md.colors[color]--;
788 * If the page is cacheable, just return and keep the same color, even
789 * if there are no longer any mappings.
791 if (m->md.color != -1) {
792 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
793 PMAP_STATS_INC(pmap_ncache_remove_c);
795 PMAP_STATS_INC(pmap_ncache_remove_oc);
799 KASSERT(m->md.colors[DCACHE_OTHER_COLOR(color)] != 0,
800 ("pmap_cache_remove: uncacheable, no mappings of other color"));
803 * If the page is not cacheable (color is -1), and the number of
804 * mappings for this color is not zero, just return. There are
805 * mappings of the other color still, so remain non-cacheable.
807 if (m->md.colors[color] != 0) {
808 PMAP_STATS_INC(pmap_ncache_remove_nc);
813 * The number of mappings for this color is now zero. Recache the
814 * other colored mappings, and change the page color to the other
815 * color. There should be no lines in the data cache for this page,
816 * so flushing should not be needed.
818 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
819 atomic_set_long(&tp->tte_data, TD_CV);
820 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
822 m->md.color = DCACHE_OTHER_COLOR(color);
824 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
825 PMAP_STATS_INC(pmap_ncache_remove_cc);
827 PMAP_STATS_INC(pmap_ncache_remove_coc);
831 * Map a wired page into kernel virtual address space.
834 pmap_kenter(vm_offset_t va, vm_page_t m)
841 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
842 PMAP_STATS_INC(pmap_nkenter);
843 tp = tsb_kvtotte(va);
844 CTR4(KTR_PMAP, "pmap_kenter: va=%#lx pa=%#lx tp=%p data=%#lx",
845 va, VM_PAGE_TO_PHYS(m), tp, tp->tte_data);
846 if (DCACHE_COLOR(VM_PAGE_TO_PHYS(m)) != DCACHE_COLOR(va)) {
848 "pmap_kenter: off colour va=%#lx pa=%#lx o=%p ot=%d pi=%#lx",
849 va, VM_PAGE_TO_PHYS(m), m->object,
850 m->object ? m->object->type : -1,
852 PMAP_STATS_INC(pmap_nkenter_oc);
854 if ((tp->tte_data & TD_V) != 0) {
855 om = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
856 ova = TTE_GET_VA(tp);
857 if (m == om && va == ova) {
858 PMAP_STATS_INC(pmap_nkenter_stupid);
861 TAILQ_REMOVE(&om->md.tte_list, tp, tte_link);
862 pmap_cache_remove(om, ova);
864 tlb_page_demap(kernel_pmap, ova);
866 data = TD_V | TD_8K | VM_PAGE_TO_PHYS(m) | TD_REF | TD_SW | TD_CP |
868 if (pmap_cache_enter(m, va) != 0)
870 tp->tte_vpn = TV_VPN(va, TS_8K);
872 TAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link);
876 * Map a wired page into kernel virtual address space. This additionally
877 * takes a flag argument wich is or'ed to the TTE data. This is used by
879 * NOTE: if the mapping is non-cacheable, it's the caller's responsibility
880 * to flush entries that might still be in the cache, if applicable.
883 pmap_kenter_flags(vm_offset_t va, vm_paddr_t pa, u_long flags)
887 tp = tsb_kvtotte(va);
888 CTR4(KTR_PMAP, "pmap_kenter_flags: va=%#lx pa=%#lx tp=%p data=%#lx",
889 va, pa, tp, tp->tte_data);
890 tp->tte_vpn = TV_VPN(va, TS_8K);
891 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_P | flags;
895 * Remove a wired page from kernel virtual address space.
898 pmap_kremove(vm_offset_t va)
903 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
904 PMAP_STATS_INC(pmap_nkremove);
905 tp = tsb_kvtotte(va);
906 CTR3(KTR_PMAP, "pmap_kremove: va=%#lx tp=%p data=%#lx", va, tp,
908 if ((tp->tte_data & TD_V) == 0)
910 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
911 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
912 pmap_cache_remove(m, va);
917 * Inverse of pmap_kenter_flags, used by bus_space_unmap().
920 pmap_kremove_flags(vm_offset_t va)
924 tp = tsb_kvtotte(va);
925 CTR3(KTR_PMAP, "pmap_kremove: va=%#lx tp=%p data=%#lx", va, tp,
931 * Map a range of physical addresses into kernel virtual address space.
933 * The value passed in *virt is a suggested virtual address for the mapping.
934 * Architectures which can support a direct-mapped physical to virtual region
935 * can return the appropriate address within that region, leaving '*virt'
939 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
942 return (TLB_PHYS_TO_DIRECT(start));
946 * Map a list of wired pages into kernel virtual address space. This is
947 * intended for temporary mappings which do not need page modification or
948 * references recorded. Existing mappings in the region are overwritten.
951 pmap_qenter(vm_offset_t sva, vm_page_t *m, int count)
956 PMAP_STATS_INC(pmap_nqenter);
958 if (!(locked = mtx_owned(&vm_page_queue_mtx)))
959 vm_page_lock_queues();
960 while (count-- > 0) {
966 vm_page_unlock_queues();
967 tlb_range_demap(kernel_pmap, sva, va);
971 * Remove page mappings from kernel virtual address space. Intended for
972 * temporary mappings entered by pmap_qenter.
975 pmap_qremove(vm_offset_t sva, int count)
980 PMAP_STATS_INC(pmap_nqremove);
982 if (!(locked = mtx_owned(&vm_page_queue_mtx)))
983 vm_page_lock_queues();
984 while (count-- > 0) {
989 vm_page_unlock_queues();
990 tlb_range_demap(kernel_pmap, sva, va);
994 * Initialize the pmap associated with process 0.
997 pmap_pinit0(pmap_t pm)
1002 for (i = 0; i < MAXCPU; i++)
1003 pm->pm_context[i] = 0;
1006 pm->pm_tsb_obj = NULL;
1007 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1011 * Initialize a preallocated and zeroed pmap structure, such as one in a
1012 * vmspace structure.
1015 pmap_pinit(pmap_t pm)
1017 vm_page_t ma[TSB_PAGES];
1024 * Allocate kva space for the tsb.
1026 if (pm->pm_tsb == NULL) {
1027 pm->pm_tsb = (struct tte *)kmem_alloc_nofault(kernel_map,
1029 if (pm->pm_tsb == NULL) {
1030 PMAP_LOCK_DESTROY(pm);
1036 * Allocate an object for it.
1038 if (pm->pm_tsb_obj == NULL)
1039 pm->pm_tsb_obj = vm_object_allocate(OBJT_DEFAULT, TSB_PAGES);
1041 VM_OBJECT_LOCK(pm->pm_tsb_obj);
1042 for (i = 0; i < TSB_PAGES; i++) {
1043 m = vm_page_grab(pm->pm_tsb_obj, i, VM_ALLOC_NOBUSY |
1044 VM_ALLOC_RETRY | VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1045 m->valid = VM_PAGE_BITS_ALL;
1049 VM_OBJECT_UNLOCK(pm->pm_tsb_obj);
1050 pmap_qenter((vm_offset_t)pm->pm_tsb, ma, TSB_PAGES);
1052 for (i = 0; i < MAXCPU; i++)
1053 pm->pm_context[i] = -1;
1055 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1060 * Release any resources held by the given physical map.
1061 * Called when a pmap initialized by pmap_pinit is being released.
1062 * Should only be called if the map contains no valid mappings.
1065 pmap_release(pmap_t pm)
1071 CTR2(KTR_PMAP, "pmap_release: ctx=%#x tsb=%p",
1072 pm->pm_context[PCPU_GET(cpuid)], pm->pm_tsb);
1073 KASSERT(pmap_resident_count(pm) == 0,
1074 ("pmap_release: resident pages %ld != 0",
1075 pmap_resident_count(pm)));
1078 * After the pmap was freed, it might be reallocated to a new process.
1079 * When switching, this might lead us to wrongly assume that we need
1080 * not switch contexts because old and new pmap pointer are equal.
1081 * Therefore, make sure that this pmap is not referenced by any PCPU
1082 * pointer any more. This could happen in two cases:
1083 * - A process that referenced the pmap is currently exiting on a CPU.
1084 * However, it is guaranteed to not switch in any more after setting
1085 * its state to PRS_ZOMBIE.
1086 * - A process that referenced this pmap ran on a CPU, but we switched
1087 * to a kernel thread, leaving the pmap pointer unchanged.
1089 mtx_lock_spin(&sched_lock);
1090 SLIST_FOREACH(pc, &cpuhead, pc_allcpu) {
1091 if (pc->pc_pmap == pm)
1094 mtx_unlock_spin(&sched_lock);
1096 obj = pm->pm_tsb_obj;
1097 VM_OBJECT_LOCK(obj);
1098 KASSERT(obj->ref_count == 1, ("pmap_release: tsbobj ref count != 1"));
1099 while (!TAILQ_EMPTY(&obj->memq)) {
1100 m = TAILQ_FIRST(&obj->memq);
1101 vm_page_lock_queues();
1102 if (vm_page_sleep_if_busy(m, FALSE, "pmaprl"))
1104 KASSERT(m->hold_count == 0,
1105 ("pmap_release: freeing held tsb page"));
1108 atomic_subtract_int(&cnt.v_wire_count, 1);
1109 vm_page_free_zero(m);
1110 vm_page_unlock_queues();
1112 VM_OBJECT_UNLOCK(obj);
1113 pmap_qremove((vm_offset_t)pm->pm_tsb, TSB_PAGES);
1114 PMAP_LOCK_DESTROY(pm);
1118 * Grow the number of kernel page table entries. Unneeded.
1121 pmap_growkernel(vm_offset_t addr)
1124 panic("pmap_growkernel: can't grow kernel");
1128 pmap_remove_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp,
1134 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1135 data = atomic_readandclear_long(&tp->tte_data);
1136 if ((data & TD_FAKE) == 0) {
1137 m = PHYS_TO_VM_PAGE(TD_PA(data));
1138 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1139 if ((data & TD_WIRED) != 0)
1140 pm->pm_stats.wired_count--;
1141 if ((data & TD_PV) != 0) {
1142 if ((data & TD_W) != 0)
1144 if ((data & TD_REF) != 0)
1145 vm_page_flag_set(m, PG_REFERENCED);
1146 if (TAILQ_EMPTY(&m->md.tte_list))
1147 vm_page_flag_clear(m, PG_WRITEABLE);
1148 pm->pm_stats.resident_count--;
1150 pmap_cache_remove(m, va);
1153 if (PMAP_REMOVE_DONE(pm))
1159 * Remove the given range of addresses from the specified map.
1162 pmap_remove(pmap_t pm, vm_offset_t start, vm_offset_t end)
1167 CTR3(KTR_PMAP, "pmap_remove: ctx=%#lx start=%#lx end=%#lx",
1168 pm->pm_context[PCPU_GET(cpuid)], start, end);
1169 if (PMAP_REMOVE_DONE(pm))
1171 vm_page_lock_queues();
1173 if (end - start > PMAP_TSB_THRESH) {
1174 tsb_foreach(pm, NULL, start, end, pmap_remove_tte);
1175 tlb_context_demap(pm);
1177 for (va = start; va < end; va += PAGE_SIZE) {
1178 if ((tp = tsb_tte_lookup(pm, va)) != NULL) {
1179 if (!pmap_remove_tte(pm, NULL, tp, va))
1183 tlb_range_demap(pm, start, end - 1);
1186 vm_page_unlock_queues();
1190 pmap_remove_all(vm_page_t m)
1197 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1198 for (tp = TAILQ_FIRST(&m->md.tte_list); tp != NULL; tp = tpn) {
1199 tpn = TAILQ_NEXT(tp, tte_link);
1200 if ((tp->tte_data & TD_PV) == 0)
1202 pm = TTE_GET_PMAP(tp);
1203 va = TTE_GET_VA(tp);
1205 if ((tp->tte_data & TD_WIRED) != 0)
1206 pm->pm_stats.wired_count--;
1207 if ((tp->tte_data & TD_REF) != 0)
1208 vm_page_flag_set(m, PG_REFERENCED);
1209 if ((tp->tte_data & TD_W) != 0)
1211 tp->tte_data &= ~TD_V;
1212 tlb_page_demap(pm, va);
1213 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1214 pm->pm_stats.resident_count--;
1215 pmap_cache_remove(m, va);
1219 vm_page_flag_clear(m, PG_WRITEABLE);
1223 pmap_protect_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp,
1229 data = atomic_clear_long(&tp->tte_data, TD_REF | TD_SW | TD_W);
1230 if ((data & TD_PV) != 0) {
1231 m = PHYS_TO_VM_PAGE(TD_PA(data));
1232 if ((data & TD_REF) != 0)
1233 vm_page_flag_set(m, PG_REFERENCED);
1234 if ((data & TD_W) != 0)
1241 * Set the physical protection on the specified range of this map as requested.
1244 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
1249 CTR4(KTR_PMAP, "pmap_protect: ctx=%#lx sva=%#lx eva=%#lx prot=%#lx",
1250 pm->pm_context[PCPU_GET(cpuid)], sva, eva, prot);
1252 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1253 pmap_remove(pm, sva, eva);
1257 if (prot & VM_PROT_WRITE)
1260 vm_page_lock_queues();
1262 if (eva - sva > PMAP_TSB_THRESH) {
1263 tsb_foreach(pm, NULL, sva, eva, pmap_protect_tte);
1264 tlb_context_demap(pm);
1266 for (va = sva; va < eva; va += PAGE_SIZE) {
1267 if ((tp = tsb_tte_lookup(pm, va)) != NULL)
1268 pmap_protect_tte(pm, NULL, tp, va);
1270 tlb_range_demap(pm, sva, eva - 1);
1273 vm_page_unlock_queues();
1277 * Map the given physical page at the specified virtual address in the
1278 * target pmap with the protection requested. If specified the page
1279 * will be wired down.
1282 pmap_enter(pmap_t pm, vm_offset_t va, vm_prot_t access, vm_page_t m,
1283 vm_prot_t prot, boolean_t wired)
1286 vm_page_lock_queues();
1288 pmap_enter_locked(pm, va, m, prot, wired);
1289 vm_page_unlock_queues();
1294 * Map the given physical page at the specified virtual address in the
1295 * target pmap with the protection requested. If specified the page
1296 * will be wired down.
1298 * The page queues and pmap must be locked.
1301 pmap_enter_locked(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1309 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1310 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1311 PMAP_STATS_INC(pmap_nenter);
1312 pa = VM_PAGE_TO_PHYS(m);
1315 * If this is a fake page from the device_pager, but it covers actual
1316 * physical memory, convert to the real backing page.
1318 if ((m->flags & PG_FICTITIOUS) != 0) {
1319 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1320 if (pa >= phys_avail[i] && pa <= phys_avail[i + 1]) {
1321 m = PHYS_TO_VM_PAGE(pa);
1328 "pmap_enter: ctx=%p m=%p va=%#lx pa=%#lx prot=%#x wired=%d",
1329 pm->pm_context[PCPU_GET(cpuid)], m, va, pa, prot, wired);
1332 * If there is an existing mapping, and the physical address has not
1333 * changed, must be protection or wiring change.
1335 if ((tp = tsb_tte_lookup(pm, va)) != NULL && TTE_GET_PA(tp) == pa) {
1336 CTR0(KTR_PMAP, "pmap_enter: update");
1337 PMAP_STATS_INC(pmap_nenter_update);
1340 * Wiring change, just update stats.
1343 if ((tp->tte_data & TD_WIRED) == 0) {
1344 tp->tte_data |= TD_WIRED;
1345 pm->pm_stats.wired_count++;
1348 if ((tp->tte_data & TD_WIRED) != 0) {
1349 tp->tte_data &= ~TD_WIRED;
1350 pm->pm_stats.wired_count--;
1355 * Save the old bits and clear the ones we're interested in.
1357 data = tp->tte_data;
1358 tp->tte_data &= ~(TD_EXEC | TD_SW | TD_W);
1361 * If we're turning off write permissions, sense modify status.
1363 if ((prot & VM_PROT_WRITE) != 0) {
1364 tp->tte_data |= TD_SW;
1366 tp->tte_data |= TD_W;
1368 vm_page_flag_set(m, PG_WRITEABLE);
1369 } else if ((data & TD_W) != 0) {
1374 * If we're turning on execute permissions, flush the icache.
1376 if ((prot & VM_PROT_EXECUTE) != 0) {
1377 if ((data & TD_EXEC) == 0) {
1378 icache_page_inval(pa);
1380 tp->tte_data |= TD_EXEC;
1384 * Delete the old mapping.
1386 tlb_page_demap(pm, TTE_GET_VA(tp));
1389 * If there is an existing mapping, but its for a different
1390 * phsyical address, delete the old mapping.
1393 CTR0(KTR_PMAP, "pmap_enter: replace");
1394 PMAP_STATS_INC(pmap_nenter_replace);
1395 pmap_remove_tte(pm, NULL, tp, va);
1396 tlb_page_demap(pm, va);
1398 CTR0(KTR_PMAP, "pmap_enter: new");
1399 PMAP_STATS_INC(pmap_nenter_new);
1403 * Now set up the data and install the new mapping.
1405 data = TD_V | TD_8K | TD_PA(pa);
1406 if (pm == kernel_pmap)
1408 if ((prot & VM_PROT_WRITE) != 0) {
1410 vm_page_flag_set(m, PG_WRITEABLE);
1412 if (prot & VM_PROT_EXECUTE) {
1414 icache_page_inval(pa);
1418 * If its wired update stats. We also don't need reference or
1419 * modify tracking for wired mappings, so set the bits now.
1422 pm->pm_stats.wired_count++;
1423 data |= TD_REF | TD_WIRED;
1424 if ((prot & VM_PROT_WRITE) != 0)
1428 tsb_tte_enter(pm, m, va, TS_8K, data);
1433 * Maps a sequence of resident pages belonging to the same object.
1434 * The sequence begins with the given page m_start. This page is
1435 * mapped at the given virtual address start. Each subsequent page is
1436 * mapped at a virtual address that is offset from start by the same
1437 * amount as the page is offset from m_start within the object. The
1438 * last page in the sequence is the page with the largest offset from
1439 * m_start that can be mapped at a virtual address less than the given
1440 * virtual address end. Not every virtual page between start and end
1441 * is mapped; only those for which a resident page exists with the
1442 * corresponding offset from m_start are mapped.
1445 pmap_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end,
1446 vm_page_t m_start, vm_prot_t prot)
1449 vm_pindex_t diff, psize;
1451 psize = atop(end - start);
1454 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1455 pmap_enter_locked(pm, start + ptoa(diff), m, prot &
1456 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1457 m = TAILQ_NEXT(m, listq);
1463 pmap_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot)
1467 pmap_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1473 pmap_object_init_pt(pmap_t pm, vm_offset_t addr, vm_object_t object,
1474 vm_pindex_t pindex, vm_size_t size)
1477 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
1478 KASSERT(object->type == OBJT_DEVICE,
1479 ("pmap_object_init_pt: non-device object"));
1483 * Change the wiring attribute for a map/virtual-address pair.
1484 * The mapping must already exist in the pmap.
1487 pmap_change_wiring(pmap_t pm, vm_offset_t va, boolean_t wired)
1493 if ((tp = tsb_tte_lookup(pm, va)) != NULL) {
1495 data = atomic_set_long(&tp->tte_data, TD_WIRED);
1496 if ((data & TD_WIRED) == 0)
1497 pm->pm_stats.wired_count++;
1499 data = atomic_clear_long(&tp->tte_data, TD_WIRED);
1500 if ((data & TD_WIRED) != 0)
1501 pm->pm_stats.wired_count--;
1508 pmap_copy_tte(pmap_t src_pmap, pmap_t dst_pmap, struct tte *tp, vm_offset_t va)
1513 if ((tp->tte_data & TD_FAKE) != 0)
1515 if (tsb_tte_lookup(dst_pmap, va) == NULL) {
1516 data = tp->tte_data &
1517 ~(TD_PV | TD_REF | TD_SW | TD_CV | TD_W);
1518 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
1519 tsb_tte_enter(dst_pmap, m, va, TS_8K, data);
1525 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
1526 vm_size_t len, vm_offset_t src_addr)
1531 if (dst_addr != src_addr)
1533 vm_page_lock_queues();
1534 if (dst_pmap < src_pmap) {
1535 PMAP_LOCK(dst_pmap);
1536 PMAP_LOCK(src_pmap);
1538 PMAP_LOCK(src_pmap);
1539 PMAP_LOCK(dst_pmap);
1541 if (len > PMAP_TSB_THRESH) {
1542 tsb_foreach(src_pmap, dst_pmap, src_addr, src_addr + len,
1544 tlb_context_demap(dst_pmap);
1546 for (va = src_addr; va < src_addr + len; va += PAGE_SIZE) {
1547 if ((tp = tsb_tte_lookup(src_pmap, va)) != NULL)
1548 pmap_copy_tte(src_pmap, dst_pmap, tp, va);
1550 tlb_range_demap(dst_pmap, src_addr, src_addr + len - 1);
1552 vm_page_unlock_queues();
1553 PMAP_UNLOCK(src_pmap);
1554 PMAP_UNLOCK(dst_pmap);
1558 pmap_zero_page(vm_page_t m)
1564 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1565 ("pmap_zero_page: fake page"));
1566 PMAP_STATS_INC(pmap_nzero_page);
1567 pa = VM_PAGE_TO_PHYS(m);
1568 if (m->md.color == -1) {
1569 PMAP_STATS_INC(pmap_nzero_page_nc);
1570 aszero(ASI_PHYS_USE_EC, pa, PAGE_SIZE);
1571 } else if (m->md.color == DCACHE_COLOR(pa)) {
1572 PMAP_STATS_INC(pmap_nzero_page_c);
1573 va = TLB_PHYS_TO_DIRECT(pa);
1574 cpu_block_zero((void *)va, PAGE_SIZE);
1576 PMAP_STATS_INC(pmap_nzero_page_oc);
1577 PMAP_LOCK(kernel_pmap);
1578 va = pmap_temp_map_1 + (m->md.color * PAGE_SIZE);
1579 tp = tsb_kvtotte(va);
1580 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1581 tp->tte_vpn = TV_VPN(va, TS_8K);
1582 cpu_block_zero((void *)va, PAGE_SIZE);
1583 tlb_page_demap(kernel_pmap, va);
1584 PMAP_UNLOCK(kernel_pmap);
1589 pmap_zero_page_area(vm_page_t m, int off, int size)
1595 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1596 ("pmap_zero_page_area: fake page"));
1597 KASSERT(off + size <= PAGE_SIZE, ("pmap_zero_page_area: bad off/size"));
1598 PMAP_STATS_INC(pmap_nzero_page_area);
1599 pa = VM_PAGE_TO_PHYS(m);
1600 if (m->md.color == -1) {
1601 PMAP_STATS_INC(pmap_nzero_page_area_nc);
1602 aszero(ASI_PHYS_USE_EC, pa + off, size);
1603 } else if (m->md.color == DCACHE_COLOR(pa)) {
1604 PMAP_STATS_INC(pmap_nzero_page_area_c);
1605 va = TLB_PHYS_TO_DIRECT(pa);
1606 bzero((void *)(va + off), size);
1608 PMAP_STATS_INC(pmap_nzero_page_area_oc);
1609 PMAP_LOCK(kernel_pmap);
1610 va = pmap_temp_map_1 + (m->md.color * PAGE_SIZE);
1611 tp = tsb_kvtotte(va);
1612 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1613 tp->tte_vpn = TV_VPN(va, TS_8K);
1614 bzero((void *)(va + off), size);
1615 tlb_page_demap(kernel_pmap, va);
1616 PMAP_UNLOCK(kernel_pmap);
1621 pmap_zero_page_idle(vm_page_t m)
1627 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1628 ("pmap_zero_page_idle: fake page"));
1629 PMAP_STATS_INC(pmap_nzero_page_idle);
1630 pa = VM_PAGE_TO_PHYS(m);
1631 if (m->md.color == -1) {
1632 PMAP_STATS_INC(pmap_nzero_page_idle_nc);
1633 aszero(ASI_PHYS_USE_EC, pa, PAGE_SIZE);
1634 } else if (m->md.color == DCACHE_COLOR(pa)) {
1635 PMAP_STATS_INC(pmap_nzero_page_idle_c);
1636 va = TLB_PHYS_TO_DIRECT(pa);
1637 cpu_block_zero((void *)va, PAGE_SIZE);
1639 PMAP_STATS_INC(pmap_nzero_page_idle_oc);
1640 va = pmap_idle_map + (m->md.color * PAGE_SIZE);
1641 tp = tsb_kvtotte(va);
1642 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1643 tp->tte_vpn = TV_VPN(va, TS_8K);
1644 cpu_block_zero((void *)va, PAGE_SIZE);
1645 tlb_page_demap(kernel_pmap, va);
1650 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
1658 KASSERT((mdst->flags & PG_FICTITIOUS) == 0,
1659 ("pmap_copy_page: fake dst page"));
1660 KASSERT((msrc->flags & PG_FICTITIOUS) == 0,
1661 ("pmap_copy_page: fake src page"));
1662 PMAP_STATS_INC(pmap_ncopy_page);
1663 pdst = VM_PAGE_TO_PHYS(mdst);
1664 psrc = VM_PAGE_TO_PHYS(msrc);
1665 if (msrc->md.color == -1 && mdst->md.color == -1) {
1666 PMAP_STATS_INC(pmap_ncopy_page_nc);
1667 ascopy(ASI_PHYS_USE_EC, psrc, pdst, PAGE_SIZE);
1668 } else if (msrc->md.color == DCACHE_COLOR(psrc) &&
1669 mdst->md.color == DCACHE_COLOR(pdst)) {
1670 PMAP_STATS_INC(pmap_ncopy_page_c);
1671 vdst = TLB_PHYS_TO_DIRECT(pdst);
1672 vsrc = TLB_PHYS_TO_DIRECT(psrc);
1673 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE);
1674 } else if (msrc->md.color == -1) {
1675 if (mdst->md.color == DCACHE_COLOR(pdst)) {
1676 PMAP_STATS_INC(pmap_ncopy_page_dc);
1677 vdst = TLB_PHYS_TO_DIRECT(pdst);
1678 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst,
1681 PMAP_STATS_INC(pmap_ncopy_page_doc);
1682 PMAP_LOCK(kernel_pmap);
1683 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE);
1684 tp = tsb_kvtotte(vdst);
1686 TD_V | TD_8K | TD_PA(pdst) | TD_CP | TD_CV | TD_W;
1687 tp->tte_vpn = TV_VPN(vdst, TS_8K);
1688 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst,
1690 tlb_page_demap(kernel_pmap, vdst);
1691 PMAP_UNLOCK(kernel_pmap);
1693 } else if (mdst->md.color == -1) {
1694 if (msrc->md.color == DCACHE_COLOR(psrc)) {
1695 PMAP_STATS_INC(pmap_ncopy_page_sc);
1696 vsrc = TLB_PHYS_TO_DIRECT(psrc);
1697 ascopyto((void *)vsrc, ASI_PHYS_USE_EC, pdst,
1700 PMAP_STATS_INC(pmap_ncopy_page_soc);
1701 PMAP_LOCK(kernel_pmap);
1702 vsrc = pmap_temp_map_1 + (msrc->md.color * PAGE_SIZE);
1703 tp = tsb_kvtotte(vsrc);
1705 TD_V | TD_8K | TD_PA(psrc) | TD_CP | TD_CV | TD_W;
1706 tp->tte_vpn = TV_VPN(vsrc, TS_8K);
1707 ascopyto((void *)vsrc, ASI_PHYS_USE_EC, pdst,
1709 tlb_page_demap(kernel_pmap, vsrc);
1710 PMAP_UNLOCK(kernel_pmap);
1713 PMAP_STATS_INC(pmap_ncopy_page_oc);
1714 PMAP_LOCK(kernel_pmap);
1715 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE);
1716 tp = tsb_kvtotte(vdst);
1718 TD_V | TD_8K | TD_PA(pdst) | TD_CP | TD_CV | TD_W;
1719 tp->tte_vpn = TV_VPN(vdst, TS_8K);
1720 vsrc = pmap_temp_map_2 + (msrc->md.color * PAGE_SIZE);
1721 tp = tsb_kvtotte(vsrc);
1723 TD_V | TD_8K | TD_PA(psrc) | TD_CP | TD_CV | TD_W;
1724 tp->tte_vpn = TV_VPN(vsrc, TS_8K);
1725 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE);
1726 tlb_page_demap(kernel_pmap, vdst);
1727 tlb_page_demap(kernel_pmap, vsrc);
1728 PMAP_UNLOCK(kernel_pmap);
1733 * Returns true if the pmap's pv is one of the first
1734 * 16 pvs linked to from this page. This count may
1735 * be changed upwards or downwards in the future; it
1736 * is only necessary that true be returned for a small
1737 * subset of pmaps for proper page aging.
1740 pmap_page_exists_quick(pmap_t pm, vm_page_t m)
1745 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1746 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1749 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1750 if ((tp->tte_data & TD_PV) == 0)
1752 if (TTE_GET_PMAP(tp) == pm)
1761 * Return the number of managed mappings to the given physical page
1765 pmap_page_wired_mappings(vm_page_t m)
1771 if ((m->flags & PG_FICTITIOUS) != 0)
1773 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1774 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link)
1775 if ((tp->tte_data & (TD_PV | TD_WIRED)) == (TD_PV | TD_WIRED))
1781 * Remove all pages from specified address space, this aids process exit
1782 * speeds. This is much faster than pmap_remove n the case of running down
1783 * an entire address space. Only works for the current pmap.
1786 pmap_remove_pages(pmap_t pm)
1791 * Returns TRUE if the given page has a managed mapping.
1794 pmap_page_is_mapped(vm_page_t m)
1798 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1800 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1801 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1802 if ((tp->tte_data & TD_PV) != 0)
1809 * pmap_ts_referenced:
1811 * Return a count of reference bits for a page, clearing those bits.
1812 * It is not necessary for every reference bit to be cleared, but it
1813 * is necessary that 0 only be returned when there are truly no
1814 * reference bits set.
1816 * XXX: The exact number of bits to check and clear is a matter that
1817 * should be tested and standardized at some point in the future for
1818 * optimal aging of shared pages.
1822 pmap_ts_referenced(vm_page_t m)
1830 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1831 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1834 if ((tp = TAILQ_FIRST(&m->md.tte_list)) != NULL) {
1837 tpn = TAILQ_NEXT(tp, tte_link);
1838 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1839 TAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link);
1840 if ((tp->tte_data & TD_PV) == 0)
1842 data = atomic_clear_long(&tp->tte_data, TD_REF);
1843 if ((data & TD_REF) != 0 && ++count > 4)
1845 } while ((tp = tpn) != NULL && tp != tpf);
1851 pmap_is_modified(vm_page_t m)
1855 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1856 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1858 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1859 if ((tp->tte_data & TD_PV) == 0)
1861 if ((tp->tte_data & TD_W) != 0)
1868 * pmap_is_prefaultable:
1870 * Return whether or not the specified virtual address is elgible
1874 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
1881 pmap_clear_modify(vm_page_t m)
1886 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1887 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1889 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1890 if ((tp->tte_data & TD_PV) == 0)
1892 data = atomic_clear_long(&tp->tte_data, TD_W);
1893 if ((data & TD_W) != 0)
1894 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1899 pmap_clear_reference(vm_page_t m)
1904 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1905 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1907 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1908 if ((tp->tte_data & TD_PV) == 0)
1910 data = atomic_clear_long(&tp->tte_data, TD_REF);
1911 if ((data & TD_REF) != 0)
1912 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1917 pmap_remove_write(vm_page_t m)
1922 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1923 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 ||
1924 (m->flags & PG_WRITEABLE) == 0)
1926 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1927 if ((tp->tte_data & TD_PV) == 0)
1929 data = atomic_clear_long(&tp->tte_data, TD_SW | TD_W);
1930 if ((data & TD_W) != 0) {
1932 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1935 vm_page_flag_clear(m, PG_WRITEABLE);
1939 pmap_mincore(pmap_t pm, vm_offset_t addr)
1947 * Activate a user pmap. The pmap must be activated before its address space
1948 * can be accessed in any way.
1951 pmap_activate(struct thread *td)
1957 vm = td->td_proc->p_vmspace;
1958 pm = vmspace_pmap(vm);
1960 mtx_lock_spin(&sched_lock);
1962 context = PCPU_GET(tlb_ctx);
1963 if (context == PCPU_GET(tlb_ctx_max)) {
1965 context = PCPU_GET(tlb_ctx_min);
1967 PCPU_SET(tlb_ctx, context + 1);
1969 pm->pm_context[PCPU_GET(cpuid)] = context;
1970 pm->pm_active |= PCPU_GET(cpumask);
1973 stxa(AA_DMMU_TSB, ASI_DMMU, pm->pm_tsb);
1974 stxa(AA_IMMU_TSB, ASI_IMMU, pm->pm_tsb);
1975 stxa(AA_DMMU_PCXR, ASI_DMMU, context);
1978 mtx_unlock_spin(&sched_lock);
1982 pmap_addr_hint(vm_object_t object, vm_offset_t va, vm_size_t size)