2 * Copyright (c) 2003 Jake Burkholder.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/mutex.h>
37 #include <sys/sysctl.h>
42 #include <machine/cache.h>
43 #include <machine/cpufunc.h>
44 #include <machine/lsu.h>
45 #include <machine/smp.h>
46 #include <machine/tlb.h>
48 #define SPITFIRE_TLB_ENTRIES 64
50 PMAP_STATS_VAR(spitfire_dcache_npage_inval);
51 PMAP_STATS_VAR(spitfire_dcache_npage_inval_match);
52 PMAP_STATS_VAR(spitfire_icache_npage_inval);
53 PMAP_STATS_VAR(spitfire_icache_npage_inval_match);
56 * Enable the level 1 caches.
59 spitfire_cache_enable(u_int cpu_impl __unused)
63 lsu = ldxa(0, ASI_LSU_CTL_REG);
64 stxa_sync(0, ASI_LSU_CTL_REG, lsu | LSU_IC | LSU_DC);
68 * Flush all lines from the level 1 caches.
71 spitfire_cache_flush(void)
75 for (addr = 0; addr < PCPU_GET(cache.dc_size);
76 addr += PCPU_GET(cache.dc_linesize))
77 stxa_sync(addr, ASI_DCACHE_TAG, 0);
78 for (addr = 0; addr < PCPU_GET(cache.ic_size);
79 addr += PCPU_GET(cache.ic_linesize))
80 stxa_sync(addr, ASI_ICACHE_TAG, 0);
84 * Flush a physical page from the data cache.
87 spitfire_dcache_page_inval(vm_paddr_t pa)
94 KASSERT((pa & PAGE_MASK) == 0, ("%s: pa not page aligned", __func__));
95 PMAP_STATS_INC(spitfire_dcache_npage_inval);
96 target = pa >> (PAGE_SHIFT - DC_TAG_SHIFT);
97 cookie = ipi_dcache_page_inval(tl_ipi_spitfire_dcache_page_inval, pa);
98 for (addr = 0; addr < PCPU_GET(cache.dc_size);
99 addr += PCPU_GET(cache.dc_linesize)) {
100 tag = ldxa(addr, ASI_DCACHE_TAG);
101 if (((tag >> DC_VALID_SHIFT) & DC_VALID_MASK) == 0)
103 tag &= DC_TAG_MASK << DC_TAG_SHIFT;
105 PMAP_STATS_INC(spitfire_dcache_npage_inval_match);
106 stxa_sync(addr, ASI_DCACHE_TAG, tag);
113 * Flush a physical page from the instruction cache.
116 spitfire_icache_page_inval(vm_paddr_t pa)
118 register u_long tag __asm("%g1");
123 KASSERT((pa & PAGE_MASK) == 0, ("%s: pa not page aligned", __func__));
124 PMAP_STATS_INC(spitfire_icache_npage_inval);
125 target = pa >> (PAGE_SHIFT - IC_TAG_SHIFT);
126 cookie = ipi_icache_page_inval(tl_ipi_spitfire_icache_page_inval, pa);
127 for (addr = 0; addr < PCPU_GET(cache.ic_size);
128 addr += PCPU_GET(cache.ic_linesize)) {
129 __asm __volatile("ldda [%1] %2, %%g0" /*, %g1 */
130 : "=r" (tag) : "r" (addr), "n" (ASI_ICACHE_TAG));
131 if (((tag >> IC_VALID_SHIFT) & IC_VALID_MASK) == 0)
133 tag &= IC_TAG_MASK << IC_TAG_SHIFT;
135 PMAP_STATS_INC(spitfire_icache_npage_inval_match);
136 stxa_sync(addr, ASI_ICACHE_TAG, tag);
143 * Flush all non-locked mappings from the TLB.
146 spitfire_tlb_flush_nonlocked(void)
150 for (i = 0; i < SPITFIRE_TLB_ENTRIES; i++) {
151 if ((ldxa(TLB_DAR_SLOT(i), ASI_DTLB_DATA_ACCESS_REG) &
153 stxa_sync(TLB_DAR_SLOT(i),
154 ASI_DTLB_DATA_ACCESS_REG, 0);
155 if ((ldxa(TLB_DAR_SLOT(i), ASI_ITLB_DATA_ACCESS_REG) &
157 stxa_sync(TLB_DAR_SLOT(i),
158 ASI_ITLB_DATA_ACCESS_REG, 0);
163 * Flush all user mappings from the TLB.
166 spitfire_tlb_flush_user(void)
172 for (i = 0; i < SPITFIRE_TLB_ENTRIES; i++) {
173 data = ldxa(TLB_DAR_SLOT(i), ASI_DTLB_DATA_ACCESS_REG);
174 tag = ldxa(TLB_DAR_SLOT(i), ASI_DTLB_TAG_READ_REG);
175 if ((data & TD_V) != 0 && (data & TD_L) == 0 &&
176 TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
177 stxa_sync(TLB_DAR_SLOT(i),
178 ASI_DTLB_DATA_ACCESS_REG, 0);
179 data = ldxa(TLB_DAR_SLOT(i), ASI_ITLB_DATA_ACCESS_REG);
180 tag = ldxa(TLB_DAR_SLOT(i), ASI_ITLB_TAG_READ_REG);
181 if ((data & TD_V) != 0 && (data & TD_L) == 0 &&
182 TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
183 stxa_sync(TLB_DAR_SLOT(i),
184 ASI_ITLB_DATA_ACCESS_REG, 0);