2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2010 - 2011 Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <machine/asi.h>
36 #include <machine/cache.h>
37 #include <machine/cpu.h>
38 #include <machine/cpufunc.h>
39 #include <machine/mcntl.h>
40 #include <machine/lsu.h>
41 #include <machine/tlb.h>
42 #include <machine/tte.h>
43 #include <machine/vmparam.h>
45 #define ZEUS_FTLB_ENTRIES 32
46 #define ZEUS_STLB_ENTRIES 2048
49 * CPU-specific initialization for Fujitsu Zeus CPUs
52 zeus_init(u_int cpu_impl)
56 /* Ensure the TSB Extension Registers hold 0 as TSB_Base. */
58 stxa(AA_DMMU_TSB_PEXT_REG, ASI_DMMU, 0);
59 stxa(AA_IMMU_TSB_PEXT_REG, ASI_IMMU, 0);
62 stxa(AA_DMMU_TSB_SEXT_REG, ASI_DMMU, 0);
64 * NB: the secondary context was removed from the iMMU.
68 stxa(AA_DMMU_TSB_NEXT_REG, ASI_DMMU, 0);
69 stxa(AA_IMMU_TSB_NEXT_REG, ASI_IMMU, 0);
72 val = ldxa(AA_MCNTL, ASI_MCNTL);
73 /* Ensure MCNTL_JPS1_TSBP is 0. */
74 val &= ~MCNTL_JPS1_TSBP;
76 * Ensure 4-Mbyte page entries are stored in the 1024-entry, 2-way set
79 val = (val & ~MCNTL_RMD_MASK) | MCNTL_RMD_1024;
80 stxa(AA_MCNTL, ASI_MCNTL, val);
84 * Enable level 1 caches.
87 zeus_cache_enable(u_int cpu_impl)
91 lsu = ldxa(0, ASI_LSU_CTL_REG);
92 stxa(0, ASI_LSU_CTL_REG, lsu | LSU_IC | LSU_DC);
97 * Flush all lines from the level 1 caches.
100 zeus_cache_flush(void)
103 stxa_sync(0, ASI_FLUSH_L1I, 0);
107 * Flush a physical page from the data cache. Data cache consistency is
108 * maintained by hardware.
111 zeus_dcache_page_inval(vm_paddr_t spa __unused)
117 * Flush a physical page from the intsruction cache. Instruction cache
118 * consistency is maintained by hardware.
121 zeus_icache_page_inval(vm_paddr_t pa __unused)
127 * Flush all non-locked mappings from the TLBs.
130 zeus_tlb_flush_nonlocked(void)
133 stxa(TLB_DEMAP_ALL, ASI_DMMU_DEMAP, 0);
134 stxa(TLB_DEMAP_ALL, ASI_IMMU_DEMAP, 0);
139 * Flush all user mappings from the TLBs.
142 zeus_tlb_flush_user(void)
147 for (i = 0; i < ZEUS_FTLB_ENTRIES; i++) {
148 slot = TLB_DAR_SLOT(TLB_DAR_FTLB, i);
149 data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
150 tag = ldxa(slot, ASI_DTLB_TAG_READ_REG);
151 if ((data & TD_V) != 0 && (data & TD_L) == 0 &&
152 TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
153 stxa_sync(slot, ASI_DTLB_DATA_ACCESS_REG, 0);
154 data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
155 tag = ldxa(slot, ASI_ITLB_TAG_READ_REG);
156 if ((data & TD_V) != 0 && (data & TD_L) == 0 &&
157 TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
158 stxa_sync(slot, ASI_ITLB_DATA_ACCESS_REG, 0);
160 for (i = 0; i < ZEUS_STLB_ENTRIES; i++) {
161 slot = TLB_DAR_SLOT(TLB_DAR_STLB, i);
162 data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
163 tag = ldxa(slot, ASI_DTLB_TAG_READ_REG);
164 if ((data & TD_V) != 0 && (data & TD_L) == 0 &&
165 TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
166 stxa_sync(slot, ASI_DTLB_DATA_ACCESS_REG, 0);
167 data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
168 tag = ldxa(slot, ASI_ITLB_TAG_READ_REG);
169 if ((data & TD_V) != 0 && (data & TD_L) == 0 &&
170 TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
171 stxa_sync(slot, ASI_ITLB_DATA_ACCESS_REG, 0);