2 * Copyright (c) 2006 Kip Macy
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef _MACHINE_MMU_H_
31 #define _MACHINE_MMU_H_
34 #define FAST_IMMU_MISS_TT 0x64
35 #define FAST_DMMU_MISS_TT 0x68
36 #define FAST_PROT_TT 0x6c
39 * Constants defining alternate spaces
40 * and register layouts within them,
41 * and a few other interesting assembly constants.
45 * vaddr offsets of various registers
47 #define MMU_PCONTEXT 0x08 /* primary context number */
48 #define MMU_SCONTEXT 0x10 /* secondary context number */
51 * Pseudo Synchronous Fault Status Register Layout
53 * IMMU and DMMU maintain their own pseudo SFSR Register
55 * +------------------------------------------------+
56 * | Reserved | Context | FT |
57 * +----------------------|-------------------------+
61 #define SFSR_FT 0x0000FFFF /* fault type mask */
62 #define SFSR_CTX 0xFFFF0000 /* fault context mask */
65 * Definition of FT (Fault Type) bit field of sfsr.
68 #define FT_PRIV MMFSA_F_PRIV /* privilege violation */
69 #define FT_SPEC_LD MMFSA_F_SOPG /* speculative ld to e page */
70 #define FT_ATOMIC_NC MMFSA_F_NCATM /* atomic to nc page */
71 #define FT_ILL_ALT MMFSA_F_INVASI /* illegal lda/sta */
72 #define FT_NFO MMFSA_F_NFO /* normal access to nfo page */
73 #define FT_RANGE MMFSA_F_INVVA /* dmmu or immu address out of range */
74 #define FT_NEW_FMISS MMFSA_F_FMISS /* fast miss */
75 #define FT_NEW_FPROT MMFSA_F_FPROT /* fast protection */
76 #define FT_NEW_MISS MMFSA_F_MISS /* mmu miss */
77 #define FT_NEW_INVRA MMFSA_F_INVRA /* invalid RA */
78 #define FT_NEW_PROT MMFSA_F_PROT /* protection violation */
79 #define FT_NEW_PRVACT MMFSA_F_PRVACT /* privileged action */
80 #define FT_NEW_WPT MMFSA_F_WPT /* watchpoint hit */
81 #define FT_NEW_UNALIGN MMFSA_F_UNALIGN /* unaligned access */
82 #define FT_NEW_INVPGSZ MMFSA_F_INVPGSZ /* invalid page size */
84 #define SFSR_FT_SHIFT 0 /* amt. to shift right to get flt type */
85 #define SFSR_CTX_SHIFT 16 /* to shift right to get context */
86 #define X_FAULT_TYPE(x) (((x) & SFSR_FT) >> SFSR_FT_SHIFT)
87 #define X_FAULT_CTX(x) (((x) & SFSR_CTX) >> SFSR_CTX_SHIFT)
90 * MMU TAG TARGET register Layout
92 * +-----+---------+------+-------------------------+
93 * | 000 | context | -- | virtual address [63:22] |
94 * +-----+---------+------+-------------------------+
95 * 63 61 60 48 47 42 41 0
97 #define TTARGET_CTX_SHIFT 48
98 #define TTARGET_VA_SHIFT 22
101 #define TTARGET_VA_BITS 42
102 #define TTARGET_VA_MASK ((1UL << TTARGET_VA_BITS) - 1)
106 * MMU PRIMARY/SECONDARY CONTEXT register
108 #define CTXREG_CTX_MASK 0x1FFF
111 * The kernel always runs in KCONTEXT, and no user mappings
112 * are ever valid in it (so any user access pagefaults).
115 #define CTX_OTHER_SHIFT 16
118 * FLUSH_ADDR is used in the flush instruction to guarantee stores to mmu
119 * registers complete. It is selected so it won't miss in the tlb.
121 #define FLUSH_ADDR (KERNBASE + 2 * PAGE_SIZE_4M)
123 #endif /* _MACHINE_MMU_H_ */