2 * Copyright (c) 2002 Jake Burkholder.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <machine/asm.h>
28 __FBSDID("$FreeBSD$");
30 #include <machine/asi.h>
31 #include <machine/ktr.h>
32 #include <machine/asmacros.h>
33 #include <machine/pstate.h>
37 .register %g2, #ignore
38 .register %g3, #ignore
40 #define IPI_DONE(r1, r2, r3, r4) \
41 lduw [PCPU(CPUMASK)], r4 ; \
42 ATOMIC_CLEAR_INT(r1, r2, r3, r4)
45 * Invalidate a physical page in the data cache. For UltraSPARC I and II.
48 ENTRY(tl_ipi_spitfire_dcache_page_inval)
49 #if KTR_COMPILE & KTR_SMP
50 CATR(KTR_SMP, "ipi_dcache_page_inval: pa=%#lx"
51 , %g1, %g2, %g3, 7, 8, 9)
52 ldx [%g5 + ICA_PA], %g2
53 stx %g2, [%g1 + KTR_PARM1]
57 ldx [%g5 + ICA_PA], %g6
58 srlx %g6, PAGE_SHIFT - DC_TAG_SHIFT, %g6
61 lduw [%g2 + DC_SIZE], %g3
62 lduw [%g2 + DC_LINESIZE], %g4
65 1: ldxa [%g2] ASI_DCACHE_TAG, %g1
66 srlx %g1, DC_VALID_SHIFT, %g3
67 andcc %g3, DC_VALID_MASK, %g0
70 sllx %g3, DC_TAG_SHIFT, %g3
75 stxa %g1, [%g2] ASI_DCACHE_TAG
81 IPI_DONE(%g5, %g1, %g2, %g3)
83 END(tl_ipi_spitfire_dcache_page_inval)
86 * Invalidate a physical page in the instruction cache. For UltraSPARC I and
89 ENTRY(tl_ipi_spitfire_icache_page_inval)
90 #if KTR_COMPILE & KTR_SMP
91 CATR(KTR_SMP, "ipi_icache_page_inval: pa=%#lx"
92 , %g1, %g2, %g3, 7, 8, 9)
93 ldx [%g5 + ICA_PA], %g2
94 stx %g2, [%g1 + KTR_PARM1]
98 ldx [%g5 + ICA_PA], %g6
99 srlx %g6, PAGE_SHIFT - IC_TAG_SHIFT, %g6
102 lduw [%g2 + IC_SIZE], %g3
103 lduw [%g2 + IC_LINESIZE], %g4
106 1: ldda [%g2] ASI_ICACHE_TAG, %g0 /*, %g1 */
107 srlx %g1, IC_VALID_SHIFT, %g3
108 andcc %g3, IC_VALID_MASK, %g0
111 sllx %g3, IC_TAG_SHIFT, %g3
116 stxa %g1, [%g2] ASI_ICACHE_TAG
122 IPI_DONE(%g5, %g1, %g2, %g3)
124 END(tl_ipi_spitfire_icache_page_inval)
127 * Invalidate a physical page in the data cache. For UltraSPARC III.
129 ENTRY(tl_ipi_cheetah_dcache_page_inval)
130 #if KTR_COMPILE & KTR_SMP
131 CATR(KTR_SMP, "ipi_dcache_page_inval: pa=%#lx"
132 , %g1, %g2, %g3, 7, 8, 9)
133 ldx [%g5 + ICA_PA], %g2
134 stx %g2, [%g1 + KTR_PARM1]
138 ldx [%g5 + ICA_PA], %g1
144 lduw [%g2 + DC_LINESIZE], %g2
146 1: stxa %g0, [%g1] ASI_DCACHE_INVALIDATE
154 IPI_DONE(%g5, %g1, %g2, %g3)
156 END(tl_ipi_cheetah_dcache_page_inval)
160 * Trigger a softint at the desired level.
163 #if KTR_COMPILE & KTR_SMP
164 CATR(KTR_SMP, "tl_ipi_level: cpuid=%d mid=%d d1=%#lx d2=%#lx"
165 , %g1, %g2, %g3, 7, 8, 9)
166 lduw [PCPU(CPUID)], %g2
167 stx %g2, [%g1 + KTR_PARM1]
168 lduw [PCPU(MID)], %g2
169 stx %g2, [%g1 + KTR_PARM2]
170 stx %g4, [%g1 + KTR_PARM3]
171 stx %g5, [%g1 + KTR_PARM4]
177 wr %g2, 0, %set_softint
182 * Demap a page from the dtlb and/or itlb.
185 ENTRY(tl_ipi_tlb_page_demap)
186 #if KTR_COMPILE & KTR_SMP
187 CATR(KTR_SMP, "ipi_tlb_page_demap: pm=%p va=%#lx"
188 , %g1, %g2, %g3, 7, 8, 9)
189 ldx [%g5 + ITA_PMAP], %g2
190 stx %g2, [%g1 + KTR_PARM1]
191 ldx [%g5 + ITA_VA], %g2
192 stx %g2, [%g1 + KTR_PARM2]
196 ldx [%g5 + ITA_PMAP], %g1
198 SET(kernel_pmap_store, %g3, %g2)
199 mov TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE, %g3
202 movne %xcc, TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE, %g3
204 ldx [%g5 + ITA_VA], %g2
207 stxa %g0, [%g2] ASI_DMMU_DEMAP
208 stxa %g0, [%g2] ASI_IMMU_DEMAP
211 IPI_DONE(%g5, %g1, %g2, %g3)
213 END(tl_ipi_tlb_page_demap)
216 * Demap a range of pages from the dtlb and itlb.
218 ENTRY(tl_ipi_tlb_range_demap)
219 #if KTR_COMPILE & KTR_SMP
220 CATR(KTR_SMP, "ipi_tlb_range_demap: pm=%p start=%#lx end=%#lx"
221 , %g1, %g2, %g3, 7, 8, 9)
222 ldx [%g5 + ITA_PMAP], %g2
223 stx %g2, [%g1 + KTR_PARM1]
224 ldx [%g5 + ITA_START], %g2
225 stx %g2, [%g1 + KTR_PARM2]
226 ldx [%g5 + ITA_END], %g2
227 stx %g2, [%g1 + KTR_PARM3]
231 ldx [%g5 + ITA_PMAP], %g1
233 SET(kernel_pmap_store, %g3, %g2)
234 mov TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE, %g3
237 movne %xcc, TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE, %g3
239 ldx [%g5 + ITA_START], %g1
240 ldx [%g5 + ITA_END], %g2
245 stxa %g0, [%g4] ASI_DMMU_DEMAP
246 stxa %g0, [%g4] ASI_IMMU_DEMAP
254 IPI_DONE(%g5, %g1, %g2, %g3)
256 END(tl_ipi_tlb_range_demap)
259 * Demap the primary context from the dtlb and itlb.
261 ENTRY(tl_ipi_tlb_context_demap)
262 #if KTR_COMPILE & KTR_SMP
263 CATR(KTR_SMP, "ipi_tlb_page_demap: pm=%p va=%#lx"
264 , %g1, %g2, %g3, 7, 8, 9)
265 ldx [%g5 + ITA_PMAP], %g2
266 stx %g2, [%g1 + KTR_PARM1]
267 ldx [%g5 + ITA_VA], %g2
268 stx %g2, [%g1 + KTR_PARM2]
272 mov TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, %g1
273 stxa %g0, [%g1] ASI_DMMU_DEMAP
274 stxa %g0, [%g1] ASI_IMMU_DEMAP
277 IPI_DONE(%g5, %g1, %g2, %g3)
279 END(tl_ipi_tlb_context_demap)