2 * Copyright (c) 2000 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include <sys/ioccom.h>
34 /* ATA/ATAPI device parameters */
36 /*000*/ u_int16_t config; /* configuration info */
37 #define ATA_PROTO_MASK 0x8003
38 #define ATA_PROTO_ATAPI 0x8000
39 #define ATA_PROTO_ATAPI_12 0x8000
40 #define ATA_PROTO_ATAPI_16 0x8001
41 #define ATA_PROTO_CFA 0x848a
42 #define ATA_ATAPI_TYPE_MASK 0x1f00
43 #define ATA_ATAPI_TYPE_DIRECT 0x0000 /* disk/floppy */
44 #define ATA_ATAPI_TYPE_TAPE 0x0100 /* streaming tape */
45 #define ATA_ATAPI_TYPE_CDROM 0x0500 /* CD-ROM device */
46 #define ATA_ATAPI_TYPE_OPTICAL 0x0700 /* optical disk */
47 #define ATA_DRQ_MASK 0x0060
48 #define ATA_DRQ_SLOW 0x0000 /* cpu 3 ms delay */
49 #define ATA_DRQ_INTR 0x0020 /* interrupt 10 ms delay */
50 #define ATA_DRQ_FAST 0x0040 /* accel 50 us delay */
51 #define ATA_RESP_INCOMPLETE 0x0004
53 /*001*/ u_int16_t cylinders; /* # of cylinders */
54 /*002*/ u_int16_t specconf; /* specific configuration */
55 /*003*/ u_int16_t heads; /* # heads */
58 /*006*/ u_int16_t sectors; /* # sectors/track */
59 /*007*/ u_int16_t vendor7[3];
60 /*010*/ u_int8_t serial[20]; /* serial number */
61 /*020*/ u_int16_t retired20;
64 /*023*/ u_int8_t revision[8]; /* firmware revision */
65 /*027*/ u_int8_t model[40]; /* model name */
66 /*047*/ u_int16_t sectors_intr; /* sectors per interrupt */
67 /*048*/ u_int16_t usedmovsd; /* double word read/write? */
68 /*049*/ u_int16_t capabilities1;
69 #define ATA_SUPPORT_DMA 0x0100
70 #define ATA_SUPPORT_LBA 0x0200
71 #define ATA_SUPPORT_IORDYDIS 0x0400
72 #define ATA_SUPPORT_IORDY 0x0800
73 #define ATA_SUPPORT_OVERLAP 0x4000
75 /*050*/ u_int16_t capabilities2;
76 /*051*/ u_int16_t retired_piomode; /* PIO modes 0-2 */
77 #define ATA_RETIRED_PIO_MASK 0x0300
79 /*052*/ u_int16_t retired_dmamode; /* DMA modes */
80 #define ATA_RETIRED_DMA_MASK 0x0003
82 /*053*/ u_int16_t atavalid; /* fields valid */
83 #define ATA_FLAG_54_58 0x0001 /* words 54-58 valid */
84 #define ATA_FLAG_64_70 0x0002 /* words 64-70 valid */
85 #define ATA_FLAG_88 0x0004 /* word 88 valid */
87 /*054*/ u_int16_t current_cylinders;
88 /*055*/ u_int16_t current_heads;
89 /*056*/ u_int16_t current_sectors;
90 /*057*/ u_int16_t current_size_1;
91 /*058*/ u_int16_t current_size_2;
92 /*059*/ u_int16_t multi;
93 #define ATA_MULTI_VALID 0x0100
95 /*060*/ u_int16_t lba_size_1;
98 /*063*/ u_int16_t mwdmamodes; /* multiword DMA modes */
99 /*064*/ u_int16_t apiomodes; /* advanced PIO modes */
101 /*065*/ u_int16_t mwdmamin; /* min. M/W DMA time/word ns */
102 /*066*/ u_int16_t mwdmarec; /* rec. M/W DMA time ns */
103 /*067*/ u_int16_t pioblind; /* min. PIO cycle w/o flow */
104 /*068*/ u_int16_t pioiordy; /* min. PIO cycle IORDY flow */
105 /*069*/ u_int16_t support3;
106 #define ATA_SUPPORT_RZAT 0x0020
107 #define ATA_SUPPORT_DRAT 0x4000
108 #define ATA_SUPPORT_ZONE_MASK 0x0003
109 #define ATA_SUPPORT_ZONE_NR 0x0000
110 #define ATA_SUPPORT_ZONE_HOST_AWARE 0x0001
111 #define ATA_SUPPORT_ZONE_DEV_MANAGED 0x0002
112 u_int16_t reserved70;
113 /*071*/ u_int16_t rlsovlap; /* rel time (us) for overlap */
114 /*072*/ u_int16_t rlsservice; /* rel time (us) for service */
115 u_int16_t reserved73;
116 u_int16_t reserved74;
117 /*075*/ u_int16_t queue;
118 #define ATA_QUEUE_LEN(x) ((x) & 0x001f)
120 /*76*/ u_int16_t satacapabilities;
121 #define ATA_SATA_GEN1 0x0002
122 #define ATA_SATA_GEN2 0x0004
123 #define ATA_SATA_GEN3 0x0008
124 #define ATA_SUPPORT_NCQ 0x0100
125 #define ATA_SUPPORT_IFPWRMNGTRCV 0x0200
126 #define ATA_SUPPORT_PHYEVENTCNT 0x0400
127 #define ATA_SUPPORT_NCQ_UNLOAD 0x0800
128 #define ATA_SUPPORT_NCQ_PRIO 0x1000
129 #define ATA_SUPPORT_HAPST 0x2000
130 #define ATA_SUPPORT_DAPST 0x4000
131 #define ATA_SUPPORT_READLOGDMAEXT 0x8000
133 /*77*/ u_int16_t satacapabilities2;
134 #define ATA_SATA_CURR_GEN_MASK 0x0006
135 #define ATA_SUPPORT_NCQ_STREAM 0x0010
136 #define ATA_SUPPORT_NCQ_QMANAGEMENT 0x0020
137 #define ATA_SUPPORT_RCVSND_FPDMA_QUEUED 0x0040
138 /*78*/ u_int16_t satasupport;
139 #define ATA_SUPPORT_NONZERO 0x0002
140 #define ATA_SUPPORT_AUTOACTIVATE 0x0004
141 #define ATA_SUPPORT_IFPWRMNGT 0x0008
142 #define ATA_SUPPORT_INORDERDATA 0x0010
143 #define ATA_SUPPORT_ASYNCNOTIF 0x0020
144 #define ATA_SUPPORT_SOFTSETPRESERVE 0x0040
145 /*79*/ u_int16_t sataenabled;
146 #define ATA_ENABLED_DAPST 0x0080
148 /*080*/ u_int16_t version_major;
149 /*081*/ u_int16_t version_minor;
152 /*082/085*/ u_int16_t command1;
153 #define ATA_SUPPORT_SMART 0x0001
154 #define ATA_SUPPORT_SECURITY 0x0002
155 #define ATA_SUPPORT_REMOVABLE 0x0004
156 #define ATA_SUPPORT_POWERMGT 0x0008
157 #define ATA_SUPPORT_PACKET 0x0010
158 #define ATA_SUPPORT_WRITECACHE 0x0020
159 #define ATA_SUPPORT_LOOKAHEAD 0x0040
160 #define ATA_SUPPORT_RELEASEIRQ 0x0080
161 #define ATA_SUPPORT_SERVICEIRQ 0x0100
162 #define ATA_SUPPORT_RESET 0x0200
163 #define ATA_SUPPORT_PROTECTED 0x0400
164 #define ATA_SUPPORT_WRITEBUFFER 0x1000
165 #define ATA_SUPPORT_READBUFFER 0x2000
166 #define ATA_SUPPORT_NOP 0x4000
168 /*083/086*/ u_int16_t command2;
169 #define ATA_SUPPORT_MICROCODE 0x0001
170 #define ATA_SUPPORT_QUEUED 0x0002
171 #define ATA_SUPPORT_CFA 0x0004
172 #define ATA_SUPPORT_APM 0x0008
173 #define ATA_SUPPORT_NOTIFY 0x0010
174 #define ATA_SUPPORT_STANDBY 0x0020
175 #define ATA_SUPPORT_SPINUP 0x0040
176 #define ATA_SUPPORT_MAXSECURITY 0x0100
177 #define ATA_SUPPORT_AUTOACOUSTIC 0x0200
178 #define ATA_SUPPORT_ADDRESS48 0x0400
179 #define ATA_SUPPORT_OVERLAY 0x0800
180 #define ATA_SUPPORT_FLUSHCACHE 0x1000
181 #define ATA_SUPPORT_FLUSHCACHE48 0x2000
183 /*084/087*/ u_int16_t extension;
184 #define ATA_SUPPORT_SMARTLOG 0x0001
185 #define ATA_SUPPORT_SMARTTEST 0x0002
186 #define ATA_SUPPORT_MEDIASN 0x0004
187 #define ATA_SUPPORT_MEDIAPASS 0x0008
188 #define ATA_SUPPORT_STREAMING 0x0010
189 #define ATA_SUPPORT_GENLOG 0x0020
190 #define ATA_SUPPORT_WRITEDMAFUAEXT 0x0040
191 #define ATA_SUPPORT_WRITEDMAQFUAEXT 0x0080
192 #define ATA_SUPPORT_64BITWWN 0x0100
193 #define ATA_SUPPORT_UNLOAD 0x2000
194 } __packed support, enabled;
196 /*088*/ u_int16_t udmamodes; /* UltraDMA modes */
197 /*089*/ u_int16_t erase_time; /* time req'd in 2min units */
198 /*090*/ u_int16_t enhanced_erase_time; /* time req'd in 2min units */
199 /*091*/ u_int16_t apm_value;
200 /*092*/ u_int16_t master_passwd_revision; /* password revision code */
201 /*093*/ u_int16_t hwres;
202 #define ATA_CABLE_ID 0x2000
204 /*094*/ u_int16_t acoustic;
205 #define ATA_ACOUSTIC_CURRENT(x) ((x) & 0x00ff)
206 #define ATA_ACOUSTIC_VENDOR(x) (((x) & 0xff00) >> 8)
208 /*095*/ u_int16_t stream_min_req_size;
209 /*096*/ u_int16_t stream_transfer_time;
210 /*097*/ u_int16_t stream_access_latency;
211 /*098*/ u_int32_t stream_granularity;
212 /*100*/ u_int16_t lba_size48_1;
213 u_int16_t lba_size48_2;
214 u_int16_t lba_size48_3;
215 u_int16_t lba_size48_4;
216 u_int16_t reserved104;
217 /*105*/ u_int16_t max_dsm_blocks;
218 /*106*/ u_int16_t pss;
219 #define ATA_PSS_LSPPS 0x000F
220 #define ATA_PSS_LSSABOVE512 0x1000
221 #define ATA_PSS_MULTLS 0x2000
222 #define ATA_PSS_VALID_MASK 0xC000
223 #define ATA_PSS_VALID_VALUE 0x4000
224 /*107*/ u_int16_t isd;
225 /*108*/ u_int16_t wwn[4];
226 u_int16_t reserved112[5];
227 /*117*/ u_int16_t lss_1;
228 /*118*/ u_int16_t lss_2;
229 /*119*/ u_int16_t support2;
230 #define ATA_SUPPORT_WRITEREADVERIFY 0x0002
231 #define ATA_SUPPORT_WRITEUNCORREXT 0x0004
232 #define ATA_SUPPORT_RWLOGDMAEXT 0x0008
233 #define ATA_SUPPORT_MICROCODE3 0x0010
234 #define ATA_SUPPORT_FREEFALL 0x0020
235 #define ATA_SUPPORT_SENSE_REPORT 0x0040
236 #define ATA_SUPPORT_EPC 0x0080
237 /*120*/ u_int16_t enabled2;
238 #define ATA_ENABLED_WRITEREADVERIFY 0x0002
239 #define ATA_ENABLED_WRITEUNCORREXT 0x0004
240 #define ATA_ENABLED_FREEFALL 0x0020
241 #define ATA_ENABLED_SENSE_REPORT 0x0040
242 #define ATA_ENABLED_EPC 0x0080
243 u_int16_t reserved121[6];
244 /*127*/ u_int16_t removable_status;
245 /*128*/ u_int16_t security_status;
246 #define ATA_SECURITY_LEVEL 0x0100 /* 0: high, 1: maximum */
247 #define ATA_SECURITY_ENH_SUPP 0x0020 /* enhanced erase supported */
248 #define ATA_SECURITY_COUNT_EXP 0x0010 /* count expired */
249 #define ATA_SECURITY_FROZEN 0x0008 /* security config is frozen */
250 #define ATA_SECURITY_LOCKED 0x0004 /* drive is locked */
251 #define ATA_SECURITY_ENABLED 0x0002 /* ATA Security is enabled */
252 #define ATA_SECURITY_SUPPORTED 0x0001 /* ATA Security is supported */
254 u_int16_t reserved129[31];
255 /*160*/ u_int16_t cfa_powermode1;
256 u_int16_t reserved161;
257 /*162*/ u_int16_t cfa_kms_support;
258 /*163*/ u_int16_t cfa_trueide_modes;
259 /*164*/ u_int16_t cfa_memory_modes;
260 u_int16_t reserved165[4];
261 /*169*/ u_int16_t support_dsm;
262 #define ATA_SUPPORT_DSM_TRIM 0x0001
263 u_int16_t reserved170[6];
264 /*176*/ u_int8_t media_serial[60];
265 /*206*/ u_int16_t sct;
266 u_int16_t reserved207[2];
267 /*209*/ u_int16_t lsalign;
268 /*210*/ u_int16_t wrv_sectors_m3_1;
269 u_int16_t wrv_sectors_m3_2;
270 /*212*/ u_int16_t wrv_sectors_m2_1;
271 u_int16_t wrv_sectors_m2_2;
272 /*214*/ u_int16_t nv_cache_caps;
273 /*215*/ u_int16_t nv_cache_size_1;
274 u_int16_t nv_cache_size_2;
275 /*217*/ u_int16_t media_rotation_rate;
276 #define ATA_RATE_NOT_REPORTED 0x0000
277 #define ATA_RATE_NON_ROTATING 0x0001
278 u_int16_t reserved218;
279 /*219*/ u_int16_t nv_cache_opt;
280 /*220*/ u_int16_t wrv_mode;
281 u_int16_t reserved221;
282 /*222*/ u_int16_t transport_major;
283 /*223*/ u_int16_t transport_minor;
284 u_int16_t reserved224[31];
285 /*255*/ u_int16_t integrity;
288 /* ATA Dataset Management */
289 #define ATA_DSM_BLK_SIZE 512
290 #define ATA_DSM_BLK_RANGES 64
291 #define ATA_DSM_RANGE_SIZE 8
292 #define ATA_DSM_RANGE_MAX 65535
295 * ATA Device Register
297 * bit 7 Obsolete (was 1 in early ATA specs)
298 * bit 6 Sets LBA/CHS mode. 1=LBA, 0=CHS
299 * bit 5 Obsolete (was 1 in early ATA specs)
300 * bit 4 1 = Slave Drive, 0 = Master Drive
301 * bit 3-0 In LBA mode, 27-24 of address. In CHS mode, head number
304 #define ATA_DEV_MASTER 0x00
305 #define ATA_DEV_SLAVE 0x10
306 #define ATA_DEV_LBA 0x40
309 #define ATA_MAX_28BIT_LBA 268435455UL
311 /* ATA Status Register */
312 #define ATA_STATUS_ERROR 0x01
313 #define ATA_STATUS_SENSE_AVAIL 0x02
314 #define ATA_STATUS_ALIGN_ERR 0x04
315 #define ATA_STATUS_DATA_REQ 0x08
316 #define ATA_STATUS_DEF_WRITE_ERR 0x10
317 #define ATA_STATUS_DEVICE_FAULT 0x20
318 #define ATA_STATUS_DEVICE_READY 0x40
319 #define ATA_STATUS_BUSY 0x80
321 /* ATA Error Register */
322 #define ATA_ERROR_ABORT 0x04
323 #define ATA_ERROR_ID_NOT_FOUND 0x10
325 /* ATA HPA Features */
326 #define ATA_HPA_FEAT_MAX_ADDR 0x00
327 #define ATA_HPA_FEAT_SET_PWD 0x01
328 #define ATA_HPA_FEAT_LOCK 0x02
329 #define ATA_HPA_FEAT_UNLOCK 0x03
330 #define ATA_HPA_FEAT_FREEZE 0x04
332 /* ATA transfer modes */
333 #define ATA_MODE_MASK 0x0f
334 #define ATA_DMA_MASK 0xf0
336 #define ATA_PIO0 0x08
337 #define ATA_PIO1 0x09
338 #define ATA_PIO2 0x0a
339 #define ATA_PIO3 0x0b
340 #define ATA_PIO4 0x0c
341 #define ATA_PIO_MAX 0x0f
343 #define ATA_WDMA0 0x20
344 #define ATA_WDMA1 0x21
345 #define ATA_WDMA2 0x22
346 #define ATA_UDMA0 0x40
347 #define ATA_UDMA1 0x41
348 #define ATA_UDMA2 0x42
349 #define ATA_UDMA3 0x43
350 #define ATA_UDMA4 0x44
351 #define ATA_UDMA5 0x45
352 #define ATA_UDMA6 0x46
353 #define ATA_SA150 0x47
354 #define ATA_SA300 0x48
355 #define ATA_SA600 0x49
356 #define ATA_DMA_MAX 0x4f
360 #define ATA_NOP 0x00 /* NOP */
361 #define ATA_NF_FLUSHQUEUE 0x00 /* flush queued cmd's */
362 #define ATA_NF_AUTOPOLL 0x01 /* start autopoll function */
363 #define ATA_DATA_SET_MANAGEMENT 0x06
364 #define ATA_DSM_TRIM 0x01
365 #define ATA_DEVICE_RESET 0x08 /* reset device */
366 #define ATA_READ 0x20 /* read */
367 #define ATA_READ48 0x24 /* read 48bit LBA */
368 #define ATA_READ_DMA48 0x25 /* read DMA 48bit LBA */
369 #define ATA_READ_DMA_QUEUED48 0x26 /* read DMA QUEUED 48bit LBA */
370 #define ATA_READ_NATIVE_MAX_ADDRESS48 0x27 /* read native max addr 48bit */
371 #define ATA_READ_MUL48 0x29 /* read multi 48bit LBA */
372 #define ATA_READ_STREAM_DMA48 0x2a /* read DMA stream 48bit LBA */
373 #define ATA_READ_LOG_EXT 0x2f /* read log ext - PIO Data-In */
374 #define ATA_READ_STREAM48 0x2b /* read stream 48bit LBA */
375 #define ATA_WRITE 0x30 /* write */
376 #define ATA_WRITE48 0x34 /* write 48bit LBA */
377 #define ATA_WRITE_DMA48 0x35 /* write DMA 48bit LBA */
378 #define ATA_WRITE_DMA_QUEUED48 0x36 /* write DMA QUEUED 48bit LBA*/
379 #define ATA_SET_MAX_ADDRESS48 0x37 /* set max address 48bit */
380 #define ATA_WRITE_MUL48 0x39 /* write multi 48bit LBA */
381 #define ATA_WRITE_STREAM_DMA48 0x3a
382 #define ATA_WRITE_STREAM48 0x3b
383 #define ATA_WRITE_DMA_FUA48 0x3d
384 #define ATA_WRITE_DMA_QUEUED_FUA48 0x3e
385 #define ATA_WRITE_LOG_EXT 0x3f
386 #define ATA_READ_VERIFY 0x40
387 #define ATA_READ_VERIFY48 0x42
388 #define ATA_WRITE_UNCORRECTABLE48 0x45 /* write uncorrectable 48bit LBA */
389 #define ATA_WU_PSEUDO 0x55 /* pseudo-uncorrectable error */
390 #define ATA_WU_FLAGGED 0xaa /* flagged-uncorrectable error */
391 #define ATA_READ_LOG_DMA_EXT 0x47 /* read log DMA ext - PIO Data-In */
392 #define ATA_ZAC_MANAGEMENT_IN 0x4a /* ZAC management in */
393 #define ATA_ZM_REPORT_ZONES 0x00 /* report zones */
394 #define ATA_WRITE_LOG_DMA_EXT 0x57 /* WRITE LOG DMA EXT */
395 #define ATA_TRUSTED_NON_DATA 0x5b /* TRUSTED NON-DATA */
396 #define ATA_TRUSTED_RECEIVE 0x5c /* TRUSTED RECEIVE */
397 #define ATA_TRUSTED_RECEIVE_DMA 0x5d /* TRUSTED RECEIVE DMA */
398 #define ATA_TRUSTED_SEND 0x5e /* TRUSTED SEND */
399 #define ATA_TRUSTED_SEND_DMA 0x5f /* TRUSTED SEND DMA */
400 #define ATA_READ_FPDMA_QUEUED 0x60 /* read DMA NCQ */
401 #define ATA_WRITE_FPDMA_QUEUED 0x61 /* write DMA NCQ */
402 #define ATA_NCQ_NON_DATA 0x63 /* NCQ non-data command */
403 #define ATA_ABORT_NCQ_QUEUE 0x00 /* abort NCQ queue */
404 #define ATA_DEADLINE_HANDLING 0x01 /* deadline handling */
405 #define ATA_SET_FEATURES 0x05 /* set features */
406 #define ATA_ZERO_EXT 0x06 /* zero ext */
407 #define ATA_NCQ_ZAC_MGMT_OUT 0x07 /* NCQ ZAC mgmt out no data */
408 #define ATA_SEND_FPDMA_QUEUED 0x64 /* send DMA NCQ */
409 #define ATA_SFPDMA_DSM 0x00 /* Data set management */
410 #define ATA_SFPDMA_DSM_TRIM 0x01 /* Set trim bit in auxiliary */
411 #define ATA_SFPDMA_HYBRID_EVICT 0x01 /* Hybrid Evict */
412 #define ATA_SFPDMA_WLDMA 0x02 /* Write Log DMA EXT */
413 #define ATA_SFPDMA_ZAC_MGMT_OUT 0x03 /* NCQ ZAC mgmt out w/data */
414 #define ATA_RECV_FPDMA_QUEUED 0x65 /* receive DMA NCQ */
415 #define ATA_RFPDMA_RL_DMA_EXT 0x00 /* Read Log DMA EXT */
416 #define ATA_RFPDMA_ZAC_MGMT_IN 0x02 /* NCQ ZAC mgmt in w/data */
417 #define ATA_SEP_ATTN 0x67 /* SEP request */
418 #define ATA_SEEK 0x70 /* seek */
419 #define ATA_ZAC_MANAGEMENT_OUT 0x9f /* ZAC management out */
420 #define ATA_ZM_CLOSE_ZONE 0x01 /* close zone */
421 #define ATA_ZM_FINISH_ZONE 0x02 /* finish zone */
422 #define ATA_ZM_OPEN_ZONE 0x03 /* open zone */
423 #define ATA_ZM_RWP 0x04 /* reset write pointer */
424 #define ATA_DOWNLOAD_MICROCODE 0x92 /* DOWNLOAD MICROCODE */
425 #define ATA_DOWNLOAD_MICROCODE_DMA 0x93 /* DOWNLOAD MICROCODE DMA */
426 #define ATA_PACKET_CMD 0xa0 /* packet command */
427 #define ATA_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/
428 #define ATA_SERVICE 0xa2 /* service command */
429 #define ATA_SMART_CMD 0xb0 /* SMART command */
430 #define ATA_CFA_ERASE 0xc0 /* CFA erase */
431 #define ATA_READ_MUL 0xc4 /* read multi */
432 #define ATA_WRITE_MUL 0xc5 /* write multi */
433 #define ATA_SET_MULTI 0xc6 /* set multi size */
434 #define ATA_READ_DMA_QUEUED 0xc7 /* read DMA QUEUED */
435 #define ATA_READ_DMA 0xc8 /* read DMA */
436 #define ATA_WRITE_DMA 0xca /* write DMA */
437 #define ATA_WRITE_DMA_QUEUED 0xcc /* write DMA QUEUED */
438 #define ATA_WRITE_MUL_FUA48 0xce
439 #define ATA_STANDBY_IMMEDIATE 0xe0 /* standby immediate */
440 #define ATA_IDLE_IMMEDIATE 0xe1 /* idle immediate */
441 #define ATA_STANDBY_CMD 0xe2 /* standby */
442 #define ATA_IDLE_CMD 0xe3 /* idle */
443 #define ATA_READ_BUFFER 0xe4 /* read buffer */
444 #define ATA_READ_PM 0xe4 /* read portmultiplier */
445 #define ATA_CHECK_POWER_MODE 0xe5 /* device power mode */
446 #define ATA_SLEEP 0xe6 /* sleep */
447 #define ATA_FLUSHCACHE 0xe7 /* flush cache to disk */
448 #define ATA_WRITE_BUFFER 0xe8 /* write buffer */
449 #define ATA_WRITE_PM 0xe8 /* write portmultiplier */
450 #define ATA_READ_BUFFER_DMA 0xe9 /* read buffer DMA */
451 #define ATA_FLUSHCACHE48 0xea /* flush cache to disk */
452 #define ATA_WRITE_BUFFER_DMA 0xeb /* write buffer DMA */
453 #define ATA_ATA_IDENTIFY 0xec /* get ATA params */
454 #define ATA_SETFEATURES 0xef /* features command */
455 #define ATA_SF_ENAB_WCACHE 0x02 /* enable write cache */
456 #define ATA_SF_DIS_WCACHE 0x82 /* disable write cache */
457 #define ATA_SF_SETXFER 0x03 /* set transfer mode */
458 #define ATA_SF_APM 0x05 /* Enable APM feature set */
459 #define ATA_SF_ENAB_PUIS 0x06 /* enable PUIS */
460 #define ATA_SF_DIS_PUIS 0x86 /* disable PUIS */
461 #define ATA_SF_PUIS_SPINUP 0x07 /* PUIS spin-up */
462 #define ATA_SF_WRV 0x0b /* Enable Write-Read-Verify */
463 #define ATA_SF_DLC 0x0c /* Enable device life control */
464 #define ATA_SF_SATA 0x10 /* Enable use of SATA feature */
465 #define ATA_SF_FFC 0x41 /* Free-fall Control */
466 #define ATA_SF_MHIST 0x43 /* Set Max Host Sect. Times */
467 #define ATA_SF_RATE 0x45 /* Set Rate Basis */
468 #define ATA_SF_EPC 0x4A /* Extended Power Conditions */
469 #define ATA_SF_ENAB_RCACHE 0xaa /* enable readahead cache */
470 #define ATA_SF_DIS_RCACHE 0x55 /* disable readahead cache */
471 #define ATA_SF_ENAB_RELIRQ 0x5d /* enable release interrupt */
472 #define ATA_SF_DIS_RELIRQ 0xdd /* disable release interrupt */
473 #define ATA_SF_ENAB_SRVIRQ 0x5e /* enable service interrupt */
474 #define ATA_SF_DIS_SRVIRQ 0xde /* disable service interrupt */
475 #define ATA_SF_LPSAERC 0x62 /* Long Phys Sect Align ErrRep*/
476 #define ATA_SF_DSN 0x63 /* Device Stats Notification */
477 #define ATA_CHECK_POWER_MODE 0xe5 /* Check Power Mode */
478 #define ATA_SECURITY_SET_PASSWORD 0xf1 /* set drive password */
479 #define ATA_SECURITY_UNLOCK 0xf2 /* unlock drive using passwd */
480 #define ATA_SECURITY_ERASE_PREPARE 0xf3 /* prepare to erase drive */
481 #define ATA_SECURITY_ERASE_UNIT 0xf4 /* erase all blocks on drive */
482 #define ATA_SECURITY_FREEZE_LOCK 0xf5 /* freeze security config */
483 #define ATA_SECURITY_DISABLE_PASSWORD 0xf6 /* disable drive password */
484 #define ATA_READ_NATIVE_MAX_ADDRESS 0xf8 /* read native max address */
485 #define ATA_SET_MAX_ADDRESS 0xf9 /* set max address */
489 #define ATAPI_TEST_UNIT_READY 0x00 /* check if device is ready */
490 #define ATAPI_REZERO 0x01 /* rewind */
491 #define ATAPI_REQUEST_SENSE 0x03 /* get sense data */
492 #define ATAPI_FORMAT 0x04 /* format unit */
493 #define ATAPI_READ 0x08 /* read data */
494 #define ATAPI_WRITE 0x0a /* write data */
495 #define ATAPI_WEOF 0x10 /* write filemark */
496 #define ATAPI_WF_WRITE 0x01
497 #define ATAPI_SPACE 0x11 /* space command */
498 #define ATAPI_SP_FM 0x01
499 #define ATAPI_SP_EOD 0x03
500 #define ATAPI_INQUIRY 0x12 /* get inquiry data */
501 #define ATAPI_MODE_SELECT 0x15 /* mode select */
502 #define ATAPI_ERASE 0x19 /* erase */
503 #define ATAPI_MODE_SENSE 0x1a /* mode sense */
504 #define ATAPI_START_STOP 0x1b /* start/stop unit */
505 #define ATAPI_SS_LOAD 0x01
506 #define ATAPI_SS_RETENSION 0x02
507 #define ATAPI_SS_EJECT 0x04
508 #define ATAPI_PREVENT_ALLOW 0x1e /* media removal */
509 #define ATAPI_READ_FORMAT_CAPACITIES 0x23 /* get format capacities */
510 #define ATAPI_READ_CAPACITY 0x25 /* get volume capacity */
511 #define ATAPI_READ_BIG 0x28 /* read data */
512 #define ATAPI_WRITE_BIG 0x2a /* write data */
513 #define ATAPI_LOCATE 0x2b /* locate to position */
514 #define ATAPI_READ_POSITION 0x34 /* read position */
515 #define ATAPI_SYNCHRONIZE_CACHE 0x35 /* flush buf, close channel */
516 #define ATAPI_WRITE_BUFFER 0x3b /* write device buffer */
517 #define ATAPI_READ_BUFFER 0x3c /* read device buffer */
518 #define ATAPI_READ_SUBCHANNEL 0x42 /* get subchannel info */
519 #define ATAPI_READ_TOC 0x43 /* get table of contents */
520 #define ATAPI_PLAY_10 0x45 /* play by lba */
521 #define ATAPI_PLAY_MSF 0x47 /* play by MSF address */
522 #define ATAPI_PLAY_TRACK 0x48 /* play by track number */
523 #define ATAPI_PAUSE 0x4b /* pause audio operation */
524 #define ATAPI_READ_DISK_INFO 0x51 /* get disk info structure */
525 #define ATAPI_READ_TRACK_INFO 0x52 /* get track info structure */
526 #define ATAPI_RESERVE_TRACK 0x53 /* reserve track */
527 #define ATAPI_SEND_OPC_INFO 0x54 /* send OPC structurek */
528 #define ATAPI_MODE_SELECT_BIG 0x55 /* set device parameters */
529 #define ATAPI_REPAIR_TRACK 0x58 /* repair track */
530 #define ATAPI_READ_MASTER_CUE 0x59 /* read master CUE info */
531 #define ATAPI_MODE_SENSE_BIG 0x5a /* get device parameters */
532 #define ATAPI_CLOSE_TRACK 0x5b /* close track/session */
533 #define ATAPI_READ_BUFFER_CAPACITY 0x5c /* get buffer capicity */
534 #define ATAPI_SEND_CUE_SHEET 0x5d /* send CUE sheet */
535 #define ATAPI_SERVICE_ACTION_IN 0x96 /* get service data */
536 #define ATAPI_BLANK 0xa1 /* blank the media */
537 #define ATAPI_SEND_KEY 0xa3 /* send DVD key structure */
538 #define ATAPI_REPORT_KEY 0xa4 /* get DVD key structure */
539 #define ATAPI_PLAY_12 0xa5 /* play by lba */
540 #define ATAPI_LOAD_UNLOAD 0xa6 /* changer control command */
541 #define ATAPI_READ_STRUCTURE 0xad /* get DVD structure */
542 #define ATAPI_PLAY_CD 0xb4 /* universal play command */
543 #define ATAPI_SET_SPEED 0xbb /* set drive speed */
544 #define ATAPI_MECH_STATUS 0xbd /* get changer status */
545 #define ATAPI_READ_CD 0xbe /* read data */
546 #define ATAPI_POLL_DSC 0xff /* poll DSC status bit */
549 struct ata_ioc_devices {
552 struct ata_params params[2];
555 /* pr channel ATA ioctl calls */
556 #define IOCATAGMAXCHANNEL _IOR('a', 1, int)
557 #define IOCATAREINIT _IOW('a', 2, int)
558 #define IOCATAATTACH _IOW('a', 3, int)
559 #define IOCATADETACH _IOW('a', 4, int)
560 #define IOCATADEVICES _IOWR('a', 5, struct ata_ioc_devices)
562 /* ATAPI request sense structure */
564 u_int8_t error; /* current or deferred errors */
565 #define ATA_SENSE_VALID 0x80
567 u_int8_t segment; /* segment number */
568 u_int8_t key; /* sense key */
569 #define ATA_SENSE_KEY_MASK 0x0f /* sense key mask */
570 #define ATA_SENSE_NO_SENSE 0x00 /* no specific sense key info */
571 #define ATA_SENSE_RECOVERED_ERROR 0x01 /* command OK, data recovered */
572 #define ATA_SENSE_NOT_READY 0x02 /* no access to drive */
573 #define ATA_SENSE_MEDIUM_ERROR 0x03 /* non-recovered data error */
574 #define ATA_SENSE_HARDWARE_ERROR 0x04 /* non-recoverable HW failure */
575 #define ATA_SENSE_ILLEGAL_REQUEST 0x05 /* invalid command param(s) */
576 #define ATA_SENSE_UNIT_ATTENTION 0x06 /* media changed */
577 #define ATA_SENSE_DATA_PROTECT 0x07 /* write protect */
578 #define ATA_SENSE_BLANK_CHECK 0x08 /* blank check */
579 #define ATA_SENSE_VENDOR_SPECIFIC 0x09 /* vendor specific skey */
580 #define ATA_SENSE_COPY_ABORTED 0x0a /* copy aborted */
581 #define ATA_SENSE_ABORTED_COMMAND 0x0b /* command aborted, try again */
582 #define ATA_SENSE_EQUAL 0x0c /* equal */
583 #define ATA_SENSE_VOLUME_OVERFLOW 0x0d /* volume overflow */
584 #define ATA_SENSE_MISCOMPARE 0x0e /* data dont match the medium */
585 #define ATA_SENSE_RESERVED 0x0f
586 #define ATA_SENSE_ILI 0x20;
587 #define ATA_SENSE_EOM 0x40;
588 #define ATA_SENSE_FILEMARK 0x80;
590 u_int32_t cmd_info; /* cmd information */
591 u_int8_t sense_length; /* additional sense len (n-7) */
592 u_int32_t cmd_specific_info; /* additional cmd spec info */
593 u_int8_t asc; /* additional sense code */
594 u_int8_t ascq; /* additional sense code qual */
595 u_int8_t replaceable_unit_code; /* replaceable unit code */
596 u_int8_t specific; /* sense key specific */
597 #define ATA_SENSE_SPEC_VALID 0x80
598 #define ATA_SENSE_SPEC_MASK 0x7f
600 u_int8_t specific1; /* sense key specific */
601 u_int8_t specific2; /* sense key specific */
605 * SET FEATURES subcommands
609 * SET FEATURES command
610 * Extended Power Conditions subcommand -- ATA_SF_EPC (0x4A)
611 * These values go in the LBA 3:0.
613 #define ATA_SF_EPC_RESTORE 0x00 /* Restore Power Condition Settings */
614 #define ATA_SF_EPC_GOTO 0x01 /* Go To Power Condition */
615 #define ATA_SF_EPC_SET_TIMER 0x02 /* Set Power Condition Timer */
616 #define ATA_SF_EPC_SET_STATE 0x03 /* Set Power Condition State */
617 #define ATA_SF_EPC_ENABLE 0x04 /* Enable the EPC feature set */
618 #define ATA_SF_EPC_DISABLE 0x05 /* Disable the EPC feature set */
619 #define ATA_SF_EPC_SET_SOURCE 0x06 /* Set EPC Power Source */
622 * SET FEATURES command
623 * Extended Power Conditions subcommand -- ATA_SF_EPC (0x4A)
624 * Power Condition ID field
625 * These values go in the count register.
627 #define ATA_EPC_STANDBY_Z 0x00 /* Substate of PM2:Standby */
628 #define ATA_EPC_STANDBY_Y 0x01 /* Substate of PM2:Standby */
629 #define ATA_EPC_IDLE_A 0x81 /* Substate of PM1:Idle */
630 #define ATA_EPC_IDLE_B 0x82 /* Substate of PM1:Idle */
631 #define ATA_EPC_IDLE_C 0x83 /* Substate of PM1:Idle */
632 #define ATA_EPC_ALL 0xff /* All supported power conditions */
635 * SET FEATURES command
636 * Extended Power Conditions subcommand -- ATA_SF_EPC (0x4A)
637 * Restore Power Conditions Settings subcommand
638 * These values go in the LBA register.
640 #define ATA_SF_EPC_RST_DFLT 0x40 /* 1=Rst from Default, 0= from Saved */
641 #define ATA_SF_EPC_RST_SAVE 0x10 /* 1=Save on completion */
644 * SET FEATURES command
645 * Extended Power Conditions subcommand -- ATA_SF_EPC (0x4A)
646 * Got To Power Condition subcommand
647 * These values go in the LBA register.
649 #define ATA_SF_EPC_GOTO_DELAY 0x02000000 /* Delayed entry bit */
650 #define ATA_SF_EPC_GOTO_HOLD 0x01000000 /* Hold Power Cond bit */
653 * SET FEATURES command
654 * Extended Power Conditions subcommand -- ATA_SF_EPC (0x4A)
655 * Set Power Condition Timer subcommand
656 * These values go in the LBA register.
658 #define ATA_SF_EPC_TIMER_MASK 0x00ffff00 /* Timer field */
659 #define ATA_SF_EPC_TIMER_SHIFT 8
660 #define ATA_SF_EPC_TIMER_SEC 0x00000080 /* Timer units, 1=sec, 0=.1s */
661 #define ATA_SF_EPC_TIMER_EN 0x00000020 /* Enable/disable cond. */
662 #define ATA_SF_EPC_TIMER_SAVE 0x00000010 /* Save settings on comp. */
665 * SET FEATURES command
666 * Extended Power Conditions subcommand -- ATA_SF_EPC (0x4A)
667 * Set Power Condition State subcommand
668 * These values go in the LBA register.
670 #define ATA_SF_EPC_SETCON_EN 0x00000020 /* Enable power cond. */
671 #define ATA_SF_EPC_SETCON_SAVE 0x00000010 /* Save settings on comp */
674 * SET FEATURES command
675 * Extended Power Conditions subcommand -- ATA_SF_EPC (0x4A)
676 * Set EPC Power Source subcommand
677 * These values go in the count register.
679 #define ATA_SF_EPC_SRC_UNKNOWN 0x0000 /* Unknown source */
680 #define ATA_SF_EPC_SRC_BAT 0x0001 /* battery source */
681 #define ATA_SF_EPC_SRC_NOT_BAT 0x0002 /* not battery source */
683 #define ATA_LOG_DIRECTORY 0x00 /* Directory of all logs */
684 #define ATA_POWER_COND_LOG 0x08 /* Power Conditions Log */
685 #define ATA_PCL_IDLE 0x00 /* Idle Power Conditions Page */
686 #define ATA_PCL_STANDBY 0x01 /* Standby Power Conditions Page */
687 #define ATA_IDENTIFY_DATA_LOG 0x30 /* Identify Device Data Log */
688 #define ATA_IDL_PAGE_LIST 0x00 /* List of supported pages */
689 #define ATA_IDL_IDENTIFY_DATA 0x01 /* Copy of Identify Device data */
690 #define ATA_IDL_CAPACITY 0x02 /* Capacity */
691 #define ATA_IDL_SUP_CAP 0x03 /* Supported Capabilities */
692 #define ATA_IDL_CUR_SETTINGS 0x04 /* Current Settings */
693 #define ATA_IDL_ATA_STRINGS 0x05 /* ATA Strings */
694 #define ATA_IDL_SECURITY 0x06 /* Security */
695 #define ATA_IDL_PARALLEL_ATA 0x07 /* Parallel ATA */
696 #define ATA_IDL_SERIAL_ATA 0x08 /* Seiral ATA */
697 #define ATA_IDL_ZDI 0x09 /* Zoned Device Information */
699 struct ata_gp_log_dir {
701 #define ATA_GP_LOG_DIR_VERSION 0x0001
702 uint8_t num_pages[255*2]; /* Number of log pages at address */
706 * ATA Power Conditions log descriptor
708 struct ata_power_cond_log_desc {
711 #define ATA_PCL_COND_SUPPORTED 0x80
712 #define ATA_PCL_COND_SAVEABLE 0x40
713 #define ATA_PCL_COND_CHANGEABLE 0x20
714 #define ATA_PCL_DEFAULT_TIMER_EN 0x10
715 #define ATA_PCL_SAVED_TIMER_EN 0x08
716 #define ATA_PCL_CURRENT_TIMER_EN 0x04
717 #define ATA_PCL_HOLD_PC_NOT_SUP 0x02
718 uint8_t reserved2[2];
719 uint8_t default_timer[4];
720 uint8_t saved_timer[4];
721 uint8_t current_timer[4];
722 uint8_t nom_time_to_active[4];
723 uint8_t min_timer[4];
724 uint8_t max_timer[4];
725 uint8_t num_transitions_to_pc[4];
726 uint8_t hours_in_pc[4];
727 uint8_t reserved3[28];
731 * ATA Power Conditions Log (0x08), Idle power conditions page (0x00)
733 struct ata_power_cond_log_idle {
734 struct ata_power_cond_log_desc idle_a_desc;
735 struct ata_power_cond_log_desc idle_b_desc;
736 struct ata_power_cond_log_desc idle_c_desc;
737 uint8_t reserved[320];
741 * ATA Power Conditions Log (0x08), Standby power conditions page (0x01)
743 struct ata_power_cond_log_standby {
744 uint8_t reserved[384];
745 struct ata_power_cond_log_desc standby_y_desc;
746 struct ata_power_cond_log_desc standby_z_desc;
750 * ATA IDENTIFY DEVICE data log (0x30) page 0x00
751 * List of Supported IDENTIFY DEVICE data pages.
753 struct ata_identify_log_pages {
755 #define ATA_IDLOG_REVISION 0x0000000000000001
757 uint8_t entries[503];
761 * ATA IDENTIFY DEVICE data log (0x30)
762 * Capacity (Page 0x02).
764 struct ata_identify_log_capacity {
766 #define ATA_CAP_HEADER_VALID 0x8000000000000000
767 #define ATA_CAP_PAGE_NUM_MASK 0x0000000000ff0000
768 #define ATA_CAP_PAGE_NUM_SHIFT 16
769 #define ATA_CAP_REV_MASK 0x00000000000000ff
771 #define ATA_CAP_CAPACITY_VALID 0x8000000000000000
772 #define ATA_CAP_ACCESSIBLE_CAP 0x0000ffffffffffff
773 uint8_t phys_logical_sect_size[8];
774 #define ATA_CAP_PL_VALID 0x8000000000000000
775 #define ATA_CAP_LTOP_REL_SUP 0x4000000000000000
776 #define ATA_CAP_LOG_SECT_SUP 0x2000000000000000
777 #define ATA_CAP_ALIGN_ERR_MASK 0x0000000000300000
778 #define ATA_CAP_LTOP_MASK 0x00000000000f0000
779 #define ATA_CAP_LOG_SECT_OFF 0x000000000000ffff
780 uint8_t logical_sect_size[8];
781 #define ATA_CAP_LOG_SECT_VALID 0x8000000000000000
782 #define ATA_CAP_LOG_SECT_SIZE 0x00000000ffffffff
783 uint8_t nominal_buffer_size[8];
784 #define ATA_CAP_NOM_BUF_VALID 0x8000000000000000
785 #define ATA_CAP_NOM_BUF_SIZE 0x7fffffffffffffff
786 uint8_t reserved[472];
790 * ATA IDENTIFY DEVICE data log (0x30)
791 * Supported Capabilities (Page 0x03).
794 struct ata_identify_log_sup_cap {
796 #define ATA_SUP_CAP_HEADER_VALID 0x8000000000000000
797 #define ATA_SUP_CAP_PAGE_NUM_MASK 0x0000000000ff0000
798 #define ATA_SUP_CAP_PAGE_NUM_SHIFT 16
799 #define ATA_SUP_CAP_REV_MASK 0x00000000000000ff
801 #define ATA_SUP_CAP_VALID 0x8000000000000000
802 #define ATA_SC_SET_SECT_CONFIG_SUP 0x0002000000000000 /* Set Sect Conf*/
803 #define ATA_SC_ZERO_EXT_SUP 0x0001000000000000 /* Zero EXT */
804 #define ATA_SC_SUCC_NCQ_SENSE_SUP 0x0000800000000000 /* Succ. NCQ Sns */
805 #define ATA_SC_DLC_SUP 0x0000400000000000 /* DLC */
806 #define ATA_SC_RQSN_DEV_FAULT_SUP 0x0000200000000000 /* Req Sns Dev Flt*/
807 #define ATA_SC_DSN_SUP 0x0000100000000000 /* DSN */
808 #define ATA_SC_LP_STANDBY_SUP 0x0000080000000000 /* LP Standby */
809 #define ATA_SC_SET_EPC_PS_SUP 0x0000040000000000 /* Set EPC PS */
810 #define ATA_SC_AMAX_ADDR_SUP 0x0000020000000000 /* AMAX Addr */
811 #define ATA_SC_DRAT_SUP 0x0000008000000000 /* DRAT */
812 #define ATA_SC_LPS_MISALGN_SUP 0x0000004000000000 /* LPS Misalign */
813 #define ATA_SC_RB_DMA_SUP 0x0000001000000000 /* Read Buf DMA */
814 #define ATA_SC_WB_DMA_SUP 0x0000000800000000 /* Write Buf DMA */
815 #define ATA_SC_DNLD_MC_DMA_SUP 0x0000000200000000 /* DL MCode DMA */
816 #define ATA_SC_28BIT_SUP 0x0000000100000000 /* 28-bit */
817 #define ATA_SC_RZAT_SUP 0x0000000080000000 /* RZAT */
818 #define ATA_SC_NOP_SUP 0x0000000020000000 /* NOP */
819 #define ATA_SC_READ_BUFFER_SUP 0x0000000010000000 /* Read Buffer */
820 #define ATA_SC_WRITE_BUFFER_SUP 0x0000000008000000 /* Write Buffer */
821 #define ATA_SC_READ_LOOK_AHEAD_SUP 0x0000000002000000 /* Read Look-Ahead*/
822 #define ATA_SC_VOLATILE_WC_SUP 0x0000000001000000 /* Volatile WC */
823 #define ATA_SC_SMART_SUP 0x0000000000800000 /* SMART */
824 #define ATA_SC_FLUSH_CACHE_EXT_SUP 0x0000000000400000 /* Flush Cache Ext */
825 #define ATA_SC_48BIT_SUP 0x0000000000100000 /* 48-Bit */
826 #define ATA_SC_SPINUP_SUP 0x0000000000040000 /* Spin-Up */
827 #define ATA_SC_PUIS_SUP 0x0000000000020000 /* PUIS */
828 #define ATA_SC_APM_SUP 0x0000000000010000 /* APM */
829 #define ATA_SC_DL_MICROCODE_SUP 0x0000000000004000 /* DL Microcode */
830 #define ATA_SC_UNLOAD_SUP 0x0000000000002000 /* Unload */
831 #define ATA_SC_WRITE_FUA_EXT_SUP 0x0000000000001000 /* Write FUA EXT */
832 #define ATA_SC_GPL_SUP 0x0000000000000800 /* GPL */
833 #define ATA_SC_STREAMING_SUP 0x0000000000000400 /* Streaming */
834 #define ATA_SC_SMART_SELFTEST_SUP 0x0000000000000100 /* SMART self-test */
835 #define ATA_SC_SMART_ERR_LOG_SUP 0x0000000000000080 /* SMART Err Log */
836 #define ATA_SC_EPC_SUP 0x0000000000000040 /* EPC */
837 #define ATA_SC_SENSE_SUP 0x0000000000000020 /* Sense data */
838 #define ATA_SC_FREEFALL_SUP 0x0000000000000010 /* Free-Fall */
839 #define ATA_SC_DM_MODE3_SUP 0x0000000000000008 /* DM Mode 3 */
840 #define ATA_SC_GPL_DMA_SUP 0x0000000000000004 /* GPL DMA */
841 #define ATA_SC_WRITE_UNCOR_SUP 0x0000000000000002 /* Write uncorr. */
842 #define ATA_SC_WRV_SUP 0x0000000000000001 /* WRV */
843 uint8_t download_code_cap[8];
844 #define ATA_DL_CODE_VALID 0x8000000000000000
845 #define ATA_DLC_DM_OFFSETS_DEFER_SUP 0x0000000400000000
846 #define ATA_DLC_DM_IMMED_SUP 0x0000000200000000
847 #define ATA_DLC_DM_OFF_IMMED_SUP 0x0000000100000000
848 #define ATA_DLC_DM_MAX_XFER_SIZE_MASK 0x00000000ffff0000
849 #define ATA_DLC_DM_MAX_XFER_SIZE_SHIFT 16
850 #define ATA_DLC_DM_MIN_XFER_SIZE_MASK 0x000000000000ffff
851 uint8_t nom_media_rotation_rate[8];
852 #define ATA_NOM_MEDIA_ROTATION_VALID 0x8000000000000000
853 #define ATA_ROTATION_MASK 0x000000000000ffff
854 uint8_t form_factor[8];
855 #define ATA_FORM_FACTOR_VALID 0x8000000000000000
856 #define ATA_FF_MASK 0x000000000000000f
857 #define ATA_FF_NOT_REPORTED 0x0000000000000000 /* Not reported */
858 #define ATA_FF_525_IN 0x0000000000000001 /* 5.25 inch */
859 #define ATA_FF_35_IN 0x0000000000000002 /* 3.5 inch */
860 #define ATA_FF_25_IN 0x0000000000000003 /* 2.5 inch */
861 #define ATA_FF_18_IN 0x0000000000000004 /* 1.8 inch */
862 #define ATA_FF_LT_18_IN 0x0000000000000005 /* < 1.8 inch */
863 #define ATA_FF_MSATA 0x0000000000000006 /* mSATA */
864 #define ATA_FF_M2 0x0000000000000007 /* M.2 */
865 #define ATA_FF_MICROSSD 0x0000000000000008 /* MicroSSD */
866 #define ATA_FF_CFAST 0x0000000000000009 /* CFast */
867 uint8_t wrv_sec_cnt_mode3[8];
868 #define ATA_WRV_MODE3_VALID 0x8000000000000000
869 #define ATA_WRV_MODE3_COUNT 0x00000000ffffffff
870 uint8_t wrv_sec_cnt_mode2[8];
871 #define ATA_WRV_MODE2_VALID 0x8000000000000000
872 #define ATA_WRV_MODE2_COUNT 0x00000000ffffffff
874 /* XXX KDM need to figure out how to handle 128-bit fields */
876 #define ATA_DSM_VALID 0x8000000000000000
877 #define ATA_LB_MARKUP_SUP 0x000000000000ff00
878 #define ATA_TRIM_SUP 0x0000000000000001
879 uint8_t util_per_unit_time[16];
880 /* XXX KDM need to figure out how to handle 128-bit fields */
881 uint8_t util_usage_rate_sup[8];
882 #define ATA_UTIL_USAGE_RATE_VALID 0x8000000000000000
883 #define ATA_SETTING_RATE_SUP 0x0000000000800000
884 #define ATA_SINCE_POWERON_SUP 0x0000000000000100
885 #define ATA_POH_RATE_SUP 0x0000000000000010
886 #define ATA_DATE_TIME_RATE_SUP 0x0000000000000001
887 uint8_t zoned_cap[8];
888 #define ATA_ZONED_VALID 0x8000000000000000
889 #define ATA_ZONED_MASK 0x0000000000000003
890 uint8_t sup_zac_cap[8];
891 #define ATA_SUP_ZAC_CAP_VALID 0x8000000000000000
892 #define ATA_ND_RWP_SUP 0x0000000000000010 /* Reset Write Ptr*/
893 #define ATA_ND_FINISH_ZONE_SUP 0x0000000000000008 /* Finish Zone */
894 #define ATA_ND_CLOSE_ZONE_SUP 0x0000000000000004 /* Close Zone */
895 #define ATA_ND_OPEN_ZONE_SUP 0x0000000000000002 /* Open Zone */
896 #define ATA_REPORT_ZONES_SUP 0x0000000000000001 /* Report Zones */
897 uint8_t reserved[392];
901 * ATA Identify Device Data Log Zoned Device Information Page (0x09).
902 * Current as of ZAC r04a, August 25, 2015.
904 struct ata_zoned_info_log {
906 #define ATA_ZDI_HEADER_VALID 0x8000000000000000
907 #define ATA_ZDI_PAGE_NUM_MASK 0x0000000000ff0000
908 #define ATA_ZDI_PAGE_NUM_SHIFT 16
909 #define ATA_ZDI_REV_MASK 0x00000000000000ff
910 uint8_t zoned_cap[8];
911 #define ATA_ZDI_CAP_VALID 0x8000000000000000
912 #define ATA_ZDI_CAP_URSWRZ 0x0000000000000001
913 uint8_t zoned_settings[8];
914 #define ATA_ZDI_SETTINGS_VALID 0x8000000000000000
915 uint8_t optimal_seq_zones[8];
916 #define ATA_ZDI_OPT_SEQ_VALID 0x8000000000000000
917 #define ATA_ZDI_OPT_SEQ_MASK 0x00000000ffffffff
918 uint8_t optimal_nonseq_zones[8];
919 #define ATA_ZDI_OPT_NS_VALID 0x8000000000000000
920 #define ATA_ZDI_OPT_NS_MASK 0x00000000ffffffff
921 uint8_t max_seq_req_zones[8];
922 #define ATA_ZDI_MAX_SEQ_VALID 0x8000000000000000
923 #define ATA_ZDI_MAX_SEQ_MASK 0x00000000ffffffff
924 uint8_t version_info[8];
925 #define ATA_ZDI_VER_VALID 0x8000000000000000
926 #define ATA_ZDI_VER_ZAC_SUP 0x0100000000000000
927 #define ATA_ZDI_VER_ZAC_MASK 0x00000000000000ff
928 uint8_t reserved[456];
931 struct ata_ioc_request {
941 struct atapi_sense sense;
947 #define ATA_CMD_CONTROL 0x01
948 #define ATA_CMD_READ 0x02
949 #define ATA_CMD_WRITE 0x04
950 #define ATA_CMD_ATAPI 0x08
956 struct ata_security_password {
958 #define ATA_SECURITY_PASSWORD_USER 0x0000
959 #define ATA_SECURITY_PASSWORD_MASTER 0x0001
960 #define ATA_SECURITY_ERASE_NORMAL 0x0000
961 #define ATA_SECURITY_ERASE_ENHANCED 0x0002
962 #define ATA_SECURITY_LEVEL_HIGH 0x0000
963 #define ATA_SECURITY_LEVEL_MAXIMUM 0x0100
965 u_int8_t password[32];
967 u_int16_t reserved[238];
970 /* pr device ATA ioctl calls */
971 #define IOCATAREQUEST _IOWR('a', 100, struct ata_ioc_request)
972 #define IOCATAGPARM _IOR('a', 101, struct ata_params)
973 #define IOCATAGMODE _IOR('a', 102, int)
974 #define IOCATASMODE _IOW('a', 103, int)
976 #define IOCATAGSPINDOWN _IOR('a', 104, int)
977 #define IOCATASSPINDOWN _IOW('a', 105, int)
980 struct ata_ioc_raid_config {
983 #define AR_JBOD 0x0001
984 #define AR_SPAN 0x0002
985 #define AR_RAID0 0x0004
986 #define AR_RAID1 0x0008
987 #define AR_RAID01 0x0010
988 #define AR_RAID3 0x0020
989 #define AR_RAID4 0x0040
990 #define AR_RAID5 0x0080
995 #define AR_DEGRADED 2
996 #define AR_REBUILDING 4
1003 struct ata_ioc_raid_status {
1012 #define AR_DISK_ONLINE 0x01
1013 #define AR_DISK_PRESENT 0x02
1014 #define AR_DISK_SPARE 0x04
1019 /* ATA RAID ioctl calls */
1020 #define IOCATARAIDCREATE _IOWR('a', 200, struct ata_ioc_raid_config)
1021 #define IOCATARAIDDELETE _IOW('a', 201, int)
1022 #define IOCATARAIDSTATUS _IOWR('a', 202, struct ata_ioc_raid_status)
1023 #define IOCATARAIDADDSPARE _IOW('a', 203, struct ata_ioc_raid_config)
1024 #define IOCATARAIDREBUILD _IOW('a', 204, int)
1026 #endif /* _SYS_ATA_H_ */
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