2 * Copyright (c) 2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/ioccom.h>
36 #define ATAPI_PSIZE_12 0 /* 12 bytes */
37 #define ATAPI_PSIZE_16 1 /* 16 bytes */
39 #define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */
40 #define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */
41 #define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */
43 #define ATAPI_TYPE_DIRECT 0 /* disk/floppy */
44 #define ATAPI_TYPE_TAPE 1 /* streaming tape */
45 #define ATAPI_TYPE_CDROM 5 /* CD-ROM device */
46 #define ATAPI_TYPE_OPTICAL 7 /* optical disk */
48 #define ATA_PROTO_ATA 0
49 #define ATA_PROTO_ATAPI 1
51 #define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */
52 #define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */
53 #define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */
55 #define ATA_FLAG_54_58 1 /* words 54-58 valid */
56 #define ATA_FLAG_64_70 2 /* words 64-70 valid */
57 #define ATA_FLAG_88 4 /* word 88 valid */
59 /* ATA/ATAPI device parameter information */
62 #if BYTE_ORDER == LITTLE_ENDIAN
63 /*000*/ u_int16_t packet_size :2; /* packet command size */
65 u_int16_t incomplete :1;
67 u_int16_t drq_type :2; /* DRQ type */
69 u_int16_t removable :1; /* device is removable */
70 u_int16_t type :5; /* device type */
73 u_int16_t cmd_protocol :1; /* command protocol */
75 u_int16_t cmd_protocol :1; /* command protocol */
78 u_int16_t type :5; /* device type */
79 u_int16_t removable :1; /* device is removable */
81 u_int16_t drq_type :2; /* DRQ type */
83 u_int16_t incomplete :1;
85 u_int16_t packet_size :2; /* packet command size */
88 /*001*/ u_int16_t cylinders; /* # of cylinders */
90 /*003*/ u_int16_t heads; /* # heads */
93 /*006*/ u_int16_t sectors; /* # sectors/track */
94 /*007*/ u_int16_t vendor7[3];
95 /*010*/ u_int8_t serial[20]; /* serial number */
99 /*023*/ u_int8_t revision[8]; /* firmware revision */
100 /*027*/ u_int8_t model[40]; /* model name */
102 #if BYTE_ORDER == LITTLE_ENDIAN
103 /*047*/ u_int16_t sectors_intr:8; /* sectors per interrupt */
107 u_int16_t sectors_intr:8; /* sectors per interrupt */
110 /*048*/ u_int16_t usedmovsd; /* double word read/write? */
112 #if BYTE_ORDER == LITTLE_ENDIAN
113 /*049*/ u_int16_t retired49:8;
114 u_int16_t support_dma :1; /* DMA supported */
115 u_int16_t support_lba :1; /* LBA supported */
116 u_int16_t disable_iordy :1; /* IORDY may be disabled */
117 u_int16_t support_iordy :1; /* IORDY supported */
118 u_int16_t softreset :1; /* needs softreset when busy */
119 u_int16_t stdby_ovlap :1; /* standby/overlap supported */
120 u_int16_t support_queueing:1; /* supports queuing overlap */
121 u_int16_t support_idma :1; /* interleaved DMA supported */
123 /*050*/ u_int16_t device_stdby_min:1;
125 u_int16_t capability_one:1;
126 u_int16_t capability_zero:1;
128 /*051*/ u_int16_t vendor51:8;
129 u_int16_t retired_piomode:8; /* PIO modes 0-2 */
130 /*052*/ u_int16_t vendor52:8;
131 u_int16_t retired_dmamode:8; /* DMA modes, not ATA-3 */
133 u_int16_t support_idma :1; /* interleaved DMA supported */
134 u_int16_t support_queueing:1; /* supports queuing overlap */
135 u_int16_t stdby_ovlap :1; /* standby/overlap supported */
136 u_int16_t softreset :1; /* needs softreset when busy */
137 u_int16_t support_iordy :1; /* IORDY supported */
138 u_int16_t disable_iordy :1; /* IORDY may be disabled */
139 u_int16_t support_lba :1; /* LBA supported */
140 u_int16_t support_dma :1; /* DMA supported */
141 u_int16_t retired49:8;
143 u_int16_t capability_zero:1;
144 u_int16_t capability_one:1;
146 u_int16_t device_stdby_min:1;
148 u_int16_t retired_piomode:8; /* PIO modes 0-2 */
149 u_int16_t vendor51:8;
150 u_int16_t retired_dmamode:8; /* DMA modes, not ATA-3 */
151 u_int16_t vendor52:8;
154 /*053*/ u_int16_t atavalid; /* fields valid */
156 u_int16_t obsolete54[5];
158 #if BYTE_ORDER == LITTLE_ENDIAN
159 /*059*/ u_int16_t multi_count:8;
160 u_int16_t multi_valid:1;
164 u_int16_t multi_valid:1;
165 u_int16_t multi_count:8;
168 /*060*/ u_int16_t lba_size_1;
169 u_int16_t lba_size_2;
170 u_int16_t obsolete62;
171 /*063*/ u_int16_t mwdmamodes; /* multiword DMA modes */
172 /*064*/ u_int16_t apiomodes; /* advanced PIO modes */
174 /*065*/ u_int16_t mwdmamin; /* min. M/W DMA time/word ns */
175 /*066*/ u_int16_t mwdmarec; /* rec. M/W DMA time ns */
176 /*067*/ u_int16_t pioblind; /* min. PIO cycle w/o flow */
177 /*068*/ u_int16_t pioiordy; /* min. PIO cycle IORDY flow */
178 u_int16_t reserved69;
179 u_int16_t reserved70;
180 /*071*/ u_int16_t rlsovlap; /* rel time (us) for overlap */
181 /*072*/ u_int16_t rlsservice; /* rel time (us) for service */
182 u_int16_t reserved73;
183 u_int16_t reserved74;
185 #if BYTE_ORDER == LITTLE_ENDIAN
186 /*075*/ u_int16_t queuelen:5;
190 u_int16_t queuelen:5;
193 u_int16_t reserved76;
194 u_int16_t reserved77;
195 u_int16_t reserved78;
196 u_int16_t reserved79;
197 /*080*/ u_int16_t version_major;
198 /*081*/ u_int16_t version_minor;
200 #if BYTE_ORDER == LITTLE_ENDIAN
201 /*082/085*/ u_int16_t smart:1;
202 u_int16_t security:1;
203 u_int16_t removable:1;
204 u_int16_t power_mngt:1;
206 u_int16_t write_cache:1;
207 u_int16_t look_ahead:1;
208 u_int16_t release_irq:1;
209 u_int16_t service_irq:1;
211 u_int16_t protected:1;
213 u_int16_t write_buffer:1;
214 u_int16_t read_buffer:1;
218 /*083/086*/ u_int16_t microcode:1;
226 u_int16_t max_security:1;
227 u_int16_t auto_acoustic:1;
228 u_int16_t address48:1;
229 u_int16_t config_overlay:1;
230 u_int16_t flush_cache:1;
231 u_int16_t flush_cache48:1;
232 u_int16_t support_one:1;
233 u_int16_t support_zero:1;
235 /*084/087*/ u_int16_t smart_error_log:1;
236 u_int16_t smart_self_test:1;
237 u_int16_t media_serial_no:1;
238 u_int16_t media_card_pass:1;
239 u_int16_t streaming:1;
242 u_int16_t extended_one:1;
243 u_int16_t extended_zero:1;
247 u_int16_t read_buffer:1;
248 u_int16_t write_buffer:1;
250 u_int16_t protected:1;
252 u_int16_t service_irq:1;
253 u_int16_t release_irq:1;
254 u_int16_t look_ahead:1;
255 u_int16_t write_cache:1;
257 u_int16_t power_mngt:1;
258 u_int16_t removable:1;
259 u_int16_t security:1;
262 u_int16_t support_zero:1;
263 u_int16_t support_one:1;
264 u_int16_t flush_cache48:1;
265 u_int16_t flush_cache:1;
266 u_int16_t config_overlay:1;
267 u_int16_t address48:1;
268 u_int16_t auto_acoustic:1;
269 u_int16_t max_security:1;
277 u_int16_t microcode:1;
279 u_int16_t extended_zero:1;
280 u_int16_t extended_one:1;
283 u_int16_t streaming:1;
284 u_int16_t media_card_pass:1;
285 u_int16_t media_serial_no:1;
286 u_int16_t smart_self_test:1;
287 u_int16_t smart_error_log:1;
291 /*088*/ u_int16_t udmamodes; /* UltraDMA modes */
292 /*089*/ u_int16_t erase_time;
293 /*090*/ u_int16_t enhanced_erase_time;
294 /*091*/ u_int16_t apm_value;
295 /*092*/ u_int16_t master_passwd_revision;
297 #if BYTE_ORDER == LITTLE_ENDIAN
298 /*093*/ u_int16_t hwres_master :8;
299 u_int16_t hwres_slave :5;
300 u_int16_t hwres_cblid :1;
301 u_int16_t hwres_valid:2;
303 /*094*/ u_int16_t current_acoustic:8;
304 u_int16_t vendor_acoustic:8;
306 u_int16_t hwres_valid:2;
307 u_int16_t hwres_cblid :1;
308 u_int16_t hwres_slave :5;
309 u_int16_t hwres_master :8;
311 u_int16_t vendor_acoustic:8;
312 u_int16_t current_acoustic:8;
315 /*095*/ u_int16_t stream_min_req_size;
316 /*096*/ u_int16_t stream_transfer_time;
317 /*097*/ u_int16_t stream_access_latency;
318 /*098*/ u_int32_t stream_granularity;
319 /*100*/ u_int16_t lba_size48_1;
320 u_int16_t lba_size48_2;
321 u_int16_t lba_size48_3;
322 u_int16_t lba_size48_4;
323 u_int16_t reserved104[23];
324 /*127*/ u_int16_t removable_status;
325 /*128*/ u_int16_t security_status;
326 u_int16_t reserved129[31];
327 /*160*/ u_int16_t cfa_powermode1;
328 u_int16_t reserved161[14];
329 /*176*/ u_int16_t media_serial[30];
330 u_int16_t reserved206[49];
331 /*255*/ u_int16_t integrity;
334 #define ATA_MODE_MASK 0x0f
335 #define ATA_DMA_MASK 0xf0
337 #define ATA_PIO0 0x08
338 #define ATA_PIO1 0x09
339 #define ATA_PIO2 0x0a
340 #define ATA_PIO3 0x0b
341 #define ATA_PIO4 0x0c
343 #define ATA_WDMA 0x20
344 #define ATA_WDMA2 0x22
345 #define ATA_UDMA 0x40
346 #define ATA_UDMA2 0x42
347 #define ATA_UDMA4 0x44
348 #define ATA_UDMA5 0x45
349 #define ATA_UDMA6 0x46
362 #define ATARAIDREBUILD 8
363 #define ATARAIDCREATE 9
364 #define ATARAIDDELETE 10
365 #define ATARAIDSTATUS 11
366 #define ATAENCSTAT 12
375 struct ata_params params[2];
395 #define AR_DEGRADED 2
396 #define AR_REBUILDING 4
411 #define ATAPI_CMD_CTRL 0x00
412 #define ATAPI_CMD_READ 0x01
413 #define ATAPI_CMD_WRITE 0x02
422 #define IOCATA _IOWR('a', 1, struct ata_cmd)
424 #endif /* _SYS_ATA_H_ */