1 /* $NetBSD: gpio.h,v 1.7 2009/09/25 20:27:50 mbalmer Exp $ */
2 /* $OpenBSD: gpio.h,v 1.7 2008/11/26 14:51:20 mbalmer Exp $ */
4 * SPDX-License-Identifier: (BSD-2-Clause-FreeBSD AND ISC)
6 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice unmodified, this list of conditions, and the following
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * Copyright (c) 2009 Marc Balmer <marc@msys.ch>
37 * Copyright (c) 2004 Alexander Yurchenko <grange@openbsd.org>
39 * Permission to use, copy, modify, and distribute this software for any
40 * purpose with or without fee is hereby granted, provided that the above
41 * copyright notice and this permission notice appear in all copies.
43 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
44 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
46 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
47 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
48 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
49 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
55 #include <sys/ioccom.h>
58 #define GPIO_PIN_LOW 0x00 /* low level (logical 0) */
59 #define GPIO_PIN_HIGH 0x01 /* high level (logical 1) */
61 /* Max name length of a pin */
62 #define GPIOMAXNAME 64
64 /* GPIO pin configuration flags */
65 #define GPIO_PIN_INPUT 0x00000001 /* input direction */
66 #define GPIO_PIN_OUTPUT 0x00000002 /* output direction */
67 #define GPIO_PIN_OPENDRAIN 0x00000004 /* open-drain output */
68 #define GPIO_PIN_PUSHPULL 0x00000008 /* push-pull output */
69 #define GPIO_PIN_TRISTATE 0x00000010 /* output disabled */
70 #define GPIO_PIN_PULLUP 0x00000020 /* internal pull-up enabled */
71 #define GPIO_PIN_PULLDOWN 0x00000040 /* internal pull-down enabled */
72 #define GPIO_PIN_INVIN 0x00000080 /* invert input */
73 #define GPIO_PIN_INVOUT 0x00000100 /* invert output */
74 #define GPIO_PIN_PULSATE 0x00000200 /* pulsate in hardware */
75 #define GPIO_PIN_PRESET_LOW 0x00000400 /* preset pin to high or */
76 #define GPIO_PIN_PRESET_HIGH 0x00000800 /* low before enabling output */
77 /* GPIO interrupt capabilities */
78 #define GPIO_INTR_NONE 0x00000000 /* no interrupt support */
79 #define GPIO_INTR_LEVEL_LOW 0x00010000 /* level trigger, low */
80 #define GPIO_INTR_LEVEL_HIGH 0x00020000 /* level trigger, high */
81 #define GPIO_INTR_EDGE_RISING 0x00040000 /* edge trigger, rising */
82 #define GPIO_INTR_EDGE_FALLING 0x00080000 /* edge trigger, falling */
83 #define GPIO_INTR_EDGE_BOTH 0x00100000 /* edge trigger, both */
84 #define GPIO_INTR_MASK (GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | \
85 GPIO_INTR_EDGE_RISING | \
86 GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH)
89 uint32_t gp_pin; /* pin number */
90 char gp_name[GPIOMAXNAME]; /* human-readable name */
91 uint32_t gp_caps; /* capabilities */
92 uint32_t gp_flags; /* current flags */
95 /* GPIO pin request (read/write/toggle) */
97 uint32_t gp_pin; /* pin number */
98 uint32_t gp_value; /* value */
102 * gpio_access_32 / GPIOACCESS32
104 * Simultaneously read and/or change up to 32 adjacent pins.
105 * If the device cannot change the pins simultaneously, returns EOPNOTSUPP.
107 * This accesses an adjacent set of up to 32 pins starting at first_pin within
108 * the device's collection of pins. How the hardware pins are mapped to the 32
109 * bits in the arguments is device-specific. It is expected that lower-numbered
110 * pins in the device's number space map linearly to lower-ordered bits within
111 * the 32-bit words (i.e., bit 0 is first_pin, bit 1 is first_pin+1, etc).
112 * Other mappings are possible; know your device.
114 * Some devices may limit the value of first_pin to 0, or to multiples of 16 or
115 * 32 or some other hardware-specific number; to access pin 2 would require
116 * first_pin to be zero and then manipulate bit (1 << 2) in the 32-bit word.
117 * Invalid values in first_pin result in an EINVAL error return.
119 * The starting state of the pins is captured and stored in orig_pins, then the
120 * pins are set to ((starting_state & ~clear_pins) ^ change_pins).
122 * Clear Change Hardware pin after call
124 * 0 1 Opposite of current value
128 struct gpio_access_32 {
129 uint32_t first_pin; /* First pin in group of 32 adjacent */
130 uint32_t clear_pins; /* Pins are changed using: */
131 uint32_t change_pins; /* ((hwstate & ~clear_pins) ^ change_pins) */
132 uint32_t orig_pins; /* Returned hwstate of pins before change. */
136 * gpio_config_32 / GPIOCONFIG32
138 * Simultaneously configure up to 32 adjacent pins. This is intended to change
139 * the configuration of all the pins simultaneously, such that pins configured
140 * for output all begin to drive the configured values simultaneously, but not
141 * all hardware can do that, so the driver "does the best it can" in this
142 * regard. Notably unlike pin_access_32(), this does NOT fail if the pins
143 * cannot be atomically configured; it is expected that callers understand the
144 * hardware and have decided to live with any such limitations it may have.
146 * The pin_flags argument is an array of GPIO_PIN_xxxx flags. If the array
147 * contains any GPIO_PIN_OUTPUT flags, the driver will manipulate the hardware
148 * such that all output pins become driven with the proper initial values
149 * simultaneously if it can. The elements in the array map to pins in the same
150 * way that bits are mapped by pin_acces_32(), and the same restrictions may
151 * apply. For example, to configure pins 2 and 3 it may be necessary to set
152 * first_pin to zero and only populate pin_flags[2] and pin_flags[3]. If a
153 * given array entry doesn't contain GPIO_PIN_INPUT or GPIO_PIN_OUTPUT then no
154 * configuration is done for that pin.
156 * Some devices may limit the value of first_pin to 0, or to multiples of 16 or
157 * 32 or some other hardware-specific number. Invalid values in first_pin or
158 * num_pins result in an error return with errno set to EINVAL.
160 struct gpio_config_32 {
163 uint32_t pin_flags[32];
169 #define GPIOMAXPIN _IOR('G', 0, int)
170 #define GPIOGETCONFIG _IOWR('G', 1, struct gpio_pin)
171 #define GPIOSETCONFIG _IOW('G', 2, struct gpio_pin)
172 #define GPIOGET _IOWR('G', 3, struct gpio_req)
173 #define GPIOSET _IOW('G', 4, struct gpio_req)
174 #define GPIOTOGGLE _IOWR('G', 5, struct gpio_req)
175 #define GPIOSETNAME _IOW('G', 6, struct gpio_pin)
176 #define GPIOACCESS32 _IOWR('G', 7, struct gpio_access_32)
177 #define GPIOCONFIG32 _IOW('G', 8, struct gpio_config_32)
179 #endif /* __GPIO_H__ */