2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1997, Stefan Esser <se@FreeBSD.ORG>
5 * Copyright (c) 1997, 1998, 1999, Kenneth D. Merry <ken@FreeBSD.ORG>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <sys/ioccom.h>
38 #define PCI_MAXNAMELEN 16
41 PCI_GETCONF_LAST_DEVICE,
42 PCI_GETCONF_LIST_CHANGED,
43 PCI_GETCONF_MORE_DEVS,
48 PCI_GETCONF_NO_MATCH = 0x0000,
49 PCI_GETCONF_MATCH_DOMAIN = 0x0001,
50 PCI_GETCONF_MATCH_BUS = 0x0002,
51 PCI_GETCONF_MATCH_DEV = 0x0004,
52 PCI_GETCONF_MATCH_FUNC = 0x0008,
53 PCI_GETCONF_MATCH_NAME = 0x0010,
54 PCI_GETCONF_MATCH_UNIT = 0x0020,
55 PCI_GETCONF_MATCH_VENDOR = 0x0040,
56 PCI_GETCONF_MATCH_DEVICE = 0x0080,
57 PCI_GETCONF_MATCH_CLASS = 0x0100
61 u_int32_t pc_domain; /* domain number */
62 u_int8_t pc_bus; /* bus number */
63 u_int8_t pc_dev; /* device on this bus */
64 u_int8_t pc_func; /* function on this device */
68 struct pcisel pc_sel; /* domain+bus+slot+function */
69 u_int8_t pc_hdr; /* PCI header type */
70 u_int16_t pc_subvendor; /* card vendor ID */
71 u_int16_t pc_subdevice; /* card device ID, assigned by
73 u_int16_t pc_vendor; /* chip vendor ID */
74 u_int16_t pc_device; /* chip device ID, assigned by
76 u_int8_t pc_class; /* chip PCI class */
77 u_int8_t pc_subclass; /* chip PCI subclass */
78 u_int8_t pc_progif; /* chip PCI programming interface */
79 u_int8_t pc_revid; /* chip revision ID */
80 char pd_name[PCI_MAXNAMELEN + 1]; /* device name */
81 u_long pd_unit; /* device unit number */
84 struct pci_match_conf {
85 struct pcisel pc_sel; /* domain+bus+slot+function */
86 char pd_name[PCI_MAXNAMELEN + 1]; /* device name */
87 u_long pd_unit; /* Unit number */
88 u_int16_t pc_vendor; /* PCI Vendor ID */
89 u_int16_t pc_device; /* PCI Device ID */
90 u_int8_t pc_class; /* PCI class */
91 pci_getconf_flags flags; /* Matching expression */
95 u_int32_t pat_buf_len; /* pattern buffer length */
96 u_int32_t num_patterns; /* number of patterns */
97 struct pci_match_conf *patterns; /* pattern buffer */
98 u_int32_t match_buf_len; /* match buffer length */
99 u_int32_t num_matches; /* number of matches returned */
100 struct pci_conf *matches; /* match buffer */
101 u_int32_t offset; /* offset into device list */
102 u_int32_t generation; /* device list generation */
103 pci_getconf_status status; /* request status */
107 struct pcisel pi_sel; /* device to operate on */
108 int pi_reg; /* configuration register to examine */
109 int pi_width; /* width (in bytes) of read or write */
110 u_int32_t pi_data; /* data to write or result of read */
114 struct pcisel pbi_sel; /* device to operate on */
115 int pbi_reg; /* starting address of BAR */
116 int pbi_enabled; /* decoding enabled */
117 uint64_t pbi_base; /* current value of BAR */
118 uint64_t pbi_length; /* length of BAR */
121 struct pci_vpd_element {
128 #define PVE_FLAG_IDENT 0x01 /* Element is the string identifier */
129 #define PVE_FLAG_RW 0x02 /* Element is read/write */
131 #define PVE_NEXT(pve) \
132 ((struct pci_vpd_element *)((char *)(pve) + \
133 sizeof(struct pci_vpd_element) + (pve)->pve_datalen))
135 struct pci_list_vpd_io {
136 struct pcisel plvi_sel; /* device to operate on */
137 size_t plvi_len; /* size of the data area */
138 struct pci_vpd_element *plvi_data;
141 struct pci_bar_mmap {
142 void *pbm_map_base; /* (sometimes IN)/OUT mmaped base */
143 size_t pbm_map_length; /* mapped length of the BAR, multiple
145 uint64_t pbm_bar_length; /* actual length of the BAR */
146 int pbm_bar_off; /* offset from the mapped base to the
148 struct pcisel pbm_sel; /* device to operate on */
149 int pbm_reg; /* starting address of BAR */
154 #define PCIIO_BAR_MMAP_FIXED 0x01
155 #define PCIIO_BAR_MMAP_EXCL 0x02
156 #define PCIIO_BAR_MMAP_RW 0x04
157 #define PCIIO_BAR_MMAP_ACTIVATE 0x08
159 #define PCIOCGETCONF _IOWR('p', 5, struct pci_conf_io)
160 #define PCIOCREAD _IOWR('p', 2, struct pci_io)
161 #define PCIOCWRITE _IOWR('p', 3, struct pci_io)
162 #define PCIOCATTACHED _IOWR('p', 4, struct pci_io)
163 #define PCIOCGETBAR _IOWR('p', 6, struct pci_bar_io)
164 #define PCIOCLISTVPD _IOWR('p', 7, struct pci_list_vpd_io)
165 #define PCIOCBARMMAP _IOWR('p', 8, struct pci_bar_mmap)
167 #endif /* !_SYS_PCIIO_H_ */