sys/x86/cpufreq/hwpstate.c

   1 /*-
   2  * Copyright (c) 2005 Nate Lawson
   3  * Copyright (c) 2004 Colin Percival
   4  * Copyright (c) 2004-2005 Bruno Durcot
   5  * Copyright (c) 2004 FUKUDA Nobuhiko
   6  * Copyright (c) 2009 Michael Reifenberger
   7  * Copyright (c) 2009 Norikatsu Shigemura
   8  * Copyright (c) 2008-2009 Gen Otsuji
   9  *
  10  * This code is depending on kern_cpu.c, est.c, powernow.c, p4tcc.c, smist.c
  11  * in various parts. The authors of these files are Nate Lawson,
  12  * Colin Percival, Bruno Durcot, and FUKUDA Nobuhiko.
  13  * This code contains patches by Michael Reifenberger and Norikatsu Shigemura.
  14  * Thank you.
  15  *
  16  * Redistribution and use in source and binary forms, with or without
  17  * modification, are permitted providing that the following conditions
  18  * are met:
  19  * 1. Redistributions of source code must retain the above copyright
  20  *    notice, this list of conditions and the following disclaimer.
  21  * 2. Redistributions in binary form must reproduce the above copyright
  22  *    notice, this list of conditions and the following disclaimer in the
  23  *    documentation and/or other materials provided with the distribution.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR
  26  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  27  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  28  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  29  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  30  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  31  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  32  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  33  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  34  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /*
  39  * For more info:
  40  * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 10h Processors
  41  * 31116 Rev 3.20  February 04, 2009
  42  * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 11h Processors
  43  * 41256 Rev 3.00 - July 07, 2008
  44  */
  45
  46 #include <sys/cdefs.h>
  47 __FBSDID("$FreeBSD$");
  48
  49 #include <sys/param.h>
  50 #include <sys/bus.h>
  51 #include <sys/cpu.h>
  52 #include <sys/kernel.h>
  53 #include <sys/module.h>
  54 #include <sys/malloc.h>
  55 #include <sys/proc.h>
  56 #include <sys/pcpu.h>
  57 #include <sys/smp.h>
  58 #include <sys/sched.h>
  59
  60 #include <machine/md_var.h>
  61 #include <machine/cputypes.h>
  62 #include <machine/specialreg.h>
  63
  64 #include <contrib/dev/acpica/include/acpi.h>
  65
  66 #include <dev/acpica/acpivar.h>
  67
  68 #include "acpi_if.h"
  69 #include "cpufreq_if.h"
  70
  71 #define MSR_AMD_10H_11H_LIMIT   0xc0010061
  72 #define MSR_AMD_10H_11H_CONTROL 0xc0010062
  73 #define MSR_AMD_10H_11H_STATUS  0xc0010063
  74 #define MSR_AMD_10H_11H_CONFIG  0xc0010064
  75
  76 #define AMD_10H_11H_MAX_STATES  16
  77
  78 /* for MSR_AMD_10H_11H_LIMIT C001_0061 */
  79 #define AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)     (((msr) >> 4) & 0x7)
  80 #define AMD_10H_11H_GET_PSTATE_LIMIT(msr)       (((msr)) & 0x7)
  81 /* for MSR_AMD_10H_11H_CONFIG 10h:C001_0064:68 / 11h:C001_0064:6B */
  82 #define AMD_10H_11H_CUR_VID(msr)                (((msr) >> 9) & 0x7F)
  83 #define AMD_10H_11H_CUR_DID(msr)                (((msr) >> 6) & 0x07)
  84 #define AMD_10H_11H_CUR_FID(msr)                ((msr) & 0x3F)
  85
  86 #define AMD_17H_CUR_VID(msr)                    (((msr) >> 14) & 0xFF)
  87 #define AMD_17H_CUR_DID(msr)                    (((msr) >> 8) & 0x3F)
  88 #define AMD_17H_CUR_FID(msr)                    ((msr) & 0xFF)
  89
  90 #define HWPSTATE_DEBUG(dev, msg...)                     \
  91         do{                                             \
  92                 if(hwpstate_verbose)                    \
  93                         device_printf(dev, msg);        \
  94         }while(0)
  95
  96 struct hwpstate_setting {
  97         int     freq;           /* CPU clock in Mhz or 100ths of a percent. */
  98         int     volts;          /* Voltage in mV. */
  99         int     power;          /* Power consumed in mW. */
 100         int     lat;            /* Transition latency in us. */
 101         int     pstate_id;      /* P-State id */
 102 };
 103
 104 struct hwpstate_softc {
 105         device_t                dev;
 106         struct hwpstate_setting hwpstate_settings[AMD_10H_11H_MAX_STATES];
 107         int                     cfnum;
 108 };
 109
 110 static void     hwpstate_identify(driver_t *driver, device_t parent);
 111 static int      hwpstate_probe(device_t dev);
 112 static int      hwpstate_attach(device_t dev);
 113 static int      hwpstate_detach(device_t dev);
 114 static int      hwpstate_set(device_t dev, const struct cf_setting *cf);
 115 static int      hwpstate_get(device_t dev, struct cf_setting *cf);
 116 static int      hwpstate_settings(device_t dev, struct cf_setting *sets, int *count);
 117 static int      hwpstate_type(device_t dev, int *type);
 118 static int      hwpstate_shutdown(device_t dev);
 119 static int      hwpstate_features(driver_t *driver, u_int *features);
 120 static int      hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev);
 121 static int      hwpstate_get_info_from_msr(device_t dev);
 122 static int      hwpstate_goto_pstate(device_t dev, int pstate_id);
 123
 124 static int      hwpstate_verbose = 0;
 125 SYSCTL_INT(_debug, OID_AUTO, hwpstate_verbose, CTLFLAG_RWTUN,
 126        &hwpstate_verbose, 0, "Debug hwpstate");
 127
 128 static device_method_t hwpstate_methods[] = {
 129         /* Device interface */
 130         DEVMETHOD(device_identify,      hwpstate_identify),
 131         DEVMETHOD(device_probe,         hwpstate_probe),
 132         DEVMETHOD(device_attach,        hwpstate_attach),
 133         DEVMETHOD(device_detach,        hwpstate_detach),
 134         DEVMETHOD(device_shutdown,      hwpstate_shutdown),
 135
 136         /* cpufreq interface */
 137         DEVMETHOD(cpufreq_drv_set,      hwpstate_set),
 138         DEVMETHOD(cpufreq_drv_get,      hwpstate_get),
 139         DEVMETHOD(cpufreq_drv_settings, hwpstate_settings),
 140         DEVMETHOD(cpufreq_drv_type,     hwpstate_type),
 141
 142         /* ACPI interface */
 143         DEVMETHOD(acpi_get_features,    hwpstate_features),
 144
 145         {0, 0}
 146 };
 147
 148 static devclass_t hwpstate_devclass;
 149 static driver_t hwpstate_driver = {
 150         "hwpstate",
 151         hwpstate_methods,
 152         sizeof(struct hwpstate_softc),
 153 };
 154
 155 DRIVER_MODULE(hwpstate, cpu, hwpstate_driver, hwpstate_devclass, 0, 0);
 156
 157 /*
 158  * Go to Px-state on all cpus considering the limit.
 159  */
 160 static int
 161 hwpstate_goto_pstate(device_t dev, int pstate)
 162 {
 163         sbintime_t sbt;
 164         int i;
 165         uint64_t msr;
 166         int j;
 167         int limit;
 168         int id = pstate;
 169         int error;
 170
 171         /* get the current pstate limit */
 172         msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
 173         limit = AMD_10H_11H_GET_PSTATE_LIMIT(msr);
 174         if (limit > id)
 175                 id = limit;
 176
 177         /*
 178          * We are going to the same Px-state on all cpus.
 179          * Probably should take _PSD into account.
 180          */
 181         error = 0;
 182         CPU_FOREACH(i) {
 183                 /* Bind to each cpu. */
 184                 thread_lock(curthread);
 185                 sched_bind(curthread, i);
 186                 thread_unlock(curthread);
 187                 HWPSTATE_DEBUG(dev, "setting P%d-state on cpu%d\n",
 188                     id, PCPU_GET(cpuid));
 189                 /* Go To Px-state */
 190                 wrmsr(MSR_AMD_10H_11H_CONTROL, id);
 191         }
 192         CPU_FOREACH(i) {
 193                 /* Bind to each cpu. */
 194                 thread_lock(curthread);
 195                 sched_bind(curthread, i);
 196                 thread_unlock(curthread);
 197                 /* wait loop (100*100 usec is enough ?) */
 198                 for (j = 0; j < 100; j++){
 199                         /* get the result. not assure msr=id */
 200                         msr = rdmsr(MSR_AMD_10H_11H_STATUS);
 201                         if (msr == id)
 202                                 break;
 203                         sbt = SBT_1MS / 10;
 204                         tsleep_sbt(dev, PZERO, "pstate_goto", sbt,
 205                             sbt >> tc_precexp, 0);
 206                 }
 207                 HWPSTATE_DEBUG(dev, "result: P%d-state on cpu%d\n",
 208                     (int)msr, PCPU_GET(cpuid));
 209                 if (msr != id) {
 210                         HWPSTATE_DEBUG(dev, "error: loop is not enough.\n");
 211                         error = ENXIO;
 212                 }
 213         }
 214         thread_lock(curthread);
 215         sched_unbind(curthread);
 216         thread_unlock(curthread);
 217         return (error);
 218 }
 219
 220 static int
 221 hwpstate_set(device_t dev, const struct cf_setting *cf)
 222 {
 223         struct hwpstate_softc *sc;
 224         struct hwpstate_setting *set;
 225         int i;
 226
 227         if (cf == NULL)
 228                 return (EINVAL);
 229         sc = device_get_softc(dev);
 230         set = sc->hwpstate_settings;
 231         for (i = 0; i < sc->cfnum; i++)
 232                 if (CPUFREQ_CMP(cf->freq, set[i].freq))
 233                         break;
 234         if (i == sc->cfnum)
 235                 return (EINVAL);
 236
 237         return (hwpstate_goto_pstate(dev, set[i].pstate_id));
 238 }
 239
 240 static int
 241 hwpstate_get(device_t dev, struct cf_setting *cf)
 242 {
 243         struct hwpstate_softc *sc;
 244         struct hwpstate_setting set;
 245         uint64_t msr;
 246
 247         sc = device_get_softc(dev);
 248         if (cf == NULL)
 249                 return (EINVAL);
 250         msr = rdmsr(MSR_AMD_10H_11H_STATUS);
 251         if(msr >= sc->cfnum)
 252                 return (EINVAL);
 253         set = sc->hwpstate_settings[msr];
 254
 255         cf->freq = set.freq;
 256         cf->volts = set.volts;
 257         cf->power = set.power;
 258         cf->lat = set.lat;
 259         cf->dev = dev;
 260         return (0);
 261 }
 262
 263 static int
 264 hwpstate_settings(device_t dev, struct cf_setting *sets, int *count)
 265 {
 266         struct hwpstate_softc *sc;
 267         struct hwpstate_setting set;
 268         int i;
 269
 270         if (sets == NULL || count == NULL)
 271                 return (EINVAL);
 272         sc = device_get_softc(dev);
 273         if (*count < sc->cfnum)
 274                 return (E2BIG);
 275         for (i = 0; i < sc->cfnum; i++, sets++) {
 276                 set = sc->hwpstate_settings[i];
 277                 sets->freq = set.freq;
 278                 sets->volts = set.volts;
 279                 sets->power = set.power;
 280                 sets->lat = set.lat;
 281                 sets->dev = dev;
 282         }
 283         *count = sc->cfnum;
 284
 285         return (0);
 286 }
 287
 288 static int
 289 hwpstate_type(device_t dev, int *type)
 290 {
 291
 292         if (type == NULL)
 293                 return (EINVAL);
 294
 295         *type = CPUFREQ_TYPE_ABSOLUTE;
 296         return (0);
 297 }
 298
 299 static void
 300 hwpstate_identify(driver_t *driver, device_t parent)
 301 {
 302
 303         if (device_find_child(parent, "hwpstate", -1) != NULL)
 304                 return;
 305
 306         if (cpu_vendor_id != CPU_VENDOR_AMD || CPUID_TO_FAMILY(cpu_id) < 0x10)
 307                 return;
 308
 309         /*
 310          * Check if hardware pstate enable bit is set.
 311          */
 312         if ((amd_pminfo & AMDPM_HW_PSTATE) == 0) {
 313                 HWPSTATE_DEBUG(parent, "hwpstate enable bit is not set.\n");
 314                 return;
 315         }
 316
 317         if (resource_disabled("hwpstate", 0))
 318                 return;
 319
 320         if (BUS_ADD_CHILD(parent, 10, "hwpstate", -1) == NULL)
 321                 device_printf(parent, "hwpstate: add child failed\n");
 322 }
 323
 324 static int
 325 hwpstate_probe(device_t dev)
 326 {
 327         struct hwpstate_softc *sc;
 328         device_t perf_dev;
 329         uint64_t msr;
 330         int error, type;
 331
 332         /*
 333          * Only hwpstate0.
 334          * It goes well with acpi_throttle.
 335          */
 336         if (device_get_unit(dev) != 0)
 337                 return (ENXIO);
 338
 339         sc = device_get_softc(dev);
 340         sc->dev = dev;
 341
 342         /*
 343          * Check if acpi_perf has INFO only flag.
 344          */
 345         perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
 346         error = TRUE;
 347         if (perf_dev && device_is_attached(perf_dev)) {
 348                 error = CPUFREQ_DRV_TYPE(perf_dev, &type);
 349                 if (error == 0) {
 350                         if ((type & CPUFREQ_FLAG_INFO_ONLY) == 0) {
 351                                 /*
 352                                  * If acpi_perf doesn't have INFO_ONLY flag,
 353                                  * it will take care of pstate transitions.
 354                                  */
 355                                 HWPSTATE_DEBUG(dev, "acpi_perf will take care of pstate transitions.\n");
 356                                 return (ENXIO);
 357                         } else {
 358                                 /*
 359                                  * If acpi_perf has INFO_ONLY flag, (_PCT has FFixedHW)
 360                                  * we can get _PSS info from acpi_perf
 361                                  * without going into ACPI.
 362                                  */
 363                                 HWPSTATE_DEBUG(dev, "going to fetch info from acpi_perf\n");
 364                                 error = hwpstate_get_info_from_acpi_perf(dev, perf_dev);
 365                         }
 366                 }
 367         }
 368
 369         if (error == 0) {
 370                 /*
 371                  * Now we get _PSS info from acpi_perf without error.
 372                  * Let's check it.
 373                  */
 374                 msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
 375                 if (sc->cfnum != 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)) {
 376                         HWPSTATE_DEBUG(dev, "MSR (%jd) and ACPI _PSS (%d)"
 377                             " count mismatch\n", (intmax_t)msr, sc->cfnum);
 378                         error = TRUE;
 379                 }
 380         }
 381
 382         /*
 383          * If we cannot get info from acpi_perf,
 384          * Let's get info from MSRs.
 385          */
 386         if (error)
 387                 error = hwpstate_get_info_from_msr(dev);
 388         if (error)
 389                 return (error);
 390
 391         device_set_desc(dev, "Cool`n'Quiet 2.0");
 392         return (0);
 393 }
 394
 395 static int
 396 hwpstate_attach(device_t dev)
 397 {
 398
 399         return (cpufreq_register(dev));
 400 }
 401
 402 static int
 403 hwpstate_get_info_from_msr(device_t dev)
 404 {
 405         struct hwpstate_softc *sc;
 406         struct hwpstate_setting *hwpstate_set;
 407         uint64_t msr;
 408         int family, i, fid, did;
 409
 410         family = CPUID_TO_FAMILY(cpu_id);
 411         sc = device_get_softc(dev);
 412         /* Get pstate count */
 413         msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
 414         sc->cfnum = 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr);
 415         hwpstate_set = sc->hwpstate_settings;
 416         for (i = 0; i < sc->cfnum; i++) {
 417                 msr = rdmsr(MSR_AMD_10H_11H_CONFIG + i);
 418                 if ((msr & ((uint64_t)1 << 63)) == 0) {
 419                         HWPSTATE_DEBUG(dev, "msr is not valid.\n");
 420                         return (ENXIO);
 421                 }
 422                 did = AMD_10H_11H_CUR_DID(msr);
 423                 fid = AMD_10H_11H_CUR_FID(msr);
 424
 425                 /* Convert fid/did to frequency. */
 426                 switch(family) {
 427                 case 0x11:
 428                         hwpstate_set[i].freq = (100 * (fid + 0x08)) >> did;
 429                         break;
 430                 case 0x10:
 431                 case 0x12:
 432                 case 0x15:
 433                 case 0x16:
 434                         hwpstate_set[i].freq = (100 * (fid + 0x10)) >> did;
 435                         break;
 436                 case 0x17:
 437                         did = AMD_17H_CUR_DID(msr);
 438                         if (did == 0) {
 439                                 HWPSTATE_DEBUG(dev, "unexpected did: 0\n");
 440                                 did = 1;
 441                         }
 442                         fid = AMD_17H_CUR_FID(msr);
 443                         hwpstate_set[i].freq = (200 * fid) / did;
 444                         break;
 445                 default:
 446                         HWPSTATE_DEBUG(dev, "get_info_from_msr: AMD family"
 447                             " 0x%02x CPUs are not supported yet\n", family);
 448                         return (ENXIO);
 449                 }
 450                 hwpstate_set[i].pstate_id = i;
 451                 /* There was volts calculation, but deleted it. */
 452                 hwpstate_set[i].volts = CPUFREQ_VAL_UNKNOWN;
 453                 hwpstate_set[i].power = CPUFREQ_VAL_UNKNOWN;
 454                 hwpstate_set[i].lat = CPUFREQ_VAL_UNKNOWN;
 455         }
 456         return (0);
 457 }
 458
 459 static int
 460 hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev)
 461 {
 462         struct hwpstate_softc *sc;
 463         struct cf_setting *perf_set;
 464         struct hwpstate_setting *hwpstate_set;
 465         int count, error, i;
 466
 467         perf_set = malloc(MAX_SETTINGS * sizeof(*perf_set), M_TEMP, M_NOWAIT);
 468         if (perf_set == NULL) {
 469                 HWPSTATE_DEBUG(dev, "nomem\n");
 470                 return (ENOMEM);
 471         }
 472         /*
 473          * Fetch settings from acpi_perf.
 474          * Now it is attached, and has info only flag.
 475          */
 476         count = MAX_SETTINGS;
 477         error = CPUFREQ_DRV_SETTINGS(perf_dev, perf_set, &count);
 478         if (error) {
 479                 HWPSTATE_DEBUG(dev, "error: CPUFREQ_DRV_SETTINGS.\n");
 480                 goto out;
 481         }
 482         sc = device_get_softc(dev);
 483         sc->cfnum = count;
 484         hwpstate_set = sc->hwpstate_settings;
 485         for (i = 0; i < count; i++) {
 486                 if (i == perf_set[i].spec[0]) {
 487                         hwpstate_set[i].pstate_id = i;
 488                         hwpstate_set[i].freq = perf_set[i].freq;
 489                         hwpstate_set[i].volts = perf_set[i].volts;
 490                         hwpstate_set[i].power = perf_set[i].power;
 491                         hwpstate_set[i].lat = perf_set[i].lat;
 492                 } else {
 493                         HWPSTATE_DEBUG(dev, "ACPI _PSS object mismatch.\n");
 494                         error = ENXIO;
 495                         goto out;
 496                 }
 497         }
 498 out:
 499         if (perf_set)
 500                 free(perf_set, M_TEMP);
 501         return (error);
 502 }
 503
 504 static int
 505 hwpstate_detach(device_t dev)
 506 {
 507
 508         hwpstate_goto_pstate(dev, 0);
 509         return (cpufreq_unregister(dev));
 510 }
 511
 512 static int
 513 hwpstate_shutdown(device_t dev)
 514 {
 515
 516         /* hwpstate_goto_pstate(dev, 0); */
 517         return (0);
 518 }
 519
 520 static int
 521 hwpstate_features(driver_t *driver, u_int *features)
 522 {
 523
 524         /* Notify the ACPI CPU that we support direct access to MSRs */
 525         *features = ACPI_CAP_PERF_MSRS;
 526         return (0);
 527 }