2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2005 Nate Lawson
5 * Copyright (c) 2004 Colin Percival
6 * Copyright (c) 2004-2005 Bruno Durcot
7 * Copyright (c) 2004 FUKUDA Nobuhiko
8 * Copyright (c) 2009 Michael Reifenberger
9 * Copyright (c) 2009 Norikatsu Shigemura
10 * Copyright (c) 2008-2009 Gen Otsuji
12 * This code is depending on kern_cpu.c, est.c, powernow.c, p4tcc.c, smist.c
13 * in various parts. The authors of these files are Nate Lawson,
14 * Colin Percival, Bruno Durcot, and FUKUDA Nobuhiko.
15 * This code contains patches by Michael Reifenberger and Norikatsu Shigemura.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted providing that the following conditions
21 * 1. Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
27 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR
28 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
29 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
31 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
42 * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 10h Processors
43 * 31116 Rev 3.20 February 04, 2009
44 * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 11h Processors
45 * 41256 Rev 3.00 - July 07, 2008
48 #include <sys/cdefs.h>
49 __FBSDID("$FreeBSD$");
51 #include <sys/param.h>
54 #include <sys/kernel.h>
55 #include <sys/module.h>
56 #include <sys/malloc.h>
60 #include <sys/sched.h>
62 #include <machine/md_var.h>
63 #include <machine/cputypes.h>
64 #include <machine/specialreg.h>
66 #include <contrib/dev/acpica/include/acpi.h>
68 #include <dev/acpica/acpivar.h>
71 #include "cpufreq_if.h"
73 #define MSR_AMD_10H_11H_LIMIT 0xc0010061
74 #define MSR_AMD_10H_11H_CONTROL 0xc0010062
75 #define MSR_AMD_10H_11H_STATUS 0xc0010063
76 #define MSR_AMD_10H_11H_CONFIG 0xc0010064
78 #define AMD_10H_11H_MAX_STATES 16
80 /* for MSR_AMD_10H_11H_LIMIT C001_0061 */
81 #define AMD_10H_11H_GET_PSTATE_MAX_VAL(msr) (((msr) >> 4) & 0x7)
82 #define AMD_10H_11H_GET_PSTATE_LIMIT(msr) (((msr)) & 0x7)
83 /* for MSR_AMD_10H_11H_CONFIG 10h:C001_0064:68 / 11h:C001_0064:6B */
84 #define AMD_10H_11H_CUR_VID(msr) (((msr) >> 9) & 0x7F)
85 #define AMD_10H_11H_CUR_DID(msr) (((msr) >> 6) & 0x07)
86 #define AMD_10H_11H_CUR_FID(msr) ((msr) & 0x3F)
88 #define AMD_17H_CUR_VID(msr) (((msr) >> 14) & 0xFF)
89 #define AMD_17H_CUR_DID(msr) (((msr) >> 8) & 0x3F)
90 #define AMD_17H_CUR_FID(msr) ((msr) & 0xFF)
92 #define HWPSTATE_DEBUG(dev, msg...) \
94 if (hwpstate_verbose) \
95 device_printf(dev, msg); \
98 struct hwpstate_setting {
99 int freq; /* CPU clock in Mhz or 100ths of a percent. */
100 int volts; /* Voltage in mV. */
101 int power; /* Power consumed in mW. */
102 int lat; /* Transition latency in us. */
103 int pstate_id; /* P-State id */
106 struct hwpstate_softc {
108 struct hwpstate_setting hwpstate_settings[AMD_10H_11H_MAX_STATES];
112 static void hwpstate_identify(driver_t *driver, device_t parent);
113 static int hwpstate_probe(device_t dev);
114 static int hwpstate_attach(device_t dev);
115 static int hwpstate_detach(device_t dev);
116 static int hwpstate_set(device_t dev, const struct cf_setting *cf);
117 static int hwpstate_get(device_t dev, struct cf_setting *cf);
118 static int hwpstate_settings(device_t dev, struct cf_setting *sets, int *count);
119 static int hwpstate_type(device_t dev, int *type);
120 static int hwpstate_shutdown(device_t dev);
121 static int hwpstate_features(driver_t *driver, u_int *features);
122 static int hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev);
123 static int hwpstate_get_info_from_msr(device_t dev);
124 static int hwpstate_goto_pstate(device_t dev, int pstate_id);
126 static int hwpstate_verbose;
127 SYSCTL_INT(_debug, OID_AUTO, hwpstate_verbose, CTLFLAG_RWTUN,
128 &hwpstate_verbose, 0, "Debug hwpstate");
130 static int hwpstate_verify;
131 SYSCTL_INT(_debug, OID_AUTO, hwpstate_verify, CTLFLAG_RWTUN,
132 &hwpstate_verify, 0, "Verify P-state after setting");
134 static device_method_t hwpstate_methods[] = {
135 /* Device interface */
136 DEVMETHOD(device_identify, hwpstate_identify),
137 DEVMETHOD(device_probe, hwpstate_probe),
138 DEVMETHOD(device_attach, hwpstate_attach),
139 DEVMETHOD(device_detach, hwpstate_detach),
140 DEVMETHOD(device_shutdown, hwpstate_shutdown),
142 /* cpufreq interface */
143 DEVMETHOD(cpufreq_drv_set, hwpstate_set),
144 DEVMETHOD(cpufreq_drv_get, hwpstate_get),
145 DEVMETHOD(cpufreq_drv_settings, hwpstate_settings),
146 DEVMETHOD(cpufreq_drv_type, hwpstate_type),
149 DEVMETHOD(acpi_get_features, hwpstate_features),
154 static devclass_t hwpstate_devclass;
155 static driver_t hwpstate_driver = {
158 sizeof(struct hwpstate_softc),
161 DRIVER_MODULE(hwpstate, cpu, hwpstate_driver, hwpstate_devclass, 0, 0);
164 * Go to Px-state on all cpus considering the limit.
167 hwpstate_goto_pstate(device_t dev, int id)
171 int cpu, i, j, limit;
173 /* get the current pstate limit */
174 msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
175 limit = AMD_10H_11H_GET_PSTATE_LIMIT(msr);
180 HWPSTATE_DEBUG(dev, "setting P%d-state on cpu%d\n", id, cpu);
182 wrmsr(MSR_AMD_10H_11H_CONTROL, id);
185 * We are going to the same Px-state on all cpus.
186 * Probably should take _PSD into account.
192 /* Bind to each cpu. */
193 thread_lock(curthread);
194 sched_bind(curthread, i);
195 thread_unlock(curthread);
196 HWPSTATE_DEBUG(dev, "setting P%d-state on cpu%d\n", id, i);
198 wrmsr(MSR_AMD_10H_11H_CONTROL, id);
202 * Verify whether each core is in the requested P-state.
204 if (hwpstate_verify) {
206 thread_lock(curthread);
207 sched_bind(curthread, i);
208 thread_unlock(curthread);
209 /* wait loop (100*100 usec is enough ?) */
210 for (j = 0; j < 100; j++) {
211 /* get the result. not assure msr=id */
212 msr = rdmsr(MSR_AMD_10H_11H_STATUS);
216 tsleep_sbt(dev, PZERO, "pstate_goto", sbt,
217 sbt >> tc_precexp, 0);
219 HWPSTATE_DEBUG(dev, "result: P%d-state on cpu%d\n",
223 "error: loop is not enough.\n");
233 hwpstate_set(device_t dev, const struct cf_setting *cf)
235 struct hwpstate_softc *sc;
236 struct hwpstate_setting *set;
241 sc = device_get_softc(dev);
242 set = sc->hwpstate_settings;
243 for (i = 0; i < sc->cfnum; i++)
244 if (CPUFREQ_CMP(cf->freq, set[i].freq))
249 return (hwpstate_goto_pstate(dev, set[i].pstate_id));
253 hwpstate_get(device_t dev, struct cf_setting *cf)
255 struct hwpstate_softc *sc;
256 struct hwpstate_setting set;
259 sc = device_get_softc(dev);
262 msr = rdmsr(MSR_AMD_10H_11H_STATUS);
263 if (msr >= sc->cfnum)
265 set = sc->hwpstate_settings[msr];
268 cf->volts = set.volts;
269 cf->power = set.power;
276 hwpstate_settings(device_t dev, struct cf_setting *sets, int *count)
278 struct hwpstate_softc *sc;
279 struct hwpstate_setting set;
282 if (sets == NULL || count == NULL)
284 sc = device_get_softc(dev);
285 if (*count < sc->cfnum)
287 for (i = 0; i < sc->cfnum; i++, sets++) {
288 set = sc->hwpstate_settings[i];
289 sets->freq = set.freq;
290 sets->volts = set.volts;
291 sets->power = set.power;
301 hwpstate_type(device_t dev, int *type)
307 *type = CPUFREQ_TYPE_ABSOLUTE;
312 hwpstate_identify(driver_t *driver, device_t parent)
315 if (device_find_child(parent, "hwpstate", -1) != NULL)
318 if (cpu_vendor_id != CPU_VENDOR_AMD || CPUID_TO_FAMILY(cpu_id) < 0x10)
322 * Check if hardware pstate enable bit is set.
324 if ((amd_pminfo & AMDPM_HW_PSTATE) == 0) {
325 HWPSTATE_DEBUG(parent, "hwpstate enable bit is not set.\n");
329 if (resource_disabled("hwpstate", 0))
332 if (BUS_ADD_CHILD(parent, 10, "hwpstate", -1) == NULL)
333 device_printf(parent, "hwpstate: add child failed\n");
337 hwpstate_probe(device_t dev)
339 struct hwpstate_softc *sc;
346 * It goes well with acpi_throttle.
348 if (device_get_unit(dev) != 0)
351 sc = device_get_softc(dev);
355 * Check if acpi_perf has INFO only flag.
357 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
359 if (perf_dev && device_is_attached(perf_dev)) {
360 error = CPUFREQ_DRV_TYPE(perf_dev, &type);
362 if ((type & CPUFREQ_FLAG_INFO_ONLY) == 0) {
364 * If acpi_perf doesn't have INFO_ONLY flag,
365 * it will take care of pstate transitions.
367 HWPSTATE_DEBUG(dev, "acpi_perf will take care of pstate transitions.\n");
371 * If acpi_perf has INFO_ONLY flag, (_PCT has FFixedHW)
372 * we can get _PSS info from acpi_perf
373 * without going into ACPI.
375 HWPSTATE_DEBUG(dev, "going to fetch info from acpi_perf\n");
376 error = hwpstate_get_info_from_acpi_perf(dev, perf_dev);
383 * Now we get _PSS info from acpi_perf without error.
386 msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
387 if (sc->cfnum != 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)) {
388 HWPSTATE_DEBUG(dev, "MSR (%jd) and ACPI _PSS (%d)"
389 " count mismatch\n", (intmax_t)msr, sc->cfnum);
395 * If we cannot get info from acpi_perf,
396 * Let's get info from MSRs.
399 error = hwpstate_get_info_from_msr(dev);
403 device_set_desc(dev, "Cool`n'Quiet 2.0");
408 hwpstate_attach(device_t dev)
411 return (cpufreq_register(dev));
415 hwpstate_get_info_from_msr(device_t dev)
417 struct hwpstate_softc *sc;
418 struct hwpstate_setting *hwpstate_set;
420 int family, i, fid, did;
422 family = CPUID_TO_FAMILY(cpu_id);
423 sc = device_get_softc(dev);
424 /* Get pstate count */
425 msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
426 sc->cfnum = 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr);
427 hwpstate_set = sc->hwpstate_settings;
428 for (i = 0; i < sc->cfnum; i++) {
429 msr = rdmsr(MSR_AMD_10H_11H_CONFIG + i);
430 if ((msr & ((uint64_t)1 << 63)) == 0) {
431 HWPSTATE_DEBUG(dev, "msr is not valid.\n");
434 did = AMD_10H_11H_CUR_DID(msr);
435 fid = AMD_10H_11H_CUR_FID(msr);
437 /* Convert fid/did to frequency. */
440 hwpstate_set[i].freq = (100 * (fid + 0x08)) >> did;
446 hwpstate_set[i].freq = (100 * (fid + 0x10)) >> did;
449 did = AMD_17H_CUR_DID(msr);
451 HWPSTATE_DEBUG(dev, "unexpected did: 0\n");
454 fid = AMD_17H_CUR_FID(msr);
455 hwpstate_set[i].freq = (200 * fid) / did;
458 HWPSTATE_DEBUG(dev, "get_info_from_msr: AMD family"
459 " 0x%02x CPUs are not supported yet\n", family);
462 hwpstate_set[i].pstate_id = i;
463 /* There was volts calculation, but deleted it. */
464 hwpstate_set[i].volts = CPUFREQ_VAL_UNKNOWN;
465 hwpstate_set[i].power = CPUFREQ_VAL_UNKNOWN;
466 hwpstate_set[i].lat = CPUFREQ_VAL_UNKNOWN;
472 hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev)
474 struct hwpstate_softc *sc;
475 struct cf_setting *perf_set;
476 struct hwpstate_setting *hwpstate_set;
479 perf_set = malloc(MAX_SETTINGS * sizeof(*perf_set), M_TEMP, M_NOWAIT);
480 if (perf_set == NULL) {
481 HWPSTATE_DEBUG(dev, "nomem\n");
485 * Fetch settings from acpi_perf.
486 * Now it is attached, and has info only flag.
488 count = MAX_SETTINGS;
489 error = CPUFREQ_DRV_SETTINGS(perf_dev, perf_set, &count);
491 HWPSTATE_DEBUG(dev, "error: CPUFREQ_DRV_SETTINGS.\n");
494 sc = device_get_softc(dev);
496 hwpstate_set = sc->hwpstate_settings;
497 for (i = 0; i < count; i++) {
498 if (i == perf_set[i].spec[0]) {
499 hwpstate_set[i].pstate_id = i;
500 hwpstate_set[i].freq = perf_set[i].freq;
501 hwpstate_set[i].volts = perf_set[i].volts;
502 hwpstate_set[i].power = perf_set[i].power;
503 hwpstate_set[i].lat = perf_set[i].lat;
505 HWPSTATE_DEBUG(dev, "ACPI _PSS object mismatch.\n");
512 free(perf_set, M_TEMP);
517 hwpstate_detach(device_t dev)
520 hwpstate_goto_pstate(dev, 0);
521 return (cpufreq_unregister(dev));
525 hwpstate_shutdown(device_t dev)
528 /* hwpstate_goto_pstate(dev, 0); */
533 hwpstate_features(driver_t *driver, u_int *features)
536 /* Notify the ACPI CPU that we support direct access to MSRs */
537 *features = ACPI_CAP_PERF_MSRS;