sys/x86/cpufreq/hwpstate.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2005 Nate Lawson
   5  * Copyright (c) 2004 Colin Percival
   6  * Copyright (c) 2004-2005 Bruno Durcot
   7  * Copyright (c) 2004 FUKUDA Nobuhiko
   8  * Copyright (c) 2009 Michael Reifenberger
   9  * Copyright (c) 2009 Norikatsu Shigemura
  10  * Copyright (c) 2008-2009 Gen Otsuji
  11  *
  12  * This code is depending on kern_cpu.c, est.c, powernow.c, p4tcc.c, smist.c
  13  * in various parts. The authors of these files are Nate Lawson,
  14  * Colin Percival, Bruno Durcot, and FUKUDA Nobuhiko.
  15  * This code contains patches by Michael Reifenberger and Norikatsu Shigemura.
  16  * Thank you.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted providing that the following conditions
  20  * are met:
  21  * 1. Redistributions of source code must retain the above copyright
  22  *    notice, this list of conditions and the following disclaimer.
  23  * 2. Redistributions in binary form must reproduce the above copyright
  24  *    notice, this list of conditions and the following disclaimer in the
  25  *    documentation and/or other materials provided with the distribution.
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR
  28  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  29  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  30  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  31  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGE.
  38  */
  39
  40 /*
  41  * For more info:
  42  * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 10h Processors
  43  * 31116 Rev 3.20  February 04, 2009
  44  * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 11h Processors
  45  * 41256 Rev 3.00 - July 07, 2008
  46  */
  47
  48 #include <sys/cdefs.h>
  49 __FBSDID("$FreeBSD$");
  50
  51 #include <sys/param.h>
  52 #include <sys/bus.h>
  53 #include <sys/cpu.h>
  54 #include <sys/kernel.h>
  55 #include <sys/module.h>
  56 #include <sys/malloc.h>
  57 #include <sys/proc.h>
  58 #include <sys/pcpu.h>
  59 #include <sys/smp.h>
  60 #include <sys/sched.h>
  61
  62 #include <machine/md_var.h>
  63 #include <machine/cputypes.h>
  64 #include <machine/specialreg.h>
  65
  66 #include <contrib/dev/acpica/include/acpi.h>
  67
  68 #include <dev/acpica/acpivar.h>
  69
  70 #include "acpi_if.h"
  71 #include "cpufreq_if.h"
  72
  73 #define MSR_AMD_10H_11H_LIMIT   0xc0010061
  74 #define MSR_AMD_10H_11H_CONTROL 0xc0010062
  75 #define MSR_AMD_10H_11H_STATUS  0xc0010063
  76 #define MSR_AMD_10H_11H_CONFIG  0xc0010064
  77
  78 #define AMD_10H_11H_MAX_STATES  16
  79
  80 /* for MSR_AMD_10H_11H_LIMIT C001_0061 */
  81 #define AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)     (((msr) >> 4) & 0x7)
  82 #define AMD_10H_11H_GET_PSTATE_LIMIT(msr)       (((msr)) & 0x7)
  83 /* for MSR_AMD_10H_11H_CONFIG 10h:C001_0064:68 / 11h:C001_0064:6B */
  84 #define AMD_10H_11H_CUR_VID(msr)                (((msr) >> 9) & 0x7F)
  85 #define AMD_10H_11H_CUR_DID(msr)                (((msr) >> 6) & 0x07)
  86 #define AMD_10H_11H_CUR_FID(msr)                ((msr) & 0x3F)
  87
  88 #define AMD_17H_CUR_VID(msr)                    (((msr) >> 14) & 0xFF)
  89 #define AMD_17H_CUR_DID(msr)                    (((msr) >> 8) & 0x3F)
  90 #define AMD_17H_CUR_FID(msr)                    ((msr) & 0xFF)
  91
  92 #define HWPSTATE_DEBUG(dev, msg...)                     \
  93         do {                                            \
  94                 if (hwpstate_verbose)                   \
  95                         device_printf(dev, msg);        \
  96         } while (0)
  97
  98 struct hwpstate_setting {
  99         int     freq;           /* CPU clock in Mhz or 100ths of a percent. */
 100         int     volts;          /* Voltage in mV. */
 101         int     power;          /* Power consumed in mW. */
 102         int     lat;            /* Transition latency in us. */
 103         int     pstate_id;      /* P-State id */
 104 };
 105
 106 struct hwpstate_softc {
 107         device_t                dev;
 108         struct hwpstate_setting hwpstate_settings[AMD_10H_11H_MAX_STATES];
 109         int                     cfnum;
 110 };
 111
 112 static void     hwpstate_identify(driver_t *driver, device_t parent);
 113 static int      hwpstate_probe(device_t dev);
 114 static int      hwpstate_attach(device_t dev);
 115 static int      hwpstate_detach(device_t dev);
 116 static int      hwpstate_set(device_t dev, const struct cf_setting *cf);
 117 static int      hwpstate_get(device_t dev, struct cf_setting *cf);
 118 static int      hwpstate_settings(device_t dev, struct cf_setting *sets, int *count);
 119 static int      hwpstate_type(device_t dev, int *type);
 120 static int      hwpstate_shutdown(device_t dev);
 121 static int      hwpstate_features(driver_t *driver, u_int *features);
 122 static int      hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev);
 123 static int      hwpstate_get_info_from_msr(device_t dev);
 124 static int      hwpstate_goto_pstate(device_t dev, int pstate_id);
 125
 126 static int      hwpstate_verbose;
 127 SYSCTL_INT(_debug, OID_AUTO, hwpstate_verbose, CTLFLAG_RWTUN,
 128     &hwpstate_verbose, 0, "Debug hwpstate");
 129
 130 static int      hwpstate_verify;
 131 SYSCTL_INT(_debug, OID_AUTO, hwpstate_verify, CTLFLAG_RWTUN,
 132     &hwpstate_verify, 0, "Verify P-state after setting");
 133
 134 static device_method_t hwpstate_methods[] = {
 135         /* Device interface */
 136         DEVMETHOD(device_identify,      hwpstate_identify),
 137         DEVMETHOD(device_probe,         hwpstate_probe),
 138         DEVMETHOD(device_attach,        hwpstate_attach),
 139         DEVMETHOD(device_detach,        hwpstate_detach),
 140         DEVMETHOD(device_shutdown,      hwpstate_shutdown),
 141
 142         /* cpufreq interface */
 143         DEVMETHOD(cpufreq_drv_set,      hwpstate_set),
 144         DEVMETHOD(cpufreq_drv_get,      hwpstate_get),
 145         DEVMETHOD(cpufreq_drv_settings, hwpstate_settings),
 146         DEVMETHOD(cpufreq_drv_type,     hwpstate_type),
 147
 148         /* ACPI interface */
 149         DEVMETHOD(acpi_get_features,    hwpstate_features),
 150
 151         {0, 0}
 152 };
 153
 154 static devclass_t hwpstate_devclass;
 155 static driver_t hwpstate_driver = {
 156         "hwpstate",
 157         hwpstate_methods,
 158         sizeof(struct hwpstate_softc),
 159 };
 160
 161 DRIVER_MODULE(hwpstate, cpu, hwpstate_driver, hwpstate_devclass, 0, 0);
 162
 163 /*
 164  * Go to Px-state on all cpus considering the limit.
 165  */
 166 static int
 167 hwpstate_goto_pstate(device_t dev, int id)
 168 {
 169         sbintime_t sbt;
 170         uint64_t msr;
 171         int cpu, i, j, limit;
 172
 173         /* get the current pstate limit */
 174         msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
 175         limit = AMD_10H_11H_GET_PSTATE_LIMIT(msr);
 176         if (limit > id)
 177                 id = limit;
 178
 179         cpu = curcpu;
 180         HWPSTATE_DEBUG(dev, "setting P%d-state on cpu%d\n", id, cpu);
 181         /* Go To Px-state */
 182         wrmsr(MSR_AMD_10H_11H_CONTROL, id);
 183
 184         /*
 185          * We are going to the same Px-state on all cpus.
 186          * Probably should take _PSD into account.
 187          */
 188         CPU_FOREACH(i) {
 189                 if (i == cpu)
 190                         continue;
 191
 192                 /* Bind to each cpu. */
 193                 thread_lock(curthread);
 194                 sched_bind(curthread, i);
 195                 thread_unlock(curthread);
 196                 HWPSTATE_DEBUG(dev, "setting P%d-state on cpu%d\n", id, i);
 197                 /* Go To Px-state */
 198                 wrmsr(MSR_AMD_10H_11H_CONTROL, id);
 199         }
 200
 201         /*
 202          * Verify whether each core is in the requested P-state.
 203          */
 204         if (hwpstate_verify) {
 205                 CPU_FOREACH(i) {
 206                         thread_lock(curthread);
 207                         sched_bind(curthread, i);
 208                         thread_unlock(curthread);
 209                         /* wait loop (100*100 usec is enough ?) */
 210                         for (j = 0; j < 100; j++) {
 211                                 /* get the result. not assure msr=id */
 212                                 msr = rdmsr(MSR_AMD_10H_11H_STATUS);
 213                                 if (msr == id)
 214                                         break;
 215                                 sbt = SBT_1MS / 10;
 216                                 tsleep_sbt(dev, PZERO, "pstate_goto", sbt,
 217                                     sbt >> tc_precexp, 0);
 218                         }
 219                         HWPSTATE_DEBUG(dev, "result: P%d-state on cpu%d\n",
 220                             (int)msr, i);
 221                         if (msr != id) {
 222                                 HWPSTATE_DEBUG(dev,
 223                                     "error: loop is not enough.\n");
 224                                 return (ENXIO);
 225                         }
 226                 }
 227         }
 228
 229         return (0);
 230 }
 231
 232 static int
 233 hwpstate_set(device_t dev, const struct cf_setting *cf)
 234 {
 235         struct hwpstate_softc *sc;
 236         struct hwpstate_setting *set;
 237         int i;
 238
 239         if (cf == NULL)
 240                 return (EINVAL);
 241         sc = device_get_softc(dev);
 242         set = sc->hwpstate_settings;
 243         for (i = 0; i < sc->cfnum; i++)
 244                 if (CPUFREQ_CMP(cf->freq, set[i].freq))
 245                         break;
 246         if (i == sc->cfnum)
 247                 return (EINVAL);
 248
 249         return (hwpstate_goto_pstate(dev, set[i].pstate_id));
 250 }
 251
 252 static int
 253 hwpstate_get(device_t dev, struct cf_setting *cf)
 254 {
 255         struct hwpstate_softc *sc;
 256         struct hwpstate_setting set;
 257         uint64_t msr;
 258
 259         sc = device_get_softc(dev);
 260         if (cf == NULL)
 261                 return (EINVAL);
 262         msr = rdmsr(MSR_AMD_10H_11H_STATUS);
 263         if (msr >= sc->cfnum)
 264                 return (EINVAL);
 265         set = sc->hwpstate_settings[msr];
 266
 267         cf->freq = set.freq;
 268         cf->volts = set.volts;
 269         cf->power = set.power;
 270         cf->lat = set.lat;
 271         cf->dev = dev;
 272         return (0);
 273 }
 274
 275 static int
 276 hwpstate_settings(device_t dev, struct cf_setting *sets, int *count)
 277 {
 278         struct hwpstate_softc *sc;
 279         struct hwpstate_setting set;
 280         int i;
 281
 282         if (sets == NULL || count == NULL)
 283                 return (EINVAL);
 284         sc = device_get_softc(dev);
 285         if (*count < sc->cfnum)
 286                 return (E2BIG);
 287         for (i = 0; i < sc->cfnum; i++, sets++) {
 288                 set = sc->hwpstate_settings[i];
 289                 sets->freq = set.freq;
 290                 sets->volts = set.volts;
 291                 sets->power = set.power;
 292                 sets->lat = set.lat;
 293                 sets->dev = dev;
 294         }
 295         *count = sc->cfnum;
 296
 297         return (0);
 298 }
 299
 300 static int
 301 hwpstate_type(device_t dev, int *type)
 302 {
 303
 304         if (type == NULL)
 305                 return (EINVAL);
 306
 307         *type = CPUFREQ_TYPE_ABSOLUTE;
 308         return (0);
 309 }
 310
 311 static void
 312 hwpstate_identify(driver_t *driver, device_t parent)
 313 {
 314
 315         if (device_find_child(parent, "hwpstate", -1) != NULL)
 316                 return;
 317
 318         if (cpu_vendor_id != CPU_VENDOR_AMD || CPUID_TO_FAMILY(cpu_id) < 0x10)
 319                 return;
 320
 321         /*
 322          * Check if hardware pstate enable bit is set.
 323          */
 324         if ((amd_pminfo & AMDPM_HW_PSTATE) == 0) {
 325                 HWPSTATE_DEBUG(parent, "hwpstate enable bit is not set.\n");
 326                 return;
 327         }
 328
 329         if (resource_disabled("hwpstate", 0))
 330                 return;
 331
 332         if (BUS_ADD_CHILD(parent, 10, "hwpstate", -1) == NULL)
 333                 device_printf(parent, "hwpstate: add child failed\n");
 334 }
 335
 336 static int
 337 hwpstate_probe(device_t dev)
 338 {
 339         struct hwpstate_softc *sc;
 340         device_t perf_dev;
 341         uint64_t msr;
 342         int error, type;
 343
 344         /*
 345          * Only hwpstate0.
 346          * It goes well with acpi_throttle.
 347          */
 348         if (device_get_unit(dev) != 0)
 349                 return (ENXIO);
 350
 351         sc = device_get_softc(dev);
 352         sc->dev = dev;
 353
 354         /*
 355          * Check if acpi_perf has INFO only flag.
 356          */
 357         perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
 358         error = TRUE;
 359         if (perf_dev && device_is_attached(perf_dev)) {
 360                 error = CPUFREQ_DRV_TYPE(perf_dev, &type);
 361                 if (error == 0) {
 362                         if ((type & CPUFREQ_FLAG_INFO_ONLY) == 0) {
 363                                 /*
 364                                  * If acpi_perf doesn't have INFO_ONLY flag,
 365                                  * it will take care of pstate transitions.
 366                                  */
 367                                 HWPSTATE_DEBUG(dev, "acpi_perf will take care of pstate transitions.\n");
 368                                 return (ENXIO);
 369                         } else {
 370                                 /*
 371                                  * If acpi_perf has INFO_ONLY flag, (_PCT has FFixedHW)
 372                                  * we can get _PSS info from acpi_perf
 373                                  * without going into ACPI.
 374                                  */
 375                                 HWPSTATE_DEBUG(dev, "going to fetch info from acpi_perf\n");
 376                                 error = hwpstate_get_info_from_acpi_perf(dev, perf_dev);
 377                         }
 378                 }
 379         }
 380
 381         if (error == 0) {
 382                 /*
 383                  * Now we get _PSS info from acpi_perf without error.
 384                  * Let's check it.
 385                  */
 386                 msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
 387                 if (sc->cfnum != 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)) {
 388                         HWPSTATE_DEBUG(dev, "MSR (%jd) and ACPI _PSS (%d)"
 389                             " count mismatch\n", (intmax_t)msr, sc->cfnum);
 390                         error = TRUE;
 391                 }
 392         }
 393
 394         /*
 395          * If we cannot get info from acpi_perf,
 396          * Let's get info from MSRs.
 397          */
 398         if (error)
 399                 error = hwpstate_get_info_from_msr(dev);
 400         if (error)
 401                 return (error);
 402
 403         device_set_desc(dev, "Cool`n'Quiet 2.0");
 404         return (0);
 405 }
 406
 407 static int
 408 hwpstate_attach(device_t dev)
 409 {
 410
 411         return (cpufreq_register(dev));
 412 }
 413
 414 static int
 415 hwpstate_get_info_from_msr(device_t dev)
 416 {
 417         struct hwpstate_softc *sc;
 418         struct hwpstate_setting *hwpstate_set;
 419         uint64_t msr;
 420         int family, i, fid, did;
 421
 422         family = CPUID_TO_FAMILY(cpu_id);
 423         sc = device_get_softc(dev);
 424         /* Get pstate count */
 425         msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
 426         sc->cfnum = 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr);
 427         hwpstate_set = sc->hwpstate_settings;
 428         for (i = 0; i < sc->cfnum; i++) {
 429                 msr = rdmsr(MSR_AMD_10H_11H_CONFIG + i);
 430                 if ((msr & ((uint64_t)1 << 63)) == 0) {
 431                         HWPSTATE_DEBUG(dev, "msr is not valid.\n");
 432                         return (ENXIO);
 433                 }
 434                 did = AMD_10H_11H_CUR_DID(msr);
 435                 fid = AMD_10H_11H_CUR_FID(msr);
 436
 437                 /* Convert fid/did to frequency. */
 438                 switch (family) {
 439                 case 0x11:
 440                         hwpstate_set[i].freq = (100 * (fid + 0x08)) >> did;
 441                         break;
 442                 case 0x10:
 443                 case 0x12:
 444                 case 0x15:
 445                 case 0x16:
 446                         hwpstate_set[i].freq = (100 * (fid + 0x10)) >> did;
 447                         break;
 448                 case 0x17:
 449                         did = AMD_17H_CUR_DID(msr);
 450                         if (did == 0) {
 451                                 HWPSTATE_DEBUG(dev, "unexpected did: 0\n");
 452                                 did = 1;
 453                         }
 454                         fid = AMD_17H_CUR_FID(msr);
 455                         hwpstate_set[i].freq = (200 * fid) / did;
 456                         break;
 457                 default:
 458                         HWPSTATE_DEBUG(dev, "get_info_from_msr: AMD family"
 459                             " 0x%02x CPUs are not supported yet\n", family);
 460                         return (ENXIO);
 461                 }
 462                 hwpstate_set[i].pstate_id = i;
 463                 /* There was volts calculation, but deleted it. */
 464                 hwpstate_set[i].volts = CPUFREQ_VAL_UNKNOWN;
 465                 hwpstate_set[i].power = CPUFREQ_VAL_UNKNOWN;
 466                 hwpstate_set[i].lat = CPUFREQ_VAL_UNKNOWN;
 467         }
 468         return (0);
 469 }
 470
 471 static int
 472 hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev)
 473 {
 474         struct hwpstate_softc *sc;
 475         struct cf_setting *perf_set;
 476         struct hwpstate_setting *hwpstate_set;
 477         int count, error, i;
 478
 479         perf_set = malloc(MAX_SETTINGS * sizeof(*perf_set), M_TEMP, M_NOWAIT);
 480         if (perf_set == NULL) {
 481                 HWPSTATE_DEBUG(dev, "nomem\n");
 482                 return (ENOMEM);
 483         }
 484         /*
 485          * Fetch settings from acpi_perf.
 486          * Now it is attached, and has info only flag.
 487          */
 488         count = MAX_SETTINGS;
 489         error = CPUFREQ_DRV_SETTINGS(perf_dev, perf_set, &count);
 490         if (error) {
 491                 HWPSTATE_DEBUG(dev, "error: CPUFREQ_DRV_SETTINGS.\n");
 492                 goto out;
 493         }
 494         sc = device_get_softc(dev);
 495         sc->cfnum = count;
 496         hwpstate_set = sc->hwpstate_settings;
 497         for (i = 0; i < count; i++) {
 498                 if (i == perf_set[i].spec[0]) {
 499                         hwpstate_set[i].pstate_id = i;
 500                         hwpstate_set[i].freq = perf_set[i].freq;
 501                         hwpstate_set[i].volts = perf_set[i].volts;
 502                         hwpstate_set[i].power = perf_set[i].power;
 503                         hwpstate_set[i].lat = perf_set[i].lat;
 504                 } else {
 505                         HWPSTATE_DEBUG(dev, "ACPI _PSS object mismatch.\n");
 506                         error = ENXIO;
 507                         goto out;
 508                 }
 509         }
 510 out:
 511         if (perf_set)
 512                 free(perf_set, M_TEMP);
 513         return (error);
 514 }
 515
 516 static int
 517 hwpstate_detach(device_t dev)
 518 {
 519
 520         hwpstate_goto_pstate(dev, 0);
 521         return (cpufreq_unregister(dev));
 522 }
 523
 524 static int
 525 hwpstate_shutdown(device_t dev)
 526 {
 527
 528         /* hwpstate_goto_pstate(dev, 0); */
 529         return (0);
 530 }
 531
 532 static int
 533 hwpstate_features(driver_t *driver, u_int *features)
 534 {
 535
 536         /* Notify the ACPI CPU that we support direct access to MSRs */
 537         *features = ACPI_CAP_PERF_MSRS;
 538         return (0);
 539 }