sys/x86/cpufreq/hwpstate.c

   1 /*-
   2  * Copyright (c) 2005 Nate Lawson
   3  * Copyright (c) 2004 Colin Percival
   4  * Copyright (c) 2004-2005 Bruno Durcot
   5  * Copyright (c) 2004 FUKUDA Nobuhiko
   6  * Copyright (c) 2009 Michael Reifenberger
   7  * Copyright (c) 2009 Norikatsu Shigemura
   8  * Copyright (c) 2008-2009 Gen Otsuji
   9  *
  10  * This code is depending on kern_cpu.c, est.c, powernow.c, p4tcc.c, smist.c
  11  * in various parts. The authors of these files are Nate Lawson,
  12  * Colin Percival, Bruno Durcot, and FUKUDA Nobuhiko.
  13  * This code contains patches by Michael Reifenberger and Norikatsu Shigemura.
  14  * Thank you.
  15  *
  16  * Redistribution and use in source and binary forms, with or without
  17  * modification, are permitted providing that the following conditions
  18  * are met:
  19  * 1. Redistributions of source code must retain the above copyright
  20  *    notice, this list of conditions and the following disclaimer.
  21  * 2. Redistributions in binary form must reproduce the above copyright
  22  *    notice, this list of conditions and the following disclaimer in the
  23  *    documentation and/or other materials provided with the distribution.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR
  26  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  27  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  28  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  29  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  30  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  31  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  32  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  33  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  34  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /*
  39  * For more info:
  40  * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 10h Processors
  41  * 31116 Rev 3.20  February 04, 2009
  42  * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 11h Processors
  43  * 41256 Rev 3.00 - July 07, 2008
  44  */
  45
  46 #include <sys/cdefs.h>
  47 __FBSDID("$FreeBSD$");
  48
  49 #include <sys/param.h>
  50 #include <sys/bus.h>
  51 #include <sys/cpu.h>
  52 #include <sys/kernel.h>
  53 #include <sys/module.h>
  54 #include <sys/malloc.h>
  55 #include <sys/proc.h>
  56 #include <sys/pcpu.h>
  57 #include <sys/smp.h>
  58 #include <sys/sched.h>
  59
  60 #include <machine/md_var.h>
  61 #include <machine/cputypes.h>
  62 #include <machine/specialreg.h>
  63
  64 #include <contrib/dev/acpica/include/acpi.h>
  65
  66 #include <dev/acpica/acpivar.h>
  67
  68 #include "acpi_if.h"
  69 #include "cpufreq_if.h"
  70
  71 #define MSR_AMD_10H_11H_LIMIT   0xc0010061
  72 #define MSR_AMD_10H_11H_CONTROL 0xc0010062
  73 #define MSR_AMD_10H_11H_STATUS  0xc0010063
  74 #define MSR_AMD_10H_11H_CONFIG  0xc0010064
  75
  76 #define AMD_10H_11H_MAX_STATES  16
  77
  78 /* for MSR_AMD_10H_11H_LIMIT C001_0061 */
  79 #define AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)     (((msr) >> 4) & 0x7)
  80 #define AMD_10H_11H_GET_PSTATE_LIMIT(msr)       (((msr)) & 0x7)
  81 /* for MSR_AMD_10H_11H_CONFIG 10h:C001_0064:68 / 11h:C001_0064:6B */
  82 #define AMD_10H_11H_CUR_VID(msr)                (((msr) >> 9) & 0x7F)
  83 #define AMD_10H_11H_CUR_DID(msr)                (((msr) >> 6) & 0x07)
  84 #define AMD_10H_11H_CUR_FID(msr)                ((msr) & 0x3F)
  85
  86 #define AMD_17H_CUR_VID(msr)                    (((msr) >> 14) & 0xFF)
  87 #define AMD_17H_CUR_DID(msr)                    (((msr) >> 8) & 0x3F)
  88 #define AMD_17H_CUR_FID(msr)                    ((msr) & 0xFF)
  89
  90 #define HWPSTATE_DEBUG(dev, msg...)                     \
  91         do{                                             \
  92                 if(hwpstate_verbose)                    \
  93                         device_printf(dev, msg);        \
  94         }while(0)
  95
  96 struct hwpstate_setting {
  97         int     freq;           /* CPU clock in Mhz or 100ths of a percent. */
  98         int     volts;          /* Voltage in mV. */
  99         int     power;          /* Power consumed in mW. */
 100         int     lat;            /* Transition latency in us. */
 101         int     pstate_id;      /* P-State id */
 102 };
 103
 104 struct hwpstate_softc {
 105         device_t                dev;
 106         struct hwpstate_setting hwpstate_settings[AMD_10H_11H_MAX_STATES];
 107         int                     cfnum;
 108 };
 109
 110 static void     hwpstate_identify(driver_t *driver, device_t parent);
 111 static int      hwpstate_probe(device_t dev);
 112 static int      hwpstate_attach(device_t dev);
 113 static int      hwpstate_detach(device_t dev);
 114 static int      hwpstate_set(device_t dev, const struct cf_setting *cf);
 115 static int      hwpstate_get(device_t dev, struct cf_setting *cf);
 116 static int      hwpstate_settings(device_t dev, struct cf_setting *sets, int *count);
 117 static int      hwpstate_type(device_t dev, int *type);
 118 static int      hwpstate_shutdown(device_t dev);
 119 static int      hwpstate_features(driver_t *driver, u_int *features);
 120 static int      hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev);
 121 static int      hwpstate_get_info_from_msr(device_t dev);
 122 static int      hwpstate_goto_pstate(device_t dev, int pstate_id);
 123
 124 static int      hwpstate_verbose = 0;
 125 SYSCTL_INT(_debug, OID_AUTO, hwpstate_verbose, CTLFLAG_RWTUN,
 126        &hwpstate_verbose, 0, "Debug hwpstate");
 127
 128 static device_method_t hwpstate_methods[] = {
 129         /* Device interface */
 130         DEVMETHOD(device_identify,      hwpstate_identify),
 131         DEVMETHOD(device_probe,         hwpstate_probe),
 132         DEVMETHOD(device_attach,        hwpstate_attach),
 133         DEVMETHOD(device_detach,        hwpstate_detach),
 134         DEVMETHOD(device_shutdown,      hwpstate_shutdown),
 135
 136         /* cpufreq interface */
 137         DEVMETHOD(cpufreq_drv_set,      hwpstate_set),
 138         DEVMETHOD(cpufreq_drv_get,      hwpstate_get),
 139         DEVMETHOD(cpufreq_drv_settings, hwpstate_settings),
 140         DEVMETHOD(cpufreq_drv_type,     hwpstate_type),
 141
 142         /* ACPI interface */
 143         DEVMETHOD(acpi_get_features,    hwpstate_features),
 144
 145         {0, 0}
 146 };
 147
 148 static devclass_t hwpstate_devclass;
 149 static driver_t hwpstate_driver = {
 150         "hwpstate",
 151         hwpstate_methods,
 152         sizeof(struct hwpstate_softc),
 153 };
 154
 155 DRIVER_MODULE(hwpstate, cpu, hwpstate_driver, hwpstate_devclass, 0, 0);
 156
 157 /*
 158  * Go to Px-state on all cpus considering the limit.
 159  */
 160 static int
 161 hwpstate_goto_pstate(device_t dev, int pstate)
 162 {
 163         int i;
 164         uint64_t msr;
 165         int j;
 166         int limit;
 167         int id = pstate;
 168         int error;
 169
 170         /* get the current pstate limit */
 171         msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
 172         limit = AMD_10H_11H_GET_PSTATE_LIMIT(msr);
 173         if(limit > id)
 174                 id = limit;
 175
 176         /*
 177          * We are going to the same Px-state on all cpus.
 178          * Probably should take _PSD into account.
 179          */
 180         error = 0;
 181         CPU_FOREACH(i) {
 182                 /* Bind to each cpu. */
 183                 thread_lock(curthread);
 184                 sched_bind(curthread, i);
 185                 thread_unlock(curthread);
 186                 HWPSTATE_DEBUG(dev, "setting P%d-state on cpu%d\n",
 187                         id, PCPU_GET(cpuid));
 188                 /* Go To Px-state */
 189                 wrmsr(MSR_AMD_10H_11H_CONTROL, id);
 190         }
 191         CPU_FOREACH(i) {
 192                 /* Bind to each cpu. */
 193                 thread_lock(curthread);
 194                 sched_bind(curthread, i);
 195                 thread_unlock(curthread);
 196                 /* wait loop (100*100 usec is enough ?) */
 197                 for(j = 0; j < 100; j++){
 198                         /* get the result. not assure msr=id */
 199                         msr = rdmsr(MSR_AMD_10H_11H_STATUS);
 200                         if(msr == id){
 201                                 break;
 202                         }
 203                         DELAY(100);
 204                 }
 205                 HWPSTATE_DEBUG(dev, "result: P%d-state on cpu%d\n",
 206                     (int)msr, PCPU_GET(cpuid));
 207                 if (msr != id) {
 208                         HWPSTATE_DEBUG(dev, "error: loop is not enough.\n");
 209                         error = ENXIO;
 210                 }
 211         }
 212         thread_lock(curthread);
 213         sched_unbind(curthread);
 214         thread_unlock(curthread);
 215         return (error);
 216 }
 217
 218 static int
 219 hwpstate_set(device_t dev, const struct cf_setting *cf)
 220 {
 221         struct hwpstate_softc *sc;
 222         struct hwpstate_setting *set;
 223         int i;
 224
 225         if (cf == NULL)
 226                 return (EINVAL);
 227         sc = device_get_softc(dev);
 228         set = sc->hwpstate_settings;
 229         for (i = 0; i < sc->cfnum; i++)
 230                 if (CPUFREQ_CMP(cf->freq, set[i].freq))
 231                         break;
 232         if (i == sc->cfnum)
 233                 return (EINVAL);
 234
 235         return (hwpstate_goto_pstate(dev, set[i].pstate_id));
 236 }
 237
 238 static int
 239 hwpstate_get(device_t dev, struct cf_setting *cf)
 240 {
 241         struct hwpstate_softc *sc;
 242         struct hwpstate_setting set;
 243         uint64_t msr;
 244
 245         sc = device_get_softc(dev);
 246         if (cf == NULL)
 247                 return (EINVAL);
 248         msr = rdmsr(MSR_AMD_10H_11H_STATUS);
 249         if(msr >= sc->cfnum)
 250                 return (EINVAL);
 251         set = sc->hwpstate_settings[msr];
 252
 253         cf->freq = set.freq;
 254         cf->volts = set.volts;
 255         cf->power = set.power;
 256         cf->lat = set.lat;
 257         cf->dev = dev;
 258         return (0);
 259 }
 260
 261 static int
 262 hwpstate_settings(device_t dev, struct cf_setting *sets, int *count)
 263 {
 264         struct hwpstate_softc *sc;
 265         struct hwpstate_setting set;
 266         int i;
 267
 268         if (sets == NULL || count == NULL)
 269                 return (EINVAL);
 270         sc = device_get_softc(dev);
 271         if (*count < sc->cfnum)
 272                 return (E2BIG);
 273         for (i = 0; i < sc->cfnum; i++, sets++) {
 274                 set = sc->hwpstate_settings[i];
 275                 sets->freq = set.freq;
 276                 sets->volts = set.volts;
 277                 sets->power = set.power;
 278                 sets->lat = set.lat;
 279                 sets->dev = dev;
 280         }
 281         *count = sc->cfnum;
 282
 283         return (0);
 284 }
 285
 286 static int
 287 hwpstate_type(device_t dev, int *type)
 288 {
 289
 290         if (type == NULL)
 291                 return (EINVAL);
 292
 293         *type = CPUFREQ_TYPE_ABSOLUTE;
 294         return (0);
 295 }
 296
 297 static void
 298 hwpstate_identify(driver_t *driver, device_t parent)
 299 {
 300
 301         if (device_find_child(parent, "hwpstate", -1) != NULL)
 302                 return;
 303
 304         if (cpu_vendor_id != CPU_VENDOR_AMD || CPUID_TO_FAMILY(cpu_id) < 0x10)
 305                 return;
 306
 307         /*
 308          * Check if hardware pstate enable bit is set.
 309          */
 310         if ((amd_pminfo & AMDPM_HW_PSTATE) == 0) {
 311                 HWPSTATE_DEBUG(parent, "hwpstate enable bit is not set.\n");
 312                 return;
 313         }
 314
 315         if (resource_disabled("hwpstate", 0))
 316                 return;
 317
 318         if (BUS_ADD_CHILD(parent, 10, "hwpstate", -1) == NULL)
 319                 device_printf(parent, "hwpstate: add child failed\n");
 320 }
 321
 322 static int
 323 hwpstate_probe(device_t dev)
 324 {
 325         struct hwpstate_softc *sc;
 326         device_t perf_dev;
 327         uint64_t msr;
 328         int error, type;
 329
 330         /*
 331          * Only hwpstate0.
 332          * It goes well with acpi_throttle.
 333          */
 334         if (device_get_unit(dev) != 0)
 335                 return (ENXIO);
 336
 337         sc = device_get_softc(dev);
 338         sc->dev = dev;
 339
 340         /*
 341          * Check if acpi_perf has INFO only flag.
 342          */
 343         perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
 344         error = TRUE;
 345         if (perf_dev && device_is_attached(perf_dev)) {
 346                 error = CPUFREQ_DRV_TYPE(perf_dev, &type);
 347                 if (error == 0) {
 348                         if ((type & CPUFREQ_FLAG_INFO_ONLY) == 0) {
 349                                 /*
 350                                  * If acpi_perf doesn't have INFO_ONLY flag,
 351                                  * it will take care of pstate transitions.
 352                                  */
 353                                 HWPSTATE_DEBUG(dev, "acpi_perf will take care of pstate transitions.\n");
 354                                 return (ENXIO);
 355                         } else {
 356                                 /*
 357                                  * If acpi_perf has INFO_ONLY flag, (_PCT has FFixedHW)
 358                                  * we can get _PSS info from acpi_perf
 359                                  * without going into ACPI.
 360                                  */
 361                                 HWPSTATE_DEBUG(dev, "going to fetch info from acpi_perf\n");
 362                                 error = hwpstate_get_info_from_acpi_perf(dev, perf_dev);
 363                         }
 364                 }
 365         }
 366
 367         if (error == 0) {
 368                 /*
 369                  * Now we get _PSS info from acpi_perf without error.
 370                  * Let's check it.
 371                  */
 372                 msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
 373                 if (sc->cfnum != 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)) {
 374                         HWPSTATE_DEBUG(dev, "MSR (%jd) and ACPI _PSS (%d)"
 375                             " count mismatch\n", (intmax_t)msr, sc->cfnum);
 376                         error = TRUE;
 377                 }
 378         }
 379
 380         /*
 381          * If we cannot get info from acpi_perf,
 382          * Let's get info from MSRs.
 383          */
 384         if (error)
 385                 error = hwpstate_get_info_from_msr(dev);
 386         if (error)
 387                 return (error);
 388
 389         device_set_desc(dev, "Cool`n'Quiet 2.0");
 390         return (0);
 391 }
 392
 393 static int
 394 hwpstate_attach(device_t dev)
 395 {
 396
 397         return (cpufreq_register(dev));
 398 }
 399
 400 static int
 401 hwpstate_get_info_from_msr(device_t dev)
 402 {
 403         struct hwpstate_softc *sc;
 404         struct hwpstate_setting *hwpstate_set;
 405         uint64_t msr;
 406         int family, i, fid, did;
 407
 408         family = CPUID_TO_FAMILY(cpu_id);
 409         sc = device_get_softc(dev);
 410         /* Get pstate count */
 411         msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
 412         sc->cfnum = 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr);
 413         hwpstate_set = sc->hwpstate_settings;
 414         for (i = 0; i < sc->cfnum; i++) {
 415                 msr = rdmsr(MSR_AMD_10H_11H_CONFIG + i);
 416                 if ((msr & ((uint64_t)1 << 63)) == 0) {
 417                         HWPSTATE_DEBUG(dev, "msr is not valid.\n");
 418                         return (ENXIO);
 419                 }
 420                 did = AMD_10H_11H_CUR_DID(msr);
 421                 fid = AMD_10H_11H_CUR_FID(msr);
 422
 423                 /* Convert fid/did to frequency. */
 424                 switch(family) {
 425                 case 0x11:
 426                         hwpstate_set[i].freq = (100 * (fid + 0x08)) >> did;
 427                         break;
 428                 case 0x10:
 429                 case 0x12:
 430                 case 0x15:
 431                 case 0x16:
 432                         hwpstate_set[i].freq = (100 * (fid + 0x10)) >> did;
 433                         break;
 434                 case 0x17:
 435                         did = AMD_17H_CUR_DID(msr);
 436                         if (did == 0) {
 437                                 HWPSTATE_DEBUG(dev, "unexpected did: 0\n");
 438                                 did = 1;
 439                         }
 440                         fid = AMD_17H_CUR_FID(msr);
 441                         hwpstate_set[i].freq = (200 * fid) / did;
 442                         break;
 443                 default:
 444                         HWPSTATE_DEBUG(dev, "get_info_from_msr: AMD family"
 445                             " 0x%02x CPUs are not supported yet\n", family);
 446                         return (ENXIO);
 447                 }
 448                 hwpstate_set[i].pstate_id = i;
 449                 /* There was volts calculation, but deleted it. */
 450                 hwpstate_set[i].volts = CPUFREQ_VAL_UNKNOWN;
 451                 hwpstate_set[i].power = CPUFREQ_VAL_UNKNOWN;
 452                 hwpstate_set[i].lat = CPUFREQ_VAL_UNKNOWN;
 453         }
 454         return (0);
 455 }
 456
 457 static int
 458 hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev)
 459 {
 460         struct hwpstate_softc *sc;
 461         struct cf_setting *perf_set;
 462         struct hwpstate_setting *hwpstate_set;
 463         int count, error, i;
 464
 465         perf_set = malloc(MAX_SETTINGS * sizeof(*perf_set), M_TEMP, M_NOWAIT);
 466         if (perf_set == NULL) {
 467                 HWPSTATE_DEBUG(dev, "nomem\n");
 468                 return (ENOMEM);
 469         }
 470         /*
 471          * Fetch settings from acpi_perf.
 472          * Now it is attached, and has info only flag.
 473          */
 474         count = MAX_SETTINGS;
 475         error = CPUFREQ_DRV_SETTINGS(perf_dev, perf_set, &count);
 476         if (error) {
 477                 HWPSTATE_DEBUG(dev, "error: CPUFREQ_DRV_SETTINGS.\n");
 478                 goto out;
 479         }
 480         sc = device_get_softc(dev);
 481         sc->cfnum = count;
 482         hwpstate_set = sc->hwpstate_settings;
 483         for (i = 0; i < count; i++) {
 484                 if (i == perf_set[i].spec[0]) {
 485                         hwpstate_set[i].pstate_id = i;
 486                         hwpstate_set[i].freq = perf_set[i].freq;
 487                         hwpstate_set[i].volts = perf_set[i].volts;
 488                         hwpstate_set[i].power = perf_set[i].power;
 489                         hwpstate_set[i].lat = perf_set[i].lat;
 490                 } else {
 491                         HWPSTATE_DEBUG(dev, "ACPI _PSS object mismatch.\n");
 492                         error = ENXIO;
 493                         goto out;
 494                 }
 495         }
 496 out:
 497         if (perf_set)
 498                 free(perf_set, M_TEMP);
 499         return (error);
 500 }
 501
 502 static int
 503 hwpstate_detach(device_t dev)
 504 {
 505
 506         hwpstate_goto_pstate(dev, 0);
 507         return (cpufreq_unregister(dev));
 508 }
 509
 510 static int
 511 hwpstate_shutdown(device_t dev)
 512 {
 513
 514         /* hwpstate_goto_pstate(dev, 0); */
 515         return (0);
 516 }
 517
 518 static int
 519 hwpstate_features(driver_t *driver, u_int *features)
 520 {
 521
 522         /* Notify the ACPI CPU that we support direct access to MSRs */
 523         *features = ACPI_CAP_PERF_MSRS;
 524         return (0);
 525 }