sys/x86/cpufreq/hwpstate.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2005 Nate Lawson
   5  * Copyright (c) 2004 Colin Percival
   6  * Copyright (c) 2004-2005 Bruno Durcot
   7  * Copyright (c) 2004 FUKUDA Nobuhiko
   8  * Copyright (c) 2009 Michael Reifenberger
   9  * Copyright (c) 2009 Norikatsu Shigemura
  10  * Copyright (c) 2008-2009 Gen Otsuji
  11  *
  12  * This code is depending on kern_cpu.c, est.c, powernow.c, p4tcc.c, smist.c
  13  * in various parts. The authors of these files are Nate Lawson,
  14  * Colin Percival, Bruno Durcot, and FUKUDA Nobuhiko.
  15  * This code contains patches by Michael Reifenberger and Norikatsu Shigemura.
  16  * Thank you.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted providing that the following conditions
  20  * are met:
  21  * 1. Redistributions of source code must retain the above copyright
  22  *    notice, this list of conditions and the following disclaimer.
  23  * 2. Redistributions in binary form must reproduce the above copyright
  24  *    notice, this list of conditions and the following disclaimer in the
  25  *    documentation and/or other materials provided with the distribution.
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR
  28  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  29  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  30  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  31  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGE.
  38  */
  39
  40 /*
  41  * For more info:
  42  * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 10h Processors
  43  * 31116 Rev 3.20  February 04, 2009
  44  * BIOS and Kernel Developer's Guide(BKDG) for AMD Family 11h Processors
  45  * 41256 Rev 3.00 - July 07, 2008
  46  */
  47
  48 #include <sys/cdefs.h>
  49 __FBSDID("$FreeBSD$");
  50
  51 #include <sys/param.h>
  52 #include <sys/bus.h>
  53 #include <sys/cpu.h>
  54 #include <sys/kernel.h>
  55 #include <sys/module.h>
  56 #include <sys/malloc.h>
  57 #include <sys/proc.h>
  58 #include <sys/pcpu.h>
  59 #include <sys/smp.h>
  60 #include <sys/sched.h>
  61
  62 #include <machine/md_var.h>
  63 #include <machine/cputypes.h>
  64 #include <machine/specialreg.h>
  65
  66 #include <contrib/dev/acpica/include/acpi.h>
  67
  68 #include <dev/acpica/acpivar.h>
  69
  70 #include "acpi_if.h"
  71 #include "cpufreq_if.h"
  72
  73 #define MSR_AMD_10H_11H_LIMIT   0xc0010061
  74 #define MSR_AMD_10H_11H_CONTROL 0xc0010062
  75 #define MSR_AMD_10H_11H_STATUS  0xc0010063
  76 #define MSR_AMD_10H_11H_CONFIG  0xc0010064
  77
  78 #define AMD_10H_11H_MAX_STATES  16
  79
  80 /* for MSR_AMD_10H_11H_LIMIT C001_0061 */
  81 #define AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)     (((msr) >> 4) & 0x7)
  82 #define AMD_10H_11H_GET_PSTATE_LIMIT(msr)       (((msr)) & 0x7)
  83 /* for MSR_AMD_10H_11H_CONFIG 10h:C001_0064:68 / 11h:C001_0064:6B */
  84 #define AMD_10H_11H_CUR_VID(msr)                (((msr) >> 9) & 0x7F)
  85 #define AMD_10H_11H_CUR_DID(msr)                (((msr) >> 6) & 0x07)
  86 #define AMD_10H_11H_CUR_FID(msr)                ((msr) & 0x3F)
  87
  88 #define AMD_17H_CUR_VID(msr)                    (((msr) >> 14) & 0xFF)
  89 #define AMD_17H_CUR_DID(msr)                    (((msr) >> 8) & 0x3F)
  90 #define AMD_17H_CUR_FID(msr)                    ((msr) & 0xFF)
  91
  92 #define HWPSTATE_DEBUG(dev, msg...)                     \
  93         do {                                            \
  94                 if (hwpstate_verbose)                   \
  95                         device_printf(dev, msg);        \
  96         } while (0)
  97
  98 struct hwpstate_setting {
  99         int     freq;           /* CPU clock in Mhz or 100ths of a percent. */
 100         int     volts;          /* Voltage in mV. */
 101         int     power;          /* Power consumed in mW. */
 102         int     lat;            /* Transition latency in us. */
 103         int     pstate_id;      /* P-State id */
 104 };
 105
 106 struct hwpstate_softc {
 107         device_t                dev;
 108         struct hwpstate_setting hwpstate_settings[AMD_10H_11H_MAX_STATES];
 109         int                     cfnum;
 110 };
 111
 112 static void     hwpstate_identify(driver_t *driver, device_t parent);
 113 static int      hwpstate_probe(device_t dev);
 114 static int      hwpstate_attach(device_t dev);
 115 static int      hwpstate_detach(device_t dev);
 116 static int      hwpstate_set(device_t dev, const struct cf_setting *cf);
 117 static int      hwpstate_get(device_t dev, struct cf_setting *cf);
 118 static int      hwpstate_settings(device_t dev, struct cf_setting *sets, int *count);
 119 static int      hwpstate_type(device_t dev, int *type);
 120 static int      hwpstate_shutdown(device_t dev);
 121 static int      hwpstate_features(driver_t *driver, u_int *features);
 122 static int      hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev);
 123 static int      hwpstate_get_info_from_msr(device_t dev);
 124 static int      hwpstate_goto_pstate(device_t dev, int pstate_id);
 125
 126 static int      hwpstate_verbose = 0;
 127 SYSCTL_INT(_debug, OID_AUTO, hwpstate_verbose, CTLFLAG_RWTUN,
 128     &hwpstate_verbose, 0, "Debug hwpstate");
 129
 130 static device_method_t hwpstate_methods[] = {
 131         /* Device interface */
 132         DEVMETHOD(device_identify,      hwpstate_identify),
 133         DEVMETHOD(device_probe,         hwpstate_probe),
 134         DEVMETHOD(device_attach,        hwpstate_attach),
 135         DEVMETHOD(device_detach,        hwpstate_detach),
 136         DEVMETHOD(device_shutdown,      hwpstate_shutdown),
 137
 138         /* cpufreq interface */
 139         DEVMETHOD(cpufreq_drv_set,      hwpstate_set),
 140         DEVMETHOD(cpufreq_drv_get,      hwpstate_get),
 141         DEVMETHOD(cpufreq_drv_settings, hwpstate_settings),
 142         DEVMETHOD(cpufreq_drv_type,     hwpstate_type),
 143
 144         /* ACPI interface */
 145         DEVMETHOD(acpi_get_features,    hwpstate_features),
 146
 147         {0, 0}
 148 };
 149
 150 static devclass_t hwpstate_devclass;
 151 static driver_t hwpstate_driver = {
 152         "hwpstate",
 153         hwpstate_methods,
 154         sizeof(struct hwpstate_softc),
 155 };
 156
 157 DRIVER_MODULE(hwpstate, cpu, hwpstate_driver, hwpstate_devclass, 0, 0);
 158
 159 /*
 160  * Go to Px-state on all cpus considering the limit.
 161  */
 162 static int
 163 hwpstate_goto_pstate(device_t dev, int pstate)
 164 {
 165         sbintime_t sbt;
 166         int i;
 167         uint64_t msr;
 168         int j;
 169         int limit;
 170         int id = pstate;
 171         int error;
 172
 173         /* get the current pstate limit */
 174         msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
 175         limit = AMD_10H_11H_GET_PSTATE_LIMIT(msr);
 176         if (limit > id)
 177                 id = limit;
 178
 179         /*
 180          * We are going to the same Px-state on all cpus.
 181          * Probably should take _PSD into account.
 182          */
 183         error = 0;
 184         CPU_FOREACH(i) {
 185                 /* Bind to each cpu. */
 186                 thread_lock(curthread);
 187                 sched_bind(curthread, i);
 188                 thread_unlock(curthread);
 189                 HWPSTATE_DEBUG(dev, "setting P%d-state on cpu%d\n",
 190                     id, PCPU_GET(cpuid));
 191                 /* Go To Px-state */
 192                 wrmsr(MSR_AMD_10H_11H_CONTROL, id);
 193         }
 194         CPU_FOREACH(i) {
 195                 /* Bind to each cpu. */
 196                 thread_lock(curthread);
 197                 sched_bind(curthread, i);
 198                 thread_unlock(curthread);
 199                 /* wait loop (100*100 usec is enough ?) */
 200                 for (j = 0; j < 100; j++) {
 201                         /* get the result. not assure msr=id */
 202                         msr = rdmsr(MSR_AMD_10H_11H_STATUS);
 203                         if (msr == id)
 204                                 break;
 205                         sbt = SBT_1MS / 10;
 206                         tsleep_sbt(dev, PZERO, "pstate_goto", sbt,
 207                             sbt >> tc_precexp, 0);
 208                 }
 209                 HWPSTATE_DEBUG(dev, "result: P%d-state on cpu%d\n",
 210                     (int)msr, PCPU_GET(cpuid));
 211                 if (msr != id) {
 212                         HWPSTATE_DEBUG(dev, "error: loop is not enough.\n");
 213                         error = ENXIO;
 214                 }
 215         }
 216         thread_lock(curthread);
 217         sched_unbind(curthread);
 218         thread_unlock(curthread);
 219         return (error);
 220 }
 221
 222 static int
 223 hwpstate_set(device_t dev, const struct cf_setting *cf)
 224 {
 225         struct hwpstate_softc *sc;
 226         struct hwpstate_setting *set;
 227         int i;
 228
 229         if (cf == NULL)
 230                 return (EINVAL);
 231         sc = device_get_softc(dev);
 232         set = sc->hwpstate_settings;
 233         for (i = 0; i < sc->cfnum; i++)
 234                 if (CPUFREQ_CMP(cf->freq, set[i].freq))
 235                         break;
 236         if (i == sc->cfnum)
 237                 return (EINVAL);
 238
 239         return (hwpstate_goto_pstate(dev, set[i].pstate_id));
 240 }
 241
 242 static int
 243 hwpstate_get(device_t dev, struct cf_setting *cf)
 244 {
 245         struct hwpstate_softc *sc;
 246         struct hwpstate_setting set;
 247         uint64_t msr;
 248
 249         sc = device_get_softc(dev);
 250         if (cf == NULL)
 251                 return (EINVAL);
 252         msr = rdmsr(MSR_AMD_10H_11H_STATUS);
 253         if (msr >= sc->cfnum)
 254                 return (EINVAL);
 255         set = sc->hwpstate_settings[msr];
 256
 257         cf->freq = set.freq;
 258         cf->volts = set.volts;
 259         cf->power = set.power;
 260         cf->lat = set.lat;
 261         cf->dev = dev;
 262         return (0);
 263 }
 264
 265 static int
 266 hwpstate_settings(device_t dev, struct cf_setting *sets, int *count)
 267 {
 268         struct hwpstate_softc *sc;
 269         struct hwpstate_setting set;
 270         int i;
 271
 272         if (sets == NULL || count == NULL)
 273                 return (EINVAL);
 274         sc = device_get_softc(dev);
 275         if (*count < sc->cfnum)
 276                 return (E2BIG);
 277         for (i = 0; i < sc->cfnum; i++, sets++) {
 278                 set = sc->hwpstate_settings[i];
 279                 sets->freq = set.freq;
 280                 sets->volts = set.volts;
 281                 sets->power = set.power;
 282                 sets->lat = set.lat;
 283                 sets->dev = dev;
 284         }
 285         *count = sc->cfnum;
 286
 287         return (0);
 288 }
 289
 290 static int
 291 hwpstate_type(device_t dev, int *type)
 292 {
 293
 294         if (type == NULL)
 295                 return (EINVAL);
 296
 297         *type = CPUFREQ_TYPE_ABSOLUTE;
 298         return (0);
 299 }
 300
 301 static void
 302 hwpstate_identify(driver_t *driver, device_t parent)
 303 {
 304
 305         if (device_find_child(parent, "hwpstate", -1) != NULL)
 306                 return;
 307
 308         if (cpu_vendor_id != CPU_VENDOR_AMD || CPUID_TO_FAMILY(cpu_id) < 0x10)
 309                 return;
 310
 311         /*
 312          * Check if hardware pstate enable bit is set.
 313          */
 314         if ((amd_pminfo & AMDPM_HW_PSTATE) == 0) {
 315                 HWPSTATE_DEBUG(parent, "hwpstate enable bit is not set.\n");
 316                 return;
 317         }
 318
 319         if (resource_disabled("hwpstate", 0))
 320                 return;
 321
 322         if (BUS_ADD_CHILD(parent, 10, "hwpstate", -1) == NULL)
 323                 device_printf(parent, "hwpstate: add child failed\n");
 324 }
 325
 326 static int
 327 hwpstate_probe(device_t dev)
 328 {
 329         struct hwpstate_softc *sc;
 330         device_t perf_dev;
 331         uint64_t msr;
 332         int error, type;
 333
 334         /*
 335          * Only hwpstate0.
 336          * It goes well with acpi_throttle.
 337          */
 338         if (device_get_unit(dev) != 0)
 339                 return (ENXIO);
 340
 341         sc = device_get_softc(dev);
 342         sc->dev = dev;
 343
 344         /*
 345          * Check if acpi_perf has INFO only flag.
 346          */
 347         perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
 348         error = TRUE;
 349         if (perf_dev && device_is_attached(perf_dev)) {
 350                 error = CPUFREQ_DRV_TYPE(perf_dev, &type);
 351                 if (error == 0) {
 352                         if ((type & CPUFREQ_FLAG_INFO_ONLY) == 0) {
 353                                 /*
 354                                  * If acpi_perf doesn't have INFO_ONLY flag,
 355                                  * it will take care of pstate transitions.
 356                                  */
 357                                 HWPSTATE_DEBUG(dev, "acpi_perf will take care of pstate transitions.\n");
 358                                 return (ENXIO);
 359                         } else {
 360                                 /*
 361                                  * If acpi_perf has INFO_ONLY flag, (_PCT has FFixedHW)
 362                                  * we can get _PSS info from acpi_perf
 363                                  * without going into ACPI.
 364                                  */
 365                                 HWPSTATE_DEBUG(dev, "going to fetch info from acpi_perf\n");
 366                                 error = hwpstate_get_info_from_acpi_perf(dev, perf_dev);
 367                         }
 368                 }
 369         }
 370
 371         if (error == 0) {
 372                 /*
 373                  * Now we get _PSS info from acpi_perf without error.
 374                  * Let's check it.
 375                  */
 376                 msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
 377                 if (sc->cfnum != 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)) {
 378                         HWPSTATE_DEBUG(dev, "MSR (%jd) and ACPI _PSS (%d)"
 379                             " count mismatch\n", (intmax_t)msr, sc->cfnum);
 380                         error = TRUE;
 381                 }
 382         }
 383
 384         /*
 385          * If we cannot get info from acpi_perf,
 386          * Let's get info from MSRs.
 387          */
 388         if (error)
 389                 error = hwpstate_get_info_from_msr(dev);
 390         if (error)
 391                 return (error);
 392
 393         device_set_desc(dev, "Cool`n'Quiet 2.0");
 394         return (0);
 395 }
 396
 397 static int
 398 hwpstate_attach(device_t dev)
 399 {
 400
 401         return (cpufreq_register(dev));
 402 }
 403
 404 static int
 405 hwpstate_get_info_from_msr(device_t dev)
 406 {
 407         struct hwpstate_softc *sc;
 408         struct hwpstate_setting *hwpstate_set;
 409         uint64_t msr;
 410         int family, i, fid, did;
 411
 412         family = CPUID_TO_FAMILY(cpu_id);
 413         sc = device_get_softc(dev);
 414         /* Get pstate count */
 415         msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
 416         sc->cfnum = 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr);
 417         hwpstate_set = sc->hwpstate_settings;
 418         for (i = 0; i < sc->cfnum; i++) {
 419                 msr = rdmsr(MSR_AMD_10H_11H_CONFIG + i);
 420                 if ((msr & ((uint64_t)1 << 63)) == 0) {
 421                         HWPSTATE_DEBUG(dev, "msr is not valid.\n");
 422                         return (ENXIO);
 423                 }
 424                 did = AMD_10H_11H_CUR_DID(msr);
 425                 fid = AMD_10H_11H_CUR_FID(msr);
 426
 427                 /* Convert fid/did to frequency. */
 428                 switch (family) {
 429                 case 0x11:
 430                         hwpstate_set[i].freq = (100 * (fid + 0x08)) >> did;
 431                         break;
 432                 case 0x10:
 433                 case 0x12:
 434                 case 0x15:
 435                 case 0x16:
 436                         hwpstate_set[i].freq = (100 * (fid + 0x10)) >> did;
 437                         break;
 438                 case 0x17:
 439                         did = AMD_17H_CUR_DID(msr);
 440                         if (did == 0) {
 441                                 HWPSTATE_DEBUG(dev, "unexpected did: 0\n");
 442                                 did = 1;
 443                         }
 444                         fid = AMD_17H_CUR_FID(msr);
 445                         hwpstate_set[i].freq = (200 * fid) / did;
 446                         break;
 447                 default:
 448                         HWPSTATE_DEBUG(dev, "get_info_from_msr: AMD family"
 449                             " 0x%02x CPUs are not supported yet\n", family);
 450                         return (ENXIO);
 451                 }
 452                 hwpstate_set[i].pstate_id = i;
 453                 /* There was volts calculation, but deleted it. */
 454                 hwpstate_set[i].volts = CPUFREQ_VAL_UNKNOWN;
 455                 hwpstate_set[i].power = CPUFREQ_VAL_UNKNOWN;
 456                 hwpstate_set[i].lat = CPUFREQ_VAL_UNKNOWN;
 457         }
 458         return (0);
 459 }
 460
 461 static int
 462 hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev)
 463 {
 464         struct hwpstate_softc *sc;
 465         struct cf_setting *perf_set;
 466         struct hwpstate_setting *hwpstate_set;
 467         int count, error, i;
 468
 469         perf_set = malloc(MAX_SETTINGS * sizeof(*perf_set), M_TEMP, M_NOWAIT);
 470         if (perf_set == NULL) {
 471                 HWPSTATE_DEBUG(dev, "nomem\n");
 472                 return (ENOMEM);
 473         }
 474         /*
 475          * Fetch settings from acpi_perf.
 476          * Now it is attached, and has info only flag.
 477          */
 478         count = MAX_SETTINGS;
 479         error = CPUFREQ_DRV_SETTINGS(perf_dev, perf_set, &count);
 480         if (error) {
 481                 HWPSTATE_DEBUG(dev, "error: CPUFREQ_DRV_SETTINGS.\n");
 482                 goto out;
 483         }
 484         sc = device_get_softc(dev);
 485         sc->cfnum = count;
 486         hwpstate_set = sc->hwpstate_settings;
 487         for (i = 0; i < count; i++) {
 488                 if (i == perf_set[i].spec[0]) {
 489                         hwpstate_set[i].pstate_id = i;
 490                         hwpstate_set[i].freq = perf_set[i].freq;
 491                         hwpstate_set[i].volts = perf_set[i].volts;
 492                         hwpstate_set[i].power = perf_set[i].power;
 493                         hwpstate_set[i].lat = perf_set[i].lat;
 494                 } else {
 495                         HWPSTATE_DEBUG(dev, "ACPI _PSS object mismatch.\n");
 496                         error = ENXIO;
 497                         goto out;
 498                 }
 499         }
 500 out:
 501         if (perf_set)
 502                 free(perf_set, M_TEMP);
 503         return (error);
 504 }
 505
 506 static int
 507 hwpstate_detach(device_t dev)
 508 {
 509
 510         hwpstate_goto_pstate(dev, 0);
 511         return (cpufreq_unregister(dev));
 512 }
 513
 514 static int
 515 hwpstate_shutdown(device_t dev)
 516 {
 517
 518         /* hwpstate_goto_pstate(dev, 0); */
 519         return (0);
 520 }
 521
 522 static int
 523 hwpstate_features(driver_t *driver, u_int *features)
 524 {
 525
 526         /* Notify the ACPI CPU that we support direct access to MSRs */
 527         *features = ACPI_CAP_PERF_MSRS;
 528         return (0);
 529 }