2 * Copyright (c) 2005 Nate Lawson
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Throttle clock frequency by using the thermal control circuit. This
29 * operates independently of SpeedStep and ACPI throttling and is supported
30 * on Pentium 4 and later models (feature TM).
32 * Reference: Intel Developer's manual v.3 #245472-012
34 * The original version of this driver was written by Ted Unangst for
35 * OpenBSD and imported by Maxim Sobolev. It was rewritten by Nate Lawson
36 * for use with the cpufreq framework.
39 #include <sys/cdefs.h>
40 __FBSDID("$FreeBSD$");
42 #include <sys/param.h>
43 #include <sys/systm.h>
46 #include <sys/kernel.h>
47 #include <sys/module.h>
49 #include <machine/md_var.h>
50 #include <machine/specialreg.h>
52 #include "cpufreq_if.h"
54 #include <contrib/dev/acpica/include/acpi.h>
56 #include <dev/acpica/acpivar.h>
66 #define TCC_NUM_SETTINGS 8
68 #define TCC_ENABLE_ONDEMAND (1<<4)
69 #define TCC_REG_OFFSET 1
70 #define TCC_SPEED_PERCENT(x) ((10000 * (x)) / TCC_NUM_SETTINGS)
72 static int p4tcc_features(driver_t *driver, u_int *features);
73 static void p4tcc_identify(driver_t *driver, device_t parent);
74 static int p4tcc_probe(device_t dev);
75 static int p4tcc_attach(device_t dev);
76 static int p4tcc_detach(device_t dev);
77 static int p4tcc_settings(device_t dev, struct cf_setting *sets,
79 static int p4tcc_set(device_t dev, const struct cf_setting *set);
80 static int p4tcc_get(device_t dev, struct cf_setting *set);
81 static int p4tcc_type(device_t dev, int *type);
83 static device_method_t p4tcc_methods[] = {
84 /* Device interface */
85 DEVMETHOD(device_identify, p4tcc_identify),
86 DEVMETHOD(device_probe, p4tcc_probe),
87 DEVMETHOD(device_attach, p4tcc_attach),
88 DEVMETHOD(device_detach, p4tcc_detach),
90 /* cpufreq interface */
91 DEVMETHOD(cpufreq_drv_set, p4tcc_set),
92 DEVMETHOD(cpufreq_drv_get, p4tcc_get),
93 DEVMETHOD(cpufreq_drv_type, p4tcc_type),
94 DEVMETHOD(cpufreq_drv_settings, p4tcc_settings),
97 DEVMETHOD(acpi_get_features, p4tcc_features),
102 static driver_t p4tcc_driver = {
105 sizeof(struct p4tcc_softc),
108 static devclass_t p4tcc_devclass;
109 DRIVER_MODULE(p4tcc, cpu, p4tcc_driver, p4tcc_devclass, 0, 0);
112 p4tcc_features(driver_t *driver, u_int *features)
115 /* Notify the ACPI CPU that we support direct access to MSRs */
116 *features = ACPI_CAP_THR_MSRS;
121 p4tcc_identify(driver_t *driver, device_t parent)
124 if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) != (CPUID_ACPI | CPUID_TM))
127 /* Make sure we're not being doubly invoked. */
128 if (device_find_child(parent, "p4tcc", -1) != NULL)
132 * We attach a p4tcc child for every CPU since settings need to
133 * be performed on every CPU in the SMP case. See section 13.15.3
134 * of the IA32 Intel Architecture Software Developer's Manual,
135 * Volume 3, for more info.
137 if (BUS_ADD_CHILD(parent, 10, "p4tcc", -1) == NULL)
138 device_printf(parent, "add p4tcc child failed\n");
142 p4tcc_probe(device_t dev)
145 if (resource_disabled("p4tcc", 0))
148 device_set_desc(dev, "CPU Frequency Thermal Control");
153 p4tcc_attach(device_t dev)
155 struct p4tcc_softc *sc;
156 struct cf_setting set;
158 sc = device_get_softc(dev);
160 sc->set_count = TCC_NUM_SETTINGS;
163 * On boot, the TCC is usually in Automatic mode where reading the
164 * current performance level is likely to produce bogus results.
165 * We record that state here and don't trust the contents of the
166 * status MSR until we've set it ourselves.
168 sc->auto_mode = TRUE;
171 * XXX: After a cursory glance at various Intel specification
172 * XXX: updates it seems like these tests for errata is bogus.
173 * XXX: As far as I can tell, the failure mode is benign, in
174 * XXX: that cpus with no errata will have their bottom two
175 * XXX: STPCLK# rates disabled, so rather than waste more time
176 * XXX: hunting down intel docs, just document it and punt. /phk
178 switch (cpu_id & 0xff) {
185 * These CPU models hang when set to 12.5%.
186 * See Errata O50, P44, and Z21.
190 case 0x07: /* errata N44 and P18 */
194 case 0x62: /* Pentium D B1: errata AA21 */
195 case 0x64: /* Pentium D C1: errata AA21 */
196 case 0x65: /* Pentium D D0: errata AA21 */
198 * These CPU models hang when set to 12.5% or 25%.
199 * See Errata N44, P18l and AA21.
204 sc->lowest_val = TCC_NUM_SETTINGS - sc->set_count + 1;
207 * Before we finish attach, switch to 100%. It's possible the BIOS
208 * set us to a lower rate. The user can override this after boot.
211 p4tcc_set(dev, &set);
213 cpufreq_register(dev);
218 p4tcc_detach(device_t dev)
220 struct cf_setting set;
223 error = cpufreq_unregister(dev);
228 * Before we finish detach, switch to Automatic mode.
231 p4tcc_set(dev, &set);
236 p4tcc_settings(device_t dev, struct cf_setting *sets, int *count)
238 struct p4tcc_softc *sc;
241 sc = device_get_softc(dev);
242 if (sets == NULL || count == NULL)
244 if (*count < sc->set_count)
247 /* Return a list of valid settings for this driver. */
248 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count);
249 val = TCC_NUM_SETTINGS;
250 for (i = 0; i < sc->set_count; i++, val--) {
251 sets[i].freq = TCC_SPEED_PERCENT(val);
254 *count = sc->set_count;
260 p4tcc_set(device_t dev, const struct cf_setting *set)
262 struct p4tcc_softc *sc;
268 sc = device_get_softc(dev);
271 * Validate requested state converts to a setting that is an integer
272 * from [sc->lowest_val .. TCC_NUM_SETTINGS].
274 val = set->freq * TCC_NUM_SETTINGS / 10000;
275 if (val * 10000 != set->freq * TCC_NUM_SETTINGS ||
276 val < sc->lowest_val || val > TCC_NUM_SETTINGS)
280 * Read the current register and mask off the old setting and
281 * On-Demand bit. If the new val is < 100%, set it and the On-Demand
282 * bit, otherwise just return to Automatic mode.
284 msr = rdmsr(MSR_THERM_CONTROL);
285 mask = (TCC_NUM_SETTINGS - 1) << TCC_REG_OFFSET;
286 msr &= ~(mask | TCC_ENABLE_ONDEMAND);
287 if (val < TCC_NUM_SETTINGS)
288 msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND;
289 wrmsr(MSR_THERM_CONTROL, msr);
292 * Record whether we're now in Automatic or On-Demand mode. We have
293 * to cache this since there is no reliable way to check if TCC is in
294 * Automatic mode (i.e., at 100% or possibly 50%). Reading bit 4 of
295 * the ACPI Thermal Monitor Control Register produces 0 no matter
296 * what the current mode.
298 if (msr & TCC_ENABLE_ONDEMAND)
299 sc->auto_mode = FALSE;
301 sc->auto_mode = TRUE;
307 p4tcc_get(device_t dev, struct cf_setting *set)
309 struct p4tcc_softc *sc;
315 sc = device_get_softc(dev);
318 * Read the current register and extract the current setting. If
319 * in automatic mode, assume we're at TCC_NUM_SETTINGS (100%).
321 * XXX This is not completely reliable since at high temperatures
322 * the CPU may be automatically throttling to 50% but it's the best
325 if (!sc->auto_mode) {
326 msr = rdmsr(MSR_THERM_CONTROL);
327 val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1);
329 val = TCC_NUM_SETTINGS;
331 memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set));
332 set->freq = TCC_SPEED_PERCENT(val);
339 p4tcc_type(device_t dev, int *type)
345 *type = CPUFREQ_TYPE_RELATIVE;