2 * Copyright (c) 1996, by Peter Wemm and Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #ifndef _X86_APICREG_H_
29 #define _X86_APICREG_H_
32 * Local && I/O APIC definitions.
36 * Pentium P54C+ Built-in APIC
37 * (Advanced programmable Interrupt Controller)
39 * Base Address of Built-in APIC in memory location
42 * Map of APIC Registers:
44 * Offset (hex) Description Read/Write state
47 * 020 ID Local APIC ID R/W
48 * 030 VER Local APIC Version R
53 * 080 Task Priority Register R/W
54 * 090 Arbitration Priority Register R
55 * 0A0 Processor Priority Register R
57 * 0C0 RRR Remote read R
58 * 0D0 Logical Destination R/W
59 * 0E0 Destination Format Register 0..27 R; 28..31 R/W
60 * 0F0 SVR Spurious Interrupt Vector Reg. 0..3 R; 4..9 R/W
85 * 280 Error Status Register R
92 * 2F0 Local Vector Table (CMCI) R/W
93 * 300 ICR_LOW Interrupt Command Reg. (0-31) R/W
94 * 310 ICR_HI Interrupt Command Reg. (32-63) R/W
95 * 320 Local Vector Table (Timer) R/W
96 * 330 Local Vector Table (Thermal) R/W (PIV+)
97 * 340 Local Vector Table (Performance) R/W (P6+)
98 * 350 LVT1 Local Vector Table (LINT0) R/W
99 * 360 LVT2 Local Vector Table (LINT1) R/W
100 * 370 LVT3 Local Vector Table (ERROR) R/W
101 * 380 Initial Count Reg. for Timer R/W
102 * 390 Current Count of Timer R
107 * 3E0 Timer Divide Configuration Reg. R/W
112 /******************************************************************************
113 * global defines, etc.
117 /******************************************************************************
118 * LOCAL APIC structure
122 #include <sys/types.h>
124 #define PAD3 int : 32; int : 32; int : 32
125 #define PAD4 int : 32; int : 32; int : 32; int : 32
131 u_int32_t version; PAD3;
144 u_int32_t isr0; PAD3;
145 u_int32_t isr1; PAD3;
146 u_int32_t isr2; PAD3;
147 u_int32_t isr3; PAD3;
148 u_int32_t isr4; PAD3;
149 u_int32_t isr5; PAD3;
150 u_int32_t isr6; PAD3;
151 u_int32_t isr7; PAD3;
152 u_int32_t tmr0; PAD3;
153 u_int32_t tmr1; PAD3;
154 u_int32_t tmr2; PAD3;
155 u_int32_t tmr3; PAD3;
156 u_int32_t tmr4; PAD3;
157 u_int32_t tmr5; PAD3;
158 u_int32_t tmr6; PAD3;
159 u_int32_t tmr7; PAD3;
160 u_int32_t irr0; PAD3;
161 u_int32_t irr1; PAD3;
162 u_int32_t irr2; PAD3;
163 u_int32_t irr3; PAD3;
164 u_int32_t irr4; PAD3;
165 u_int32_t irr5; PAD3;
166 u_int32_t irr6; PAD3;
167 u_int32_t irr7; PAD3;
175 u_int32_t lvt_cmci; PAD3;
176 u_int32_t icr_lo; PAD3;
177 u_int32_t icr_hi; PAD3;
178 u_int32_t lvt_timer; PAD3;
179 u_int32_t lvt_thermal; PAD3;
180 u_int32_t lvt_pcint; PAD3;
181 u_int32_t lvt_lint0; PAD3;
182 u_int32_t lvt_lint1; PAD3;
183 u_int32_t lvt_error; PAD3;
184 u_int32_t icr_timer; PAD3;
185 u_int32_t ccr_timer; PAD3;
190 u_int32_t dcr_timer; PAD3;
194 typedef struct LAPIC lapic_t;
196 enum LAPIC_REGISTERS {
204 LAPIC_DFR = 0xe, /* Not in x2APIC */
231 LAPIC_LVT_CMCI = 0x2f,
233 LAPIC_ICR_HI = 0x31, /* Not in x2APIC */
234 LAPIC_LVT_TIMER = 0x32,
235 LAPIC_LVT_THERMAL = 0x33,
236 LAPIC_LVT_PCINT = 0x34,
237 LAPIC_LVT_LINT0 = 0x35,
238 LAPIC_LVT_LINT1 = 0x36,
239 LAPIC_LVT_ERROR = 0x37,
240 LAPIC_ICR_TIMER = 0x38,
241 LAPIC_CCR_TIMER = 0x39,
242 LAPIC_DCR_TIMER = 0x3e,
243 LAPIC_SELF_IPI = 0x3f, /* Only in x2APIC */
247 * The LAPIC_SELF_IPI register only exists in x2APIC mode. The
248 * formula below is applicable only to reserve the memory region,
249 * i.e. for xAPIC mode, where LAPIC_SELF_IPI finely serves as the
250 * address past end of the region.
252 #define LAPIC_MEM_REGION (LAPIC_SELF_IPI * 0x10)
254 #define LAPIC_MEM_MUL 0x10
256 /******************************************************************************
261 u_int32_t ioregsel; PAD3;
262 u_int32_t iowin; PAD3;
265 typedef struct IOAPIC ioapic_t;
273 /******************************************************************************
274 * various code 'logical' values
277 /******************************************************************************
281 /* default physical locations of LOCAL (CPU) APICs */
282 #define DEFAULT_APIC_BASE 0xfee00000
284 /* constants relating to APIC ID registers */
285 #define APIC_ID_MASK 0xff000000
286 #define APIC_ID_SHIFT 24
287 #define APIC_ID_CLUSTER 0xf0
288 #define APIC_ID_CLUSTER_ID 0x0f
289 #define APIC_MAX_CLUSTER 0xe
290 #define APIC_MAX_INTRACLUSTER_ID 3
291 #define APIC_ID_CLUSTER_SHIFT 4
294 #define APIC_VER_VERSION 0x000000ff
295 #define APIC_VER_MAXLVT 0x00ff0000
296 #define MAXLVTSHIFT 16
297 #define APIC_VER_EOI_SUPPRESSION 0x01000000
300 #define APIC_LDR_RESERVED 0x00ffffff
303 #define APIC_DFR_RESERVED 0x0fffffff
304 #define APIC_DFR_MODEL_MASK 0xf0000000
305 #define APIC_DFR_MODEL_FLAT 0xf0000000
306 #define APIC_DFR_MODEL_CLUSTER 0x00000000
309 #define APIC_SVR_VECTOR 0x000000ff
310 #define APIC_SVR_VEC_PROG 0x000000f0
311 #define APIC_SVR_VEC_FIX 0x0000000f
312 #define APIC_SVR_ENABLE 0x00000100
313 # define APIC_SVR_SWDIS 0x00000000
314 # define APIC_SVR_SWEN 0x00000100
315 #define APIC_SVR_FOCUS 0x00000200
316 # define APIC_SVR_FEN 0x00000000
317 # define APIC_SVR_FDIS 0x00000200
318 #define APIC_SVR_EOI_SUPPRESSION 0x00001000
321 #define APIC_TPR_PRIO 0x000000ff
322 # define APIC_TPR_INT 0x000000f0
323 # define APIC_TPR_SUB 0x0000000f
326 #define APIC_ESR_SEND_CS_ERROR 0x00000001
327 #define APIC_ESR_RECEIVE_CS_ERROR 0x00000002
328 #define APIC_ESR_SEND_ACCEPT 0x00000004
329 #define APIC_ESR_RECEIVE_ACCEPT 0x00000008
330 #define APIC_ESR_SEND_ILLEGAL_VECTOR 0x00000020
331 #define APIC_ESR_RECEIVE_ILLEGAL_VECTOR 0x00000040
332 #define APIC_ESR_ILLEGAL_REGISTER 0x00000080
334 /* fields in ICR_LOW */
335 #define APIC_VECTOR_MASK 0x000000ff
337 #define APIC_DELMODE_MASK 0x00000700
338 # define APIC_DELMODE_FIXED 0x00000000
339 # define APIC_DELMODE_LOWPRIO 0x00000100
340 # define APIC_DELMODE_SMI 0x00000200
341 # define APIC_DELMODE_RR 0x00000300
342 # define APIC_DELMODE_NMI 0x00000400
343 # define APIC_DELMODE_INIT 0x00000500
344 # define APIC_DELMODE_STARTUP 0x00000600
345 # define APIC_DELMODE_RESV 0x00000700
347 #define APIC_DESTMODE_MASK 0x00000800
348 # define APIC_DESTMODE_PHY 0x00000000
349 # define APIC_DESTMODE_LOG 0x00000800
351 #define APIC_DELSTAT_MASK 0x00001000
352 # define APIC_DELSTAT_IDLE 0x00000000
353 # define APIC_DELSTAT_PEND 0x00001000
355 #define APIC_RESV1_MASK 0x00002000
357 #define APIC_LEVEL_MASK 0x00004000
358 # define APIC_LEVEL_DEASSERT 0x00000000
359 # define APIC_LEVEL_ASSERT 0x00004000
361 #define APIC_TRIGMOD_MASK 0x00008000
362 # define APIC_TRIGMOD_EDGE 0x00000000
363 # define APIC_TRIGMOD_LEVEL 0x00008000
365 #define APIC_RRSTAT_MASK 0x00030000
366 # define APIC_RRSTAT_INVALID 0x00000000
367 # define APIC_RRSTAT_INPROG 0x00010000
368 # define APIC_RRSTAT_VALID 0x00020000
369 # define APIC_RRSTAT_RESV 0x00030000
371 #define APIC_DEST_MASK 0x000c0000
372 # define APIC_DEST_DESTFLD 0x00000000
373 # define APIC_DEST_SELF 0x00040000
374 # define APIC_DEST_ALLISELF 0x00080000
375 # define APIC_DEST_ALLESELF 0x000c0000
377 #define APIC_RESV2_MASK 0xfff00000
379 #define APIC_ICRLO_RESV_MASK (APIC_RESV1_MASK | APIC_RESV2_MASK)
381 /* fields in LVT1/2 */
382 #define APIC_LVT_VECTOR 0x000000ff
383 #define APIC_LVT_DM 0x00000700
384 # define APIC_LVT_DM_FIXED 0x00000000
385 # define APIC_LVT_DM_SMI 0x00000200
386 # define APIC_LVT_DM_NMI 0x00000400
387 # define APIC_LVT_DM_INIT 0x00000500
388 # define APIC_LVT_DM_EXTINT 0x00000700
389 #define APIC_LVT_DS 0x00001000
390 #define APIC_LVT_IIPP 0x00002000
391 #define APIC_LVT_IIPP_INTALO 0x00002000
392 #define APIC_LVT_IIPP_INTAHI 0x00000000
393 #define APIC_LVT_RIRR 0x00004000
394 #define APIC_LVT_TM 0x00008000
395 #define APIC_LVT_M 0x00010000
398 /* fields in LVT Timer */
399 #define APIC_LVTT_VECTOR 0x000000ff
400 #define APIC_LVTT_DS 0x00001000
401 #define APIC_LVTT_M 0x00010000
402 #define APIC_LVTT_TM 0x00020000
403 # define APIC_LVTT_TM_ONE_SHOT 0x00000000
404 # define APIC_LVTT_TM_PERIODIC 0x00020000
407 /* APIC timer current count */
408 #define APIC_TIMER_MAX_COUNT 0xffffffff
411 #define APIC_TDCR_2 0x00
412 #define APIC_TDCR_4 0x01
413 #define APIC_TDCR_8 0x02
414 #define APIC_TDCR_16 0x03
415 #define APIC_TDCR_32 0x08
416 #define APIC_TDCR_64 0x09
417 #define APIC_TDCR_128 0x0a
418 #define APIC_TDCR_1 0x0b
420 /* LVT table indices */
421 #define APIC_LVT_LINT0 0
422 #define APIC_LVT_LINT1 1
423 #define APIC_LVT_TIMER 2
424 #define APIC_LVT_ERROR 3
425 #define APIC_LVT_PMC 4
426 #define APIC_LVT_THERMAL 5
427 #define APIC_LVT_CMCI 6
428 #define APIC_LVT_MAX APIC_LVT_CMCI
430 /******************************************************************************
434 /* default physical locations of an IO APIC */
435 #define DEFAULT_IO_APIC_BASE 0xfec00000
437 /* window register offset */
438 #define IOAPIC_WINDOW 0x10
439 #define IOAPIC_EOIR 0x40
441 /* indexes into IO APIC */
442 #define IOAPIC_ID 0x00
443 #define IOAPIC_VER 0x01
444 #define IOAPIC_ARB 0x02
445 #define IOAPIC_REDTBL 0x10
446 #define IOAPIC_REDTBL0 IOAPIC_REDTBL
447 #define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02)
448 #define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04)
449 #define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06)
450 #define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08)
451 #define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a)
452 #define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c)
453 #define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e)
454 #define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10)
455 #define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12)
456 #define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14)
457 #define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16)
458 #define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18)
459 #define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a)
460 #define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c)
461 #define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e)
462 #define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20)
463 #define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22)
464 #define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24)
465 #define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26)
466 #define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28)
467 #define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a)
468 #define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c)
469 #define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e)
472 #define IOART_VER_VERSION 0x000000ff
473 #define IOART_VER_MAXREDIR 0x00ff0000
474 #define MAXREDIRSHIFT 16
477 * fields in the IO APIC's redirection table entries
479 #define IOART_DEST APIC_ID_MASK /* broadcast addr: all APICs */
481 #define IOART_RESV 0x00fe0000 /* reserved */
483 #define IOART_INTMASK 0x00010000 /* R/W: INTerrupt mask */
484 # define IOART_INTMCLR 0x00000000 /* clear, allow INTs */
485 # define IOART_INTMSET 0x00010000 /* set, inhibit INTs */
487 #define IOART_TRGRMOD 0x00008000 /* R/W: trigger mode */
488 # define IOART_TRGREDG 0x00000000 /* edge */
489 # define IOART_TRGRLVL 0x00008000 /* level */
491 #define IOART_REM_IRR 0x00004000 /* RO: remote IRR */
493 #define IOART_INTPOL 0x00002000 /* R/W: INT input pin polarity */
494 # define IOART_INTAHI 0x00000000 /* active high */
495 # define IOART_INTALO 0x00002000 /* active low */
497 #define IOART_DELIVS 0x00001000 /* RO: delivery status */
499 #define IOART_DESTMOD 0x00000800 /* R/W: destination mode */
500 # define IOART_DESTPHY 0x00000000 /* physical */
501 # define IOART_DESTLOG 0x00000800 /* logical */
503 #define IOART_DELMOD 0x00000700 /* R/W: delivery mode */
504 # define IOART_DELFIXED 0x00000000 /* fixed */
505 # define IOART_DELLOPRI 0x00000100 /* lowest priority */
506 # define IOART_DELSMI 0x00000200 /* System Management INT */
507 # define IOART_DELRSV1 0x00000300 /* reserved */
508 # define IOART_DELNMI 0x00000400 /* NMI signal */
509 # define IOART_DELINIT 0x00000500 /* INIT signal */
510 # define IOART_DELRSV2 0x00000600 /* reserved */
511 # define IOART_DELEXINT 0x00000700 /* External INTerrupt */
513 #define IOART_INTVEC 0x000000ff /* R/W: INTerrupt vector field */
515 #endif /* _X86_APICREG_H_ */