2 * Copyright (c) 1996, by Peter Wemm and Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #ifndef _X86_APICREG_H_
29 #define _X86_APICREG_H_
32 * Local && I/O APIC definitions.
36 * Pentium P54C+ Built-in APIC
37 * (Advanced programmable Interrupt Controller)
39 * Base Address of Built-in APIC in memory location
42 * Map of APIC Registers:
44 * Offset (hex) Description Read/Write state
47 * 020 ID Local APIC ID R/W
48 * 030 VER Local APIC Version R
53 * 080 Task Priority Register R/W
54 * 090 Arbitration Priority Register R
55 * 0A0 Processor Priority Register R
57 * 0C0 RRR Remote read R
58 * 0D0 Logical Destination R/W
59 * 0E0 Destination Format Register 0..27 R; 28..31 R/W
60 * 0F0 SVR Spurious Interrupt Vector Reg. 0..3 R; 4..9 R/W
85 * 280 Error Status Register R
92 * 2F0 Local Vector Table (CMCI) R/W
93 * 300 ICR_LOW Interrupt Command Reg. (0-31) R/W
94 * 310 ICR_HI Interrupt Command Reg. (32-63) R/W
95 * 320 Local Vector Table (Timer) R/W
96 * 330 Local Vector Table (Thermal) R/W (PIV+)
97 * 340 Local Vector Table (Performance) R/W (P6+)
98 * 350 LVT1 Local Vector Table (LINT0) R/W
99 * 360 LVT2 Local Vector Table (LINT1) R/W
100 * 370 LVT3 Local Vector Table (ERROR) R/W
101 * 380 Initial Count Reg. for Timer R/W
102 * 390 Current Count of Timer R
107 * 3E0 Timer Divide Configuration Reg. R/W
112 /******************************************************************************
113 * global defines, etc.
117 /******************************************************************************
118 * LOCAL APIC structure
122 #include <sys/types.h>
124 #define PAD3 int : 32; int : 32; int : 32
125 #define PAD4 int : 32; int : 32; int : 32; int : 32
131 u_int32_t version; PAD3;
144 u_int32_t isr0; PAD3;
145 u_int32_t isr1; PAD3;
146 u_int32_t isr2; PAD3;
147 u_int32_t isr3; PAD3;
148 u_int32_t isr4; PAD3;
149 u_int32_t isr5; PAD3;
150 u_int32_t isr6; PAD3;
151 u_int32_t isr7; PAD3;
152 u_int32_t tmr0; PAD3;
153 u_int32_t tmr1; PAD3;
154 u_int32_t tmr2; PAD3;
155 u_int32_t tmr3; PAD3;
156 u_int32_t tmr4; PAD3;
157 u_int32_t tmr5; PAD3;
158 u_int32_t tmr6; PAD3;
159 u_int32_t tmr7; PAD3;
160 u_int32_t irr0; PAD3;
161 u_int32_t irr1; PAD3;
162 u_int32_t irr2; PAD3;
163 u_int32_t irr3; PAD3;
164 u_int32_t irr4; PAD3;
165 u_int32_t irr5; PAD3;
166 u_int32_t irr6; PAD3;
167 u_int32_t irr7; PAD3;
175 u_int32_t lvt_cmci; PAD3;
176 u_int32_t icr_lo; PAD3;
177 u_int32_t icr_hi; PAD3;
178 u_int32_t lvt_timer; PAD3;
179 u_int32_t lvt_thermal; PAD3;
180 u_int32_t lvt_pcint; PAD3;
181 u_int32_t lvt_lint0; PAD3;
182 u_int32_t lvt_lint1; PAD3;
183 u_int32_t lvt_error; PAD3;
184 u_int32_t icr_timer; PAD3;
185 u_int32_t ccr_timer; PAD3;
190 u_int32_t dcr_timer; PAD3;
194 typedef struct LAPIC lapic_t;
196 enum LAPIC_REGISTERS {
204 LAPIC_DFR = 0xe, /* Not in x2APIC */
231 LAPIC_LVT_CMCI = 0x2f,
233 LAPIC_ICR_HI = 0x31, /* Not in x2APIC */
234 LAPIC_LVT_TIMER = 0x32,
235 LAPIC_LVT_THERMAL = 0x33,
236 LAPIC_LVT_PCINT = 0x34,
237 LAPIC_LVT_LINT0 = 0x35,
238 LAPIC_LVT_LINT1 = 0x36,
239 LAPIC_LVT_ERROR = 0x37,
240 LAPIC_ICR_TIMER = 0x38,
241 LAPIC_CCR_TIMER = 0x39,
242 LAPIC_DCR_TIMER = 0x3e,
243 LAPIC_SELF_IPI = 0x3f, /* Only in x2APIC */
244 LAPIC_EXT_FEATURES = 0x40, /* AMD */
245 LAPIC_EXT_CTRL = 0x41, /* AMD */
246 LAPIC_EXT_SEOI = 0x42, /* AMD */
247 LAPIC_EXT_IER0 = 0x48, /* AMD */
248 LAPIC_EXT_IER1 = 0x49, /* AMD */
249 LAPIC_EXT_IER2 = 0x4a, /* AMD */
250 LAPIC_EXT_IER3 = 0x4b, /* AMD */
251 LAPIC_EXT_IER4 = 0x4c, /* AMD */
252 LAPIC_EXT_IER5 = 0x4d, /* AMD */
253 LAPIC_EXT_IER6 = 0x4e, /* AMD */
254 LAPIC_EXT_IER7 = 0x4f, /* AMD */
255 LAPIC_EXT_LVT0 = 0x50, /* AMD */
256 LAPIC_EXT_LVT1 = 0x51, /* AMD */
257 LAPIC_EXT_LVT2 = 0x52, /* AMD */
258 LAPIC_EXT_LVT3 = 0x53, /* AMD */
261 #define LAPIC_MEM_MUL 0x10
264 * Although some registers are available on AMD processors only,
265 * it's not a big waste to reserve them on all platforms.
266 * However, we need to watch out for this space being assigned for
267 * non-APIC purposes in the future processor models.
269 #define LAPIC_MEM_REGION ((LAPIC_EXT_LVT3 + 1) * LAPIC_MEM_MUL)
271 /******************************************************************************
276 u_int32_t ioregsel; PAD3;
277 u_int32_t iowin; PAD3;
280 typedef struct IOAPIC ioapic_t;
288 /******************************************************************************
289 * various code 'logical' values
292 /******************************************************************************
296 /* default physical locations of LOCAL (CPU) APICs */
297 #define DEFAULT_APIC_BASE 0xfee00000
299 /* constants relating to APIC ID registers */
300 #define APIC_ID_MASK 0xff000000
301 #define APIC_ID_SHIFT 24
302 #define APIC_ID_CLUSTER 0xf0
303 #define APIC_ID_CLUSTER_ID 0x0f
304 #define APIC_MAX_CLUSTER 0xe
305 #define APIC_MAX_INTRACLUSTER_ID 3
306 #define APIC_ID_CLUSTER_SHIFT 4
309 #define APIC_VER_VERSION 0x000000ff
310 #define APIC_VER_MAXLVT 0x00ff0000
311 #define MAXLVTSHIFT 16
312 #define APIC_VER_EOI_SUPPRESSION 0x01000000
313 #define APIC_VER_AMD_EXT_SPACE 0x80000000
316 #define APIC_LDR_RESERVED 0x00ffffff
319 #define APIC_DFR_RESERVED 0x0fffffff
320 #define APIC_DFR_MODEL_MASK 0xf0000000
321 #define APIC_DFR_MODEL_FLAT 0xf0000000
322 #define APIC_DFR_MODEL_CLUSTER 0x00000000
325 #define APIC_SVR_VECTOR 0x000000ff
326 #define APIC_SVR_VEC_PROG 0x000000f0
327 #define APIC_SVR_VEC_FIX 0x0000000f
328 #define APIC_SVR_ENABLE 0x00000100
329 # define APIC_SVR_SWDIS 0x00000000
330 # define APIC_SVR_SWEN 0x00000100
331 #define APIC_SVR_FOCUS 0x00000200
332 # define APIC_SVR_FEN 0x00000000
333 # define APIC_SVR_FDIS 0x00000200
334 #define APIC_SVR_EOI_SUPPRESSION 0x00001000
337 #define APIC_TPR_PRIO 0x000000ff
338 # define APIC_TPR_INT 0x000000f0
339 # define APIC_TPR_SUB 0x0000000f
342 #define APIC_ESR_SEND_CS_ERROR 0x00000001
343 #define APIC_ESR_RECEIVE_CS_ERROR 0x00000002
344 #define APIC_ESR_SEND_ACCEPT 0x00000004
345 #define APIC_ESR_RECEIVE_ACCEPT 0x00000008
346 #define APIC_ESR_SEND_ILLEGAL_VECTOR 0x00000020
347 #define APIC_ESR_RECEIVE_ILLEGAL_VECTOR 0x00000040
348 #define APIC_ESR_ILLEGAL_REGISTER 0x00000080
350 /* fields in ICR_LOW */
351 #define APIC_VECTOR_MASK 0x000000ff
353 #define APIC_DELMODE_MASK 0x00000700
354 # define APIC_DELMODE_FIXED 0x00000000
355 # define APIC_DELMODE_LOWPRIO 0x00000100
356 # define APIC_DELMODE_SMI 0x00000200
357 # define APIC_DELMODE_RR 0x00000300
358 # define APIC_DELMODE_NMI 0x00000400
359 # define APIC_DELMODE_INIT 0x00000500
360 # define APIC_DELMODE_STARTUP 0x00000600
361 # define APIC_DELMODE_RESV 0x00000700
363 #define APIC_DESTMODE_MASK 0x00000800
364 # define APIC_DESTMODE_PHY 0x00000000
365 # define APIC_DESTMODE_LOG 0x00000800
367 #define APIC_DELSTAT_MASK 0x00001000
368 # define APIC_DELSTAT_IDLE 0x00000000
369 # define APIC_DELSTAT_PEND 0x00001000
371 #define APIC_RESV1_MASK 0x00002000
373 #define APIC_LEVEL_MASK 0x00004000
374 # define APIC_LEVEL_DEASSERT 0x00000000
375 # define APIC_LEVEL_ASSERT 0x00004000
377 #define APIC_TRIGMOD_MASK 0x00008000
378 # define APIC_TRIGMOD_EDGE 0x00000000
379 # define APIC_TRIGMOD_LEVEL 0x00008000
381 #define APIC_RRSTAT_MASK 0x00030000
382 # define APIC_RRSTAT_INVALID 0x00000000
383 # define APIC_RRSTAT_INPROG 0x00010000
384 # define APIC_RRSTAT_VALID 0x00020000
385 # define APIC_RRSTAT_RESV 0x00030000
387 #define APIC_DEST_MASK 0x000c0000
388 # define APIC_DEST_DESTFLD 0x00000000
389 # define APIC_DEST_SELF 0x00040000
390 # define APIC_DEST_ALLISELF 0x00080000
391 # define APIC_DEST_ALLESELF 0x000c0000
393 #define APIC_RESV2_MASK 0xfff00000
395 #define APIC_ICRLO_RESV_MASK (APIC_RESV1_MASK | APIC_RESV2_MASK)
397 /* fields in LVT1/2 */
398 #define APIC_LVT_VECTOR 0x000000ff
399 #define APIC_LVT_DM 0x00000700
400 # define APIC_LVT_DM_FIXED 0x00000000
401 # define APIC_LVT_DM_SMI 0x00000200
402 # define APIC_LVT_DM_NMI 0x00000400
403 # define APIC_LVT_DM_INIT 0x00000500
404 # define APIC_LVT_DM_EXTINT 0x00000700
405 #define APIC_LVT_DS 0x00001000
406 #define APIC_LVT_IIPP 0x00002000
407 #define APIC_LVT_IIPP_INTALO 0x00002000
408 #define APIC_LVT_IIPP_INTAHI 0x00000000
409 #define APIC_LVT_RIRR 0x00004000
410 #define APIC_LVT_TM 0x00008000
411 #define APIC_LVT_M 0x00010000
414 /* fields in LVT Timer */
415 #define APIC_LVTT_VECTOR 0x000000ff
416 #define APIC_LVTT_DS 0x00001000
417 #define APIC_LVTT_M 0x00010000
418 #define APIC_LVTT_TM 0x00060000
419 # define APIC_LVTT_TM_ONE_SHOT 0x00000000
420 # define APIC_LVTT_TM_PERIODIC 0x00020000
421 # define APIC_LVTT_TM_TSCDLT 0x00040000
422 # define APIC_LVTT_TM_RSRV 0x00060000
424 /* APIC timer current count */
425 #define APIC_TIMER_MAX_COUNT 0xffffffff
428 #define APIC_TDCR_2 0x00
429 #define APIC_TDCR_4 0x01
430 #define APIC_TDCR_8 0x02
431 #define APIC_TDCR_16 0x03
432 #define APIC_TDCR_32 0x08
433 #define APIC_TDCR_64 0x09
434 #define APIC_TDCR_128 0x0a
435 #define APIC_TDCR_1 0x0b
437 /* Constants related to AMD Extended APIC Features Register */
438 #define APIC_EXTF_ELVT_MASK 0x00ff0000
439 #define APIC_EXTF_ELVT_SHIFT 16
440 #define APIC_EXTF_EXTID_CAP 0x00000004
441 #define APIC_EXTF_SEIO_CAP 0x00000002
442 #define APIC_EXTF_IER_CAP 0x00000001
444 /* LVT table indices */
445 #define APIC_LVT_LINT0 0
446 #define APIC_LVT_LINT1 1
447 #define APIC_LVT_TIMER 2
448 #define APIC_LVT_ERROR 3
449 #define APIC_LVT_PMC 4
450 #define APIC_LVT_THERMAL 5
451 #define APIC_LVT_CMCI 6
452 #define APIC_LVT_MAX APIC_LVT_CMCI
454 /* AMD extended LVT constants, seem to be assigned by fiat */
455 #define APIC_ELVT_IBS 0 /* Instruction based sampling */
456 #define APIC_ELVT_MCA 1 /* MCE thresholding */
457 #define APIC_ELVT_DEI 2 /* Deferred error interrupt */
458 #define APIC_ELVT_SBI 3 /* Sideband interface */
459 #define APIC_ELVT_MAX APIC_ELVT_SBI
461 /******************************************************************************
465 /* default physical locations of an IO APIC */
466 #define DEFAULT_IO_APIC_BASE 0xfec00000
468 /* window register offset */
469 #define IOAPIC_WINDOW 0x10
470 #define IOAPIC_EOIR 0x40
472 /* indexes into IO APIC */
473 #define IOAPIC_ID 0x00
474 #define IOAPIC_VER 0x01
475 #define IOAPIC_ARB 0x02
476 #define IOAPIC_REDTBL 0x10
477 #define IOAPIC_REDTBL0 IOAPIC_REDTBL
478 #define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02)
479 #define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04)
480 #define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06)
481 #define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08)
482 #define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a)
483 #define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c)
484 #define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e)
485 #define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10)
486 #define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12)
487 #define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14)
488 #define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16)
489 #define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18)
490 #define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a)
491 #define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c)
492 #define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e)
493 #define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20)
494 #define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22)
495 #define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24)
496 #define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26)
497 #define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28)
498 #define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a)
499 #define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c)
500 #define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e)
503 #define IOART_VER_VERSION 0x000000ff
504 #define IOART_VER_MAXREDIR 0x00ff0000
505 #define MAXREDIRSHIFT 16
508 * fields in the IO APIC's redirection table entries
510 #define IOART_DEST APIC_ID_MASK /* broadcast addr: all APICs */
512 #define IOART_RESV 0x00fe0000 /* reserved */
514 #define IOART_INTMASK 0x00010000 /* R/W: INTerrupt mask */
515 # define IOART_INTMCLR 0x00000000 /* clear, allow INTs */
516 # define IOART_INTMSET 0x00010000 /* set, inhibit INTs */
518 #define IOART_TRGRMOD 0x00008000 /* R/W: trigger mode */
519 # define IOART_TRGREDG 0x00000000 /* edge */
520 # define IOART_TRGRLVL 0x00008000 /* level */
522 #define IOART_REM_IRR 0x00004000 /* RO: remote IRR */
524 #define IOART_INTPOL 0x00002000 /* R/W: INT input pin polarity */
525 # define IOART_INTAHI 0x00000000 /* active high */
526 # define IOART_INTALO 0x00002000 /* active low */
528 #define IOART_DELIVS 0x00001000 /* RO: delivery status */
530 #define IOART_DESTMOD 0x00000800 /* R/W: destination mode */
531 # define IOART_DESTPHY 0x00000000 /* physical */
532 # define IOART_DESTLOG 0x00000800 /* logical */
534 #define IOART_DELMOD 0x00000700 /* R/W: delivery mode */
535 # define IOART_DELFIXED 0x00000000 /* fixed */
536 # define IOART_DELLOPRI 0x00000100 /* lowest priority */
537 # define IOART_DELSMI 0x00000200 /* System Management INT */
538 # define IOART_DELRSV1 0x00000300 /* reserved */
539 # define IOART_DELNMI 0x00000400 /* NMI signal */
540 # define IOART_DELINIT 0x00000500 /* INIT signal */
541 # define IOART_DELRSV2 0x00000600 /* reserved */
542 # define IOART_DELEXINT 0x00000700 /* External INTerrupt */
544 #define IOART_INTVEC 0x000000ff /* R/W: INTerrupt vector field */
546 #endif /* _X86_APICREG_H_ */