2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef _X86_APICVAR_H_
32 #define _X86_APICVAR_H_
35 * Local && I/O APIC variable definitions.
39 * Layout of local APIC interrupt vectors:
41 * 0xff (255) +-------------+
42 * | | 15 (Spurious / IPIs / Local Interrupts)
43 * 0xf0 (240) +-------------+
44 * | | 14 (I/O Interrupts / Timer)
45 * 0xe0 (224) +-------------+
46 * | | 13 (I/O Interrupts)
47 * 0xd0 (208) +-------------+
48 * | | 12 (I/O Interrupts)
49 * 0xc0 (192) +-------------+
50 * | | 11 (I/O Interrupts)
51 * 0xb0 (176) +-------------+
52 * | | 10 (I/O Interrupts)
53 * 0xa0 (160) +-------------+
54 * | | 9 (I/O Interrupts)
55 * 0x90 (144) +-------------+
56 * | | 8 (I/O Interrupts / System Calls)
57 * 0x80 (128) +-------------+
58 * | | 7 (I/O Interrupts)
59 * 0x70 (112) +-------------+
60 * | | 6 (I/O Interrupts)
61 * 0x60 (96) +-------------+
62 * | | 5 (I/O Interrupts)
63 * 0x50 (80) +-------------+
64 * | | 4 (I/O Interrupts)
65 * 0x40 (64) +-------------+
66 * | | 3 (I/O Interrupts)
67 * 0x30 (48) +-------------+
68 * | | 2 (ATPIC Interrupts)
69 * 0x20 (32) +-------------+
70 * | | 1 (Exceptions, traps, faults, etc.)
71 * 0x10 (16) +-------------+
72 * | | 0 (Exceptions, traps, faults, etc.)
73 * 0x00 (0) +-------------+
75 * Note: 0x80 needs to be handled specially and not allocated to an
79 #define xAPIC_MAX_APIC_ID 0xfe
80 #define xAPIC_ID_ALL 0xff
81 #define MAX_APIC_ID 0x200
82 #define APIC_ID_ALL 0xffffffff
84 #define IOAPIC_MAX_ID xAPIC_MAX_APIC_ID
86 /* I/O Interrupts are used for external devices such as ISA, PCI, etc. */
87 #define APIC_IO_INTS (IDT_IO_INTS + 16)
88 #define APIC_NUM_IOINTS 191
90 /* The timer interrupt is used for clock handling and drives hardclock, etc. */
91 #define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS)
94 ********************* !!! WARNING !!! ******************************
95 * Each local apic has an interrupt receive fifo that is two entries deep
96 * for each interrupt priority class (higher 4 bits of interrupt vector).
97 * Once the fifo is full the APIC can no longer receive interrupts for this
98 * class and sending IPIs from other CPUs will be blocked.
99 * To avoid deadlocks there should be no more than two IPI interrupts
100 * pending at the same time.
101 * Currently this is guaranteed by dividing the IPIs in two groups that have
102 * each at most one IPI interrupt pending. The first group is protected by the
103 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user
104 * at a time) The second group uses a single interrupt and a bitmap to avoid
105 * redundant IPI interrupts.
108 /* Interrupts for local APIC LVT entries other than the timer. */
109 #define APIC_LOCAL_INTS 240
110 #define APIC_ERROR_INT APIC_LOCAL_INTS
111 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1)
112 #define APIC_CMC_INT (APIC_LOCAL_INTS + 2)
113 #define APIC_IPI_INTS (APIC_LOCAL_INTS + 3)
115 #define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */
116 #define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */
117 #define IPI_INVLPG (APIC_IPI_INTS + 2)
118 #define IPI_INVLRNG (APIC_IPI_INTS + 3)
119 #define IPI_INVLCACHE (APIC_IPI_INTS + 4)
120 /* Vector to handle bitmap based IPIs */
121 #define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 5)
123 /* IPIs handled by IPI_BITMAP_VECTOR */
124 #define IPI_AST 0 /* Generate software trap. */
125 #define IPI_PREEMPT 1
126 #define IPI_HARDCLOCK 2
127 #define IPI_BITMAP_LAST IPI_HARDCLOCK
128 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST)
130 #define IPI_STOP (APIC_IPI_INTS + 6) /* Stop CPU until restarted. */
131 #define IPI_SUSPEND (APIC_IPI_INTS + 7) /* Suspend CPU until restarted. */
133 #define IPI_LAZYPMAP (APIC_IPI_INTS + 8) /* Lazy pmap release. */
134 #define IPI_DYN_FIRST (APIC_IPI_INTS + 9)
136 #define IPI_DYN_FIRST (APIC_IPI_INTS + 8)
138 #define IPI_DYN_LAST (253) /* IPIs allocated at runtime */
141 * IPI_STOP_HARD does not need to occupy a slot in the IPI vector space since
142 * it is delivered using an NMI anyways.
144 #define IPI_NMI_FIRST 254
145 #define IPI_TRACE 254 /* Interrupt for tracing. */
146 #define IPI_STOP_HARD 255 /* Stop CPU with a NMI. */
149 * The spurious interrupt can share the priority class with the IPIs since
150 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo)
152 #define APIC_SPURIOUS_INT 255
156 #define APIC_IPI_DEST_SELF -1
157 #define APIC_IPI_DEST_ALL -2
158 #define APIC_IPI_DEST_OTHERS -3
160 #define APIC_BUS_UNKNOWN -1
161 #define APIC_BUS_ISA 0
162 #define APIC_BUS_EISA 1
163 #define APIC_BUS_PCI 2
164 #define APIC_BUS_MAX APIC_BUS_PCI
166 #define IRQ_EXTINT (NUM_IO_INTS + 1)
167 #define IRQ_NMI (NUM_IO_INTS + 2)
168 #define IRQ_SMI (NUM_IO_INTS + 3)
169 #define IRQ_DISABLED (NUM_IO_INTS + 4)
172 * An APIC enumerator is a pseudo bus driver that enumerates APIC's including
173 * CPU's and I/O APIC's.
175 struct apic_enumerator {
176 const char *apic_name;
177 int (*apic_probe)(void);
178 int (*apic_probe_cpus)(void);
179 int (*apic_setup_local)(void);
180 int (*apic_setup_io)(void);
181 SLIST_ENTRY(apic_enumerator) apic_next;
185 IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3),
186 IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6),
187 IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint),
188 IDTVEC(spuriousint), IDTVEC(timerint),
189 IDTVEC(apic_isr1_pti), IDTVEC(apic_isr2_pti), IDTVEC(apic_isr3_pti),
190 IDTVEC(apic_isr4_pti), IDTVEC(apic_isr5_pti), IDTVEC(apic_isr6_pti),
191 IDTVEC(apic_isr7_pti), IDTVEC(cmcint_pti), IDTVEC(errorint_pti),
192 IDTVEC(spuriousint_pti), IDTVEC(timerint_pti);
194 extern vm_paddr_t lapic_paddr;
195 extern int *apic_cpuids;
197 void apic_register_enumerator(struct apic_enumerator *enumerator);
198 void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase);
199 int ioapic_disable_pin(void *cookie, u_int pin);
200 int ioapic_get_vector(void *cookie, u_int pin);
201 void ioapic_register(void *cookie);
202 int ioapic_remap_vector(void *cookie, u_int pin, int vector);
203 int ioapic_set_bus(void *cookie, u_int pin, int bus_type);
204 int ioapic_set_extint(void *cookie, u_int pin);
205 int ioapic_set_nmi(void *cookie, u_int pin);
206 int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol);
207 int ioapic_set_triggermode(void *cookie, u_int pin,
208 enum intr_trigger trigger);
209 int ioapic_set_smi(void *cookie, u_int pin);
212 * Struct containing pointers to APIC functions whose
213 * implementation is run time selectable.
216 void (*create)(u_int, int);
217 void (*init)(vm_paddr_t);
218 void (*xapic_mode)(void);
219 bool (*is_x2apic)(void);
221 void (*dump)(const char *);
222 void (*disable)(void);
225 int (*intr_pending)(u_int);
226 void (*set_logical_id)(u_int, u_int, u_int);
227 u_int (*cpuid)(u_int);
230 u_int (*alloc_vector)(u_int, u_int);
231 u_int (*alloc_vectors)(u_int, u_int *, u_int, u_int);
232 void (*enable_vector)(u_int, u_int);
233 void (*disable_vector)(u_int, u_int);
234 void (*free_vector)(u_int, u_int, u_int);
238 int (*enable_pmc)(void);
239 void (*disable_pmc)(void);
240 void (*reenable_pmc)(void);
243 void (*enable_cmc)(void);
246 int (*enable_mca_elvt)(void);
249 void (*ipi_raw)(register_t, u_int);
250 void (*ipi_vectored)(u_int, int);
251 int (*ipi_wait)(int);
252 int (*ipi_alloc)(inthand_t *ipifunc);
253 void (*ipi_free)(int vector);
256 int (*set_lvt_mask)(u_int, u_int, u_char);
257 int (*set_lvt_mode)(u_int, u_int, u_int32_t);
258 int (*set_lvt_polarity)(u_int, u_int, enum intr_polarity);
259 int (*set_lvt_triggermode)(u_int, u_int, enum intr_trigger);
262 extern struct apic_ops apic_ops;
265 lapic_create(u_int apic_id, int boot_cpu)
268 apic_ops.create(apic_id, boot_cpu);
272 lapic_init(vm_paddr_t addr)
279 lapic_xapic_mode(void)
282 apic_ops.xapic_mode();
286 lapic_is_x2apic(void)
289 return (apic_ops.is_x2apic());
293 lapic_setup(int boot)
296 apic_ops.setup(boot);
300 lapic_dump(const char *str)
324 return (apic_ops.id());
328 lapic_intr_pending(u_int vector)
331 return (apic_ops.intr_pending(vector));
336 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
339 apic_ops.set_logical_id(apic_id, cluster, cluster_id);
343 apic_cpuid(u_int apic_id)
346 return (apic_ops.cpuid(apic_id));
350 apic_alloc_vector(u_int apic_id, u_int irq)
353 return (apic_ops.alloc_vector(apic_id, irq));
357 apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align)
360 return (apic_ops.alloc_vectors(apic_id, irqs, count, align));
364 apic_enable_vector(u_int apic_id, u_int vector)
367 apic_ops.enable_vector(apic_id, vector);
371 apic_disable_vector(u_int apic_id, u_int vector)
374 apic_ops.disable_vector(apic_id, vector);
378 apic_free_vector(u_int apic_id, u_int vector, u_int irq)
381 apic_ops.free_vector(apic_id, vector, irq);
385 lapic_enable_pmc(void)
388 return (apic_ops.enable_pmc());
392 lapic_disable_pmc(void)
395 apic_ops.disable_pmc();
399 lapic_reenable_pmc(void)
402 apic_ops.reenable_pmc();
406 lapic_enable_cmc(void)
409 apic_ops.enable_cmc();
413 lapic_enable_mca_elvt(void)
416 return (apic_ops.enable_mca_elvt());
420 lapic_ipi_raw(register_t icrlo, u_int dest)
423 apic_ops.ipi_raw(icrlo, dest);
427 lapic_ipi_vectored(u_int vector, int dest)
430 apic_ops.ipi_vectored(vector, dest);
434 lapic_ipi_wait(int delay)
437 return (apic_ops.ipi_wait(delay));
441 lapic_ipi_alloc(inthand_t *ipifunc)
444 return (apic_ops.ipi_alloc(ipifunc));
448 lapic_ipi_free(int vector)
451 return (apic_ops.ipi_free(vector));
455 lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked)
458 return (apic_ops.set_lvt_mask(apic_id, lvt, masked));
462 lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode)
465 return (apic_ops.set_lvt_mode(apic_id, lvt, mode));
469 lapic_set_lvt_polarity(u_int apic_id, u_int lvt, enum intr_polarity pol)
472 return (apic_ops.set_lvt_polarity(apic_id, lvt, pol));
476 lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, enum intr_trigger trigger)
479 return (apic_ops.set_lvt_triggermode(apic_id, lvt, trigger));
482 void lapic_handle_cmc(void);
483 void lapic_handle_error(void);
484 void lapic_handle_intr(int vector, struct trapframe *frame);
485 void lapic_handle_timer(struct trapframe *frame);
487 int ioapic_get_rid(u_int apic_id, uint16_t *ridp);
489 extern int x2apic_mode;
490 extern int lapic_eoi_suppression;
492 #ifdef _SYS_SYSCTL_H_
493 SYSCTL_DECL(_hw_apic);
497 #endif /* _X86_APICVAR_H_ */