2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef _X86_APICVAR_H_
31 #define _X86_APICVAR_H_
34 * Local && I/O APIC variable definitions.
38 * Layout of local APIC interrupt vectors:
40 * 0xff (255) +-------------+
41 * | | 15 (Spurious / IPIs / Local Interrupts)
42 * 0xf0 (240) +-------------+
43 * | | 14 (I/O Interrupts / Timer)
44 * 0xe0 (224) +-------------+
45 * | | 13 (I/O Interrupts)
46 * 0xd0 (208) +-------------+
47 * | | 12 (I/O Interrupts)
48 * 0xc0 (192) +-------------+
49 * | | 11 (I/O Interrupts)
50 * 0xb0 (176) +-------------+
51 * | | 10 (I/O Interrupts)
52 * 0xa0 (160) +-------------+
53 * | | 9 (I/O Interrupts)
54 * 0x90 (144) +-------------+
55 * | | 8 (I/O Interrupts / System Calls)
56 * 0x80 (128) +-------------+
57 * | | 7 (I/O Interrupts)
58 * 0x70 (112) +-------------+
59 * | | 6 (I/O Interrupts)
60 * 0x60 (96) +-------------+
61 * | | 5 (I/O Interrupts)
62 * 0x50 (80) +-------------+
63 * | | 4 (I/O Interrupts)
64 * 0x40 (64) +-------------+
65 * | | 3 (I/O Interrupts)
66 * 0x30 (48) +-------------+
67 * | | 2 (ATPIC Interrupts)
68 * 0x20 (32) +-------------+
69 * | | 1 (Exceptions, traps, faults, etc.)
70 * 0x10 (16) +-------------+
71 * | | 0 (Exceptions, traps, faults, etc.)
72 * 0x00 (0) +-------------+
74 * Note: 0x80 needs to be handled specially and not allocated to an
78 #define xAPIC_MAX_APIC_ID 0xfe
79 #define xAPIC_ID_ALL 0xff
80 #define MAX_APIC_ID 0x200
81 #define APIC_ID_ALL 0xffffffff
83 #define IOAPIC_MAX_ID xAPIC_MAX_APIC_ID
85 /* I/O Interrupts are used for external devices such as ISA, PCI, etc. */
86 #define APIC_IO_INTS (IDT_IO_INTS + 16)
87 #define APIC_NUM_IOINTS 191
89 /* The timer interrupt is used for clock handling and drives hardclock, etc. */
90 #define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS)
93 ********************* !!! WARNING !!! ******************************
94 * Each local apic has an interrupt receive fifo that is two entries deep
95 * for each interrupt priority class (higher 4 bits of interrupt vector).
96 * Once the fifo is full the APIC can no longer receive interrupts for this
97 * class and sending IPIs from other CPUs will be blocked.
98 * To avoid deadlocks there should be no more than two IPI interrupts
99 * pending at the same time.
100 * Currently this is guaranteed by dividing the IPIs in two groups that have
101 * each at most one IPI interrupt pending. The first group is protected by the
102 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user
103 * at a time) The second group uses a single interrupt and a bitmap to avoid
104 * redundant IPI interrupts.
107 /* Interrupts for local APIC LVT entries other than the timer. */
108 #define APIC_LOCAL_INTS 240
109 #define APIC_ERROR_INT APIC_LOCAL_INTS
110 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1)
111 #define APIC_CMC_INT (APIC_LOCAL_INTS + 2)
112 #define APIC_IPI_INTS (APIC_LOCAL_INTS + 3)
114 #define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */
115 #define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */
116 #define IPI_INVLPG (APIC_IPI_INTS + 2)
117 #define IPI_INVLRNG (APIC_IPI_INTS + 3)
118 #define IPI_INVLCACHE (APIC_IPI_INTS + 4)
119 /* Vector to handle bitmap based IPIs */
120 #define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 5)
122 /* IPIs handled by IPI_BITMAP_VECTOR */
123 #define IPI_AST 0 /* Generate software trap. */
124 #define IPI_PREEMPT 1
125 #define IPI_HARDCLOCK 2
126 #define IPI_BITMAP_LAST IPI_HARDCLOCK
127 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST)
129 #define IPI_STOP (APIC_IPI_INTS + 6) /* Stop CPU until restarted. */
130 #define IPI_SUSPEND (APIC_IPI_INTS + 7) /* Suspend CPU until restarted. */
131 #define IPI_DYN_FIRST (APIC_IPI_INTS + 8)
132 #define IPI_DYN_LAST (253) /* IPIs allocated at runtime */
135 * IPI_STOP_HARD does not need to occupy a slot in the IPI vector space since
136 * it is delivered using an NMI anyways.
138 #define IPI_NMI_FIRST 254
139 #define IPI_TRACE 254 /* Interrupt for tracing. */
140 #define IPI_STOP_HARD 255 /* Stop CPU with a NMI. */
143 * The spurious interrupt can share the priority class with the IPIs since
144 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo)
146 #define APIC_SPURIOUS_INT 255
150 #define APIC_IPI_DEST_SELF -1
151 #define APIC_IPI_DEST_ALL -2
152 #define APIC_IPI_DEST_OTHERS -3
154 #define APIC_BUS_UNKNOWN -1
155 #define APIC_BUS_ISA 0
156 #define APIC_BUS_EISA 1
157 #define APIC_BUS_PCI 2
158 #define APIC_BUS_MAX APIC_BUS_PCI
160 #define IRQ_EXTINT -1
163 #define IRQ_DISABLED -4
166 * An APIC enumerator is a pseudo bus driver that enumerates APIC's including
167 * CPU's and I/O APIC's.
169 struct apic_enumerator {
170 const char *apic_name;
171 int (*apic_probe)(void);
172 int (*apic_probe_cpus)(void);
173 int (*apic_setup_local)(void);
174 int (*apic_setup_io)(void);
175 SLIST_ENTRY(apic_enumerator) apic_next;
179 IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3),
180 IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6),
181 IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint),
182 IDTVEC(spuriousint), IDTVEC(timerint),
183 IDTVEC(apic_isr1_pti), IDTVEC(apic_isr2_pti), IDTVEC(apic_isr3_pti),
184 IDTVEC(apic_isr4_pti), IDTVEC(apic_isr5_pti), IDTVEC(apic_isr6_pti),
185 IDTVEC(apic_isr7_pti), IDTVEC(cmcint_pti), IDTVEC(errorint_pti),
186 IDTVEC(spuriousint_pti), IDTVEC(timerint_pti);
188 extern vm_paddr_t lapic_paddr;
189 extern int *apic_cpuids;
191 void apic_register_enumerator(struct apic_enumerator *enumerator);
192 void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase);
193 int ioapic_disable_pin(void *cookie, u_int pin);
194 int ioapic_get_vector(void *cookie, u_int pin);
195 void ioapic_register(void *cookie);
196 int ioapic_remap_vector(void *cookie, u_int pin, int vector);
197 int ioapic_set_bus(void *cookie, u_int pin, int bus_type);
198 int ioapic_set_extint(void *cookie, u_int pin);
199 int ioapic_set_nmi(void *cookie, u_int pin);
200 int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol);
201 int ioapic_set_triggermode(void *cookie, u_int pin,
202 enum intr_trigger trigger);
203 int ioapic_set_smi(void *cookie, u_int pin);
206 * Struct containing pointers to APIC functions whose
207 * implementation is run time selectable.
210 void (*create)(u_int, int);
211 void (*init)(vm_paddr_t);
212 void (*xapic_mode)(void);
213 bool (*is_x2apic)(void);
215 void (*dump)(const char *);
216 void (*disable)(void);
219 int (*intr_pending)(u_int);
220 void (*set_logical_id)(u_int, u_int, u_int);
221 u_int (*cpuid)(u_int);
224 u_int (*alloc_vector)(u_int, u_int);
225 u_int (*alloc_vectors)(u_int, u_int *, u_int, u_int);
226 void (*enable_vector)(u_int, u_int);
227 void (*disable_vector)(u_int, u_int);
228 void (*free_vector)(u_int, u_int, u_int);
232 int (*enable_pmc)(void);
233 void (*disable_pmc)(void);
234 void (*reenable_pmc)(void);
237 void (*enable_cmc)(void);
240 int (*enable_mca_elvt)(void);
243 void (*ipi_raw)(register_t, u_int);
244 void (*ipi_vectored)(u_int, int);
245 int (*ipi_wait)(int);
246 int (*ipi_alloc)(inthand_t *ipifunc);
247 void (*ipi_free)(int vector);
250 int (*set_lvt_mask)(u_int, u_int, u_char);
251 int (*set_lvt_mode)(u_int, u_int, u_int32_t);
252 int (*set_lvt_polarity)(u_int, u_int, enum intr_polarity);
253 int (*set_lvt_triggermode)(u_int, u_int, enum intr_trigger);
256 extern struct apic_ops apic_ops;
259 lapic_create(u_int apic_id, int boot_cpu)
262 apic_ops.create(apic_id, boot_cpu);
266 lapic_init(vm_paddr_t addr)
273 lapic_xapic_mode(void)
276 apic_ops.xapic_mode();
280 lapic_is_x2apic(void)
283 return (apic_ops.is_x2apic());
287 lapic_setup(int boot)
290 apic_ops.setup(boot);
294 lapic_dump(const char *str)
318 return (apic_ops.id());
322 lapic_intr_pending(u_int vector)
325 return (apic_ops.intr_pending(vector));
330 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
333 apic_ops.set_logical_id(apic_id, cluster, cluster_id);
337 apic_cpuid(u_int apic_id)
340 return (apic_ops.cpuid(apic_id));
344 apic_alloc_vector(u_int apic_id, u_int irq)
347 return (apic_ops.alloc_vector(apic_id, irq));
351 apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align)
354 return (apic_ops.alloc_vectors(apic_id, irqs, count, align));
358 apic_enable_vector(u_int apic_id, u_int vector)
361 apic_ops.enable_vector(apic_id, vector);
365 apic_disable_vector(u_int apic_id, u_int vector)
368 apic_ops.disable_vector(apic_id, vector);
372 apic_free_vector(u_int apic_id, u_int vector, u_int irq)
375 apic_ops.free_vector(apic_id, vector, irq);
379 lapic_enable_pmc(void)
382 return (apic_ops.enable_pmc());
386 lapic_disable_pmc(void)
389 apic_ops.disable_pmc();
393 lapic_reenable_pmc(void)
396 apic_ops.reenable_pmc();
400 lapic_enable_cmc(void)
403 apic_ops.enable_cmc();
407 lapic_enable_mca_elvt(void)
410 return (apic_ops.enable_mca_elvt());
414 lapic_ipi_raw(register_t icrlo, u_int dest)
417 apic_ops.ipi_raw(icrlo, dest);
421 lapic_ipi_vectored(u_int vector, int dest)
424 apic_ops.ipi_vectored(vector, dest);
428 lapic_ipi_wait(int delay)
431 return (apic_ops.ipi_wait(delay));
435 lapic_ipi_alloc(inthand_t *ipifunc)
438 return (apic_ops.ipi_alloc(ipifunc));
442 lapic_ipi_free(int vector)
445 return (apic_ops.ipi_free(vector));
449 lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked)
452 return (apic_ops.set_lvt_mask(apic_id, lvt, masked));
456 lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode)
459 return (apic_ops.set_lvt_mode(apic_id, lvt, mode));
463 lapic_set_lvt_polarity(u_int apic_id, u_int lvt, enum intr_polarity pol)
466 return (apic_ops.set_lvt_polarity(apic_id, lvt, pol));
470 lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, enum intr_trigger trigger)
473 return (apic_ops.set_lvt_triggermode(apic_id, lvt, trigger));
476 void lapic_handle_cmc(void);
477 void lapic_handle_error(void);
478 void lapic_handle_intr(int vector, struct trapframe *frame);
479 void lapic_handle_timer(struct trapframe *frame);
481 int ioapic_get_rid(u_int apic_id, uint16_t *ridp);
483 extern int x2apic_mode;
484 extern int lapic_eoi_suppression;
486 #ifdef _SYS_SYSCTL_H_
487 SYSCTL_DECL(_hw_apic);
491 #endif /* _X86_APICVAR_H_ */