2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef __X86_INTR_MACHDEP_H__
31 #define __X86_INTR_MACHDEP_H__
36 * Values used in determining the allocation of IRQ values among
37 * different types of I/O interrupts. These values are used as
38 * indices into a interrupt source array to map I/O interrupts to a
39 * device interrupt source whether it be a pin on an interrupt
40 * controller or an MSI interrupt. The 16 ISA IRQs are assigned fixed
41 * IDT vectors, but all other device interrupts allocate IDT vectors
42 * on demand. Currently we have 191 IDT vectors available for device
43 * interrupts on each CPU. On many systems with I/O APICs, a lot of
44 * the IRQs are not used, so the total number of IRQ values reserved
45 * can exceed the number of available IDT slots.
47 * The first 16 IRQs (0 - 15) are reserved for ISA IRQs. Interrupt
48 * pins on I/O APICs for non-ISA interrupts use IRQ values starting at
49 * IRQ 17. This layout matches the GSI numbering used by ACPI so that
50 * IRQ values returned by ACPI methods such as _CRS can be used
51 * directly by the ACPI bus driver.
53 * MSI interrupts allocate a block of interrupts starting at the end
54 * of the I/O APIC range. When running under the Xen Hypervisor, an
55 * additional range of IRQ values are available for binding to event
58 extern u_int first_msi_irq;
59 extern u_int num_io_irqs;
60 extern u_int num_msi_irqs;
63 * Default base address for MSI messages on x86 platforms.
65 #define MSI_INTEL_ADDR_BASE 0xfee00000
69 typedef void inthand_t(void);
71 #define IDTVEC(name) __CONCAT(X,name)
76 * Methods that a PIC provides to mask/unmask a given interrupt source,
77 * "turn on" the interrupt on the CPU side by setting up an IDT entry, and
78 * return the vector associated with this source.
81 void (*pic_register_sources)(struct pic *);
82 void (*pic_enable_source)(struct intsrc *);
83 void (*pic_disable_source)(struct intsrc *, int);
84 void (*pic_eoi_source)(struct intsrc *);
85 void (*pic_enable_intr)(struct intsrc *);
86 void (*pic_disable_intr)(struct intsrc *);
87 int (*pic_vector)(struct intsrc *);
88 int (*pic_source_pending)(struct intsrc *);
89 void (*pic_suspend)(struct pic *);
90 void (*pic_resume)(struct pic *, bool suspend_cancelled);
91 int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
93 int (*pic_assign_cpu)(struct intsrc *, u_int apic_id);
94 void (*pic_reprogram_pin)(struct intsrc *);
95 TAILQ_ENTRY(pic) pics;
98 /* Flags for pic_disable_source() */
105 * An interrupt source. The upper-layer code uses the PIC methods to
106 * control a given source. The lower-layer PIC drivers can store additional
107 * private data in a given interrupt source such as an interrupt pin number
108 * or an I/O APIC pointer.
112 struct intr_event *is_event;
114 u_long *is_straycount;
124 extern cpuset_t intr_cpus;
126 extern struct mtx icu_lock;
127 extern int elcr_found;
129 extern int msix_disable_migration;
133 void atpic_reset(void);
135 /* XXX: The elcr_* prototypes probably belong somewhere else. */
136 int elcr_probe(void);
137 enum intr_trigger elcr_read_trigger(u_int irq);
138 void elcr_resume(void);
139 void elcr_write_trigger(u_int irq, enum intr_trigger trigger);
141 void intr_add_cpu(u_int cpu);
143 int intr_add_handler(const char *name, int vector, driver_filter_t filter,
144 driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep,
147 int intr_bind(u_int vector, u_char cpu);
149 int intr_config_intr(int vector, enum intr_trigger trig,
150 enum intr_polarity pol);
151 int intr_describe(u_int vector, void *ih, const char *descr);
152 void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame);
153 u_int intr_next_cpu(int domain);
154 struct intsrc *intr_lookup_source(int vector);
155 int intr_register_pic(struct pic *pic);
156 int intr_register_source(struct intsrc *isrc);
157 int intr_remove_handler(void *cookie);
158 void intr_resume(bool suspend_cancelled);
159 void intr_suspend(void);
160 void intr_reprogram(void);
161 void intrcnt_add(const char *name, u_long **countp);
162 void nexus_add_irq(u_long irq);
163 int msi_alloc(device_t dev, int count, int maxcount, int *irqs);
165 int msi_map(int irq, uint64_t *addr, uint32_t *data);
166 int msi_release(int *irqs, int count);
167 int msix_alloc(device_t dev, int *irq);
168 int msix_release(int irq);
170 void xen_intr_alloc_irqs(void);
175 #endif /* !__X86_INTR_MACHDEP_H__ */