2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #ifndef __X86_INTR_MACHDEP_H__
29 #define __X86_INTR_MACHDEP_H__
34 * Values used in determining the allocation of IRQ values among
35 * different types of I/O interrupts. These values are used as
36 * indices into a interrupt source array to map I/O interrupts to a
37 * device interrupt source whether it be a pin on an interrupt
38 * controller or an MSI interrupt. The 16 ISA IRQs are assigned fixed
39 * IDT vectors, but all other device interrupts allocate IDT vectors
40 * on demand. Currently we have 191 IDT vectors available for device
41 * interrupts on each CPU. On many systems with I/O APICs, a lot of
42 * the IRQs are not used, so the total number of IRQ values reserved
43 * can exceed the number of available IDT slots.
45 * The first 16 IRQs (0 - 15) are reserved for ISA IRQs. Interrupt
46 * pins on I/O APICs for non-ISA interrupts use IRQ values starting at
47 * IRQ 17. This layout matches the GSI numbering used by ACPI so that
48 * IRQ values returned by ACPI methods such as _CRS can be used
49 * directly by the ACPI bus driver.
51 * MSI interrupts allocate a block of interrupts starting at the end
52 * of the I/O APIC range. When running under the Xen Hypervisor, an
53 * additional range of IRQ values are available for binding to event
56 extern u_int first_msi_irq;
57 extern u_int num_io_irqs;
58 extern u_int num_msi_irqs;
61 * Default base address for MSI messages on x86 platforms.
63 #define MSI_INTEL_ADDR_BASE 0xfee00000
67 typedef void inthand_t(void);
69 #define IDTVEC(name) __CONCAT(X,name)
74 * Methods that a PIC provides to mask/unmask a given interrupt source,
75 * "turn on" the interrupt on the CPU side by setting up an IDT entry, and
76 * return the vector associated with this source.
79 void (*pic_register_sources)(struct pic *);
80 void (*pic_enable_source)(struct intsrc *);
81 void (*pic_disable_source)(struct intsrc *, int);
82 void (*pic_eoi_source)(struct intsrc *);
83 void (*pic_enable_intr)(struct intsrc *);
84 void (*pic_disable_intr)(struct intsrc *);
85 int (*pic_vector)(struct intsrc *);
86 int (*pic_source_pending)(struct intsrc *);
87 void (*pic_suspend)(struct pic *);
88 void (*pic_resume)(struct pic *, bool suspend_cancelled);
89 int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
91 int (*pic_assign_cpu)(struct intsrc *, u_int apic_id);
92 void (*pic_reprogram_pin)(struct intsrc *);
93 TAILQ_ENTRY(pic) pics;
96 /* Flags for pic_disable_source() */
103 * An interrupt source. The upper-layer code uses the PIC methods to
104 * control a given source. The lower-layer PIC drivers can store additional
105 * private data in a given interrupt source such as an interrupt pin number
106 * or an I/O APIC pointer.
110 struct intr_event *is_event;
112 u_long *is_straycount;
122 extern cpuset_t intr_cpus;
124 extern struct mtx icu_lock;
125 extern int elcr_found;
127 extern int msix_disable_migration;
131 void atpic_reset(void);
133 /* XXX: The elcr_* prototypes probably belong somewhere else. */
134 int elcr_probe(void);
135 enum intr_trigger elcr_read_trigger(u_int irq);
136 void elcr_resume(void);
137 void elcr_write_trigger(u_int irq, enum intr_trigger trigger);
139 void intr_add_cpu(u_int cpu);
141 int intr_add_handler(const char *name, int vector, driver_filter_t filter,
142 driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep,
144 int intr_config_intr(int vector, enum intr_trigger trig,
145 enum intr_polarity pol);
146 int intr_describe(u_int vector, void *ih, const char *descr);
147 void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame);
148 u_int intr_next_cpu(int domain);
149 struct intsrc *intr_lookup_source(int vector);
150 int intr_register_pic(struct pic *pic);
151 int intr_register_source(struct intsrc *isrc);
152 int intr_remove_handler(void *cookie);
153 void intr_resume(bool suspend_cancelled);
154 void intr_suspend(void);
155 void intr_reprogram(void);
156 void intrcnt_add(const char *name, u_long **countp);
157 void nexus_add_irq(u_long irq);
158 int msi_alloc(device_t dev, int count, int maxcount, int *irqs);
160 int msi_map(int irq, uint64_t *addr, uint32_t *data);
161 int msi_release(int *irqs, int count);
162 int msix_alloc(device_t dev, int *irq);
163 int msix_release(int irq);
165 void xen_intr_alloc_irqs(void);
170 #endif /* !__X86_INTR_MACHDEP_H__ */