2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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29 #ifndef __X86_INTR_MACHDEP_H__
30 #define __X86_INTR_MACHDEP_H__
35 * Values used in determining the allocation of IRQ values among
36 * different types of I/O interrupts. These values are used as
37 * indices into a interrupt source array to map I/O interrupts to a
38 * device interrupt source whether it be a pin on an interrupt
39 * controller or an MSI interrupt. The 16 ISA IRQs are assigned fixed
40 * IDT vectors, but all other device interrupts allocate IDT vectors
41 * on demand. Currently we have 191 IDT vectors available for device
42 * interrupts on each CPU. On many systems with I/O APICs, a lot of
43 * the IRQs are not used, so the total number of IRQ values reserved
44 * can exceed the number of available IDT slots.
46 * The first 16 IRQs (0 - 15) are reserved for ISA IRQs. Interrupt
47 * pins on I/O APICs for non-ISA interrupts use IRQ values starting at
48 * IRQ 17. This layout matches the GSI numbering used by ACPI so that
49 * IRQ values returned by ACPI methods such as _CRS can be used
50 * directly by the ACPI bus driver.
52 * MSI interrupts allocate a block of interrupts starting at either
53 * the end of the I/O APIC range or 256, whichever is higher. When
54 * running under the Xen Hypervisor, an additional range of IRQ values
55 * are available for binding to event channel events. We use 256 as
56 * the minimum IRQ value for MSI interrupts to attempt to leave 255
57 * unused since 255 is used in PCI to indicate an invalid INTx IRQ.
59 #define NUM_MSI_INTS 512
60 #define MINIMUM_MSI_INT 256
62 extern u_int first_msi_irq;
63 extern u_int num_io_irqs;
66 * Default base address for MSI messages on x86 platforms.
68 #define MSI_INTEL_ADDR_BASE 0xfee00000
72 typedef void inthand_t(void);
74 #define IDTVEC(name) __CONCAT(X,name)
79 * Methods that a PIC provides to mask/unmask a given interrupt source,
80 * "turn on" the interrupt on the CPU side by setting up an IDT entry, and
81 * return the vector associated with this source.
84 void (*pic_register_sources)(struct pic *);
85 void (*pic_enable_source)(struct intsrc *);
86 void (*pic_disable_source)(struct intsrc *, int);
87 void (*pic_eoi_source)(struct intsrc *);
88 void (*pic_enable_intr)(struct intsrc *);
89 void (*pic_disable_intr)(struct intsrc *);
90 int (*pic_vector)(struct intsrc *);
91 int (*pic_source_pending)(struct intsrc *);
92 void (*pic_suspend)(struct pic *);
93 void (*pic_resume)(struct pic *, bool suspend_cancelled);
94 int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
96 int (*pic_assign_cpu)(struct intsrc *, u_int apic_id);
97 void (*pic_reprogram_pin)(struct intsrc *);
98 TAILQ_ENTRY(pic) pics;
101 /* Flags for pic_disable_source() */
108 * An interrupt source. The upper-layer code uses the PIC methods to
109 * control a given source. The lower-layer PIC drivers can store additional
110 * private data in a given interrupt source such as an interrupt pin number
111 * or an I/O APIC pointer.
115 struct intr_event *is_event;
117 u_long *is_straycount;
125 extern cpuset_t intr_cpus;
127 extern struct mtx icu_lock;
128 extern int elcr_found;
130 extern int msix_disable_migration;
134 void atpic_reset(void);
136 /* XXX: The elcr_* prototypes probably belong somewhere else. */
137 int elcr_probe(void);
138 enum intr_trigger elcr_read_trigger(u_int irq);
139 void elcr_resume(void);
140 void elcr_write_trigger(u_int irq, enum intr_trigger trigger);
142 void intr_add_cpu(u_int cpu);
144 int intr_add_handler(const char *name, int vector, driver_filter_t filter,
145 driver_intr_t handler, void *arg, enum intr_type flags,
148 int intr_bind(u_int vector, u_char cpu);
150 int intr_config_intr(int vector, enum intr_trigger trig,
151 enum intr_polarity pol);
152 int intr_describe(u_int vector, void *ih, const char *descr);
153 void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame);
154 u_int intr_next_cpu(void);
155 struct intsrc *intr_lookup_source(int vector);
156 int intr_register_pic(struct pic *pic);
157 int intr_register_source(struct intsrc *isrc);
158 int intr_remove_handler(void *cookie);
159 void intr_resume(bool suspend_cancelled);
160 void intr_suspend(void);
161 void intr_reprogram(void);
162 void intrcnt_add(const char *name, u_long **countp);
163 void nexus_add_irq(u_long irq);
164 int msi_alloc(device_t dev, int count, int maxcount, int *irqs);
166 int msi_map(int irq, uint64_t *addr, uint32_t *data);
167 int msi_release(int *irqs, int count);
168 int msix_alloc(device_t dev, int *irq);
169 int msix_release(int irq);
171 void xen_intr_alloc_irqs(void);
176 #endif /* !__X86_INTR_MACHDEP_H__ */