2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1991 The Regents of the University of California.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the University nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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31 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
35 #ifndef _MACHINE_SPECIALREG_H_
36 #define _MACHINE_SPECIALREG_H_
39 * Bits in 386 special registers:
41 #define CR0_PE 0x00000001 /* Protected mode Enable */
42 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
43 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
44 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
45 #define CR0_PG 0x80000000 /* PaGing enable */
48 * Bits in 486 special registers:
50 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
51 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
53 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
54 #define CR0_NW 0x20000000 /* Not Write-through */
55 #define CR0_CD 0x40000000 /* Cache Disable */
57 #define CR3_PCID_SAVE 0x8000000000000000
58 #define CR3_PCID_MASK 0xfff
61 * Bits in PPro special registers
63 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
64 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
65 #define CR4_TSD 0x00000004 /* Time stamp disable */
66 #define CR4_DE 0x00000008 /* Debugging extensions */
67 #define CR4_PSE 0x00000010 /* Page size extensions */
68 #define CR4_PAE 0x00000020 /* Physical address extension */
69 #define CR4_MCE 0x00000040 /* Machine check enable */
70 #define CR4_PGE 0x00000080 /* Page global enable */
71 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
72 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
73 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
74 #define CR4_UMIP 0x00000800 /* User Mode Instruction Prevention */
75 #define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */
76 #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */
77 #define CR4_PCIDE 0x00020000 /* Enable Context ID */
78 #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */
79 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */
80 #define CR4_SMAP 0x00200000 /* Supervisor-Mode Access Prevention */
81 #define CR4_PKE 0x00400000 /* Protection Keys Enable */
84 * Bits in AMD64 special registers. EFER is 64 bits wide.
86 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
87 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */
88 #define EFER_LMA 0x000000400 /* Long mode active (R) */
89 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
90 #define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */
91 #define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */
92 #define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */
93 #define EFER_TCE 0x000008000 /* Translation Cache Extension */
94 #define EFER_MCOMMIT 0x00020000 /* Enable MCOMMIT (AMD) */
97 * Intel Extended Features registers
99 #define XCR0 0 /* XFEATURE_ENABLED_MASK register */
101 #define XFEATURE_ENABLED_X87 0x00000001
102 #define XFEATURE_ENABLED_SSE 0x00000002
103 #define XFEATURE_ENABLED_YMM_HI128 0x00000004
104 #define XFEATURE_ENABLED_AVX XFEATURE_ENABLED_YMM_HI128
105 #define XFEATURE_ENABLED_BNDREGS 0x00000008
106 #define XFEATURE_ENABLED_BNDCSR 0x00000010
107 #define XFEATURE_ENABLED_OPMASK 0x00000020
108 #define XFEATURE_ENABLED_ZMM_HI256 0x00000040
109 #define XFEATURE_ENABLED_HI16_ZMM 0x00000080
111 #define XFEATURE_AVX \
112 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX)
113 #define XFEATURE_AVX512 \
114 (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 | \
115 XFEATURE_ENABLED_HI16_ZMM)
116 #define XFEATURE_MPX \
117 (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR)
120 * CPUID instruction features register
122 #define CPUID_FPU 0x00000001
123 #define CPUID_VME 0x00000002
124 #define CPUID_DE 0x00000004
125 #define CPUID_PSE 0x00000008
126 #define CPUID_TSC 0x00000010
127 #define CPUID_MSR 0x00000020
128 #define CPUID_PAE 0x00000040
129 #define CPUID_MCE 0x00000080
130 #define CPUID_CX8 0x00000100
131 #define CPUID_APIC 0x00000200
132 #define CPUID_B10 0x00000400
133 #define CPUID_SEP 0x00000800
134 #define CPUID_MTRR 0x00001000
135 #define CPUID_PGE 0x00002000
136 #define CPUID_MCA 0x00004000
137 #define CPUID_CMOV 0x00008000
138 #define CPUID_PAT 0x00010000
139 #define CPUID_PSE36 0x00020000
140 #define CPUID_PSN 0x00040000
141 #define CPUID_CLFSH 0x00080000
142 #define CPUID_B20 0x00100000
143 #define CPUID_DS 0x00200000
144 #define CPUID_ACPI 0x00400000
145 #define CPUID_MMX 0x00800000
146 #define CPUID_FXSR 0x01000000
147 #define CPUID_SSE 0x02000000
148 #define CPUID_XMM 0x02000000
149 #define CPUID_SSE2 0x04000000
150 #define CPUID_SS 0x08000000
151 #define CPUID_HTT 0x10000000
152 #define CPUID_TM 0x20000000
153 #define CPUID_IA64 0x40000000
154 #define CPUID_PBE 0x80000000
156 #define CPUID2_SSE3 0x00000001
157 #define CPUID2_PCLMULQDQ 0x00000002
158 #define CPUID2_DTES64 0x00000004
159 #define CPUID2_MON 0x00000008
160 #define CPUID2_DS_CPL 0x00000010
161 #define CPUID2_VMX 0x00000020
162 #define CPUID2_SMX 0x00000040
163 #define CPUID2_EST 0x00000080
164 #define CPUID2_TM2 0x00000100
165 #define CPUID2_SSSE3 0x00000200
166 #define CPUID2_CNXTID 0x00000400
167 #define CPUID2_SDBG 0x00000800
168 #define CPUID2_FMA 0x00001000
169 #define CPUID2_CX16 0x00002000
170 #define CPUID2_XTPR 0x00004000
171 #define CPUID2_PDCM 0x00008000
172 #define CPUID2_PCID 0x00020000
173 #define CPUID2_DCA 0x00040000
174 #define CPUID2_SSE41 0x00080000
175 #define CPUID2_SSE42 0x00100000
176 #define CPUID2_X2APIC 0x00200000
177 #define CPUID2_MOVBE 0x00400000
178 #define CPUID2_POPCNT 0x00800000
179 #define CPUID2_TSCDLT 0x01000000
180 #define CPUID2_AESNI 0x02000000
181 #define CPUID2_XSAVE 0x04000000
182 #define CPUID2_OSXSAVE 0x08000000
183 #define CPUID2_AVX 0x10000000
184 #define CPUID2_F16C 0x20000000
185 #define CPUID2_RDRAND 0x40000000
186 #define CPUID2_HV 0x80000000
188 /* Intel Processor Trace CPUID. */
191 #define CPUPT_CR3 (1 << 0) /* CR3 Filtering Support */
192 #define CPUPT_PSB (1 << 1) /* Configurable PSB and Cycle-Accurate Mode Supported */
193 #define CPUPT_IPF (1 << 2) /* IP Filtering and TraceStop supported */
194 #define CPUPT_MTC (1 << 3) /* MTC Supported */
195 #define CPUPT_PRW (1 << 4) /* PTWRITE Supported */
196 #define CPUPT_PWR (1 << 5) /* Power Event Trace Supported */
199 #define CPUPT_TOPA (1 << 0) /* ToPA Output Supported */
200 #define CPUPT_TOPA_MULTI (1 << 1) /* ToPA Tables Allow Multiple Output Entries */
201 #define CPUPT_SINGLE (1 << 2) /* Single-Range Output Supported */
202 #define CPUPT_TT_OUT (1 << 3) /* Output to Trace Transport Subsystem Supported */
203 #define CPUPT_LINEAR_IP (1 << 31) /* IP Payloads are Linear IP, otherwise IP is effective */
206 #define CPUPT_NADDR_S 0 /* Number of Address Ranges */
207 #define CPUPT_NADDR_M (0x7 << CPUPT_NADDR_S)
208 #define CPUPT_MTC_BITMAP_S 16 /* Bitmap of supported MTC Period Encodings */
209 #define CPUPT_MTC_BITMAP_M (0xffff << CPUPT_MTC_BITMAP_S)
212 #define CPUPT_CT_BITMAP_S 0 /* Bitmap of supported Cycle Threshold values */
213 #define CPUPT_CT_BITMAP_M (0xffff << CPUPT_CT_BITMAP_S)
214 #define CPUPT_PFE_BITMAP_S 16 /* Bitmap of supported Configurable PSB Frequency encoding */
215 #define CPUPT_PFE_BITMAP_M (0xffff << CPUPT_PFE_BITMAP_S)
218 * Important bits in the AMD extended cpuid flags
220 #define AMDID_SYSCALL 0x00000800
221 #define AMDID_MP 0x00080000
222 #define AMDID_NX 0x00100000
223 #define AMDID_EXT_MMX 0x00400000
224 #define AMDID_FFXSR 0x02000000
225 #define AMDID_PAGE1GB 0x04000000
226 #define AMDID_RDTSCP 0x08000000
227 #define AMDID_LM 0x20000000
228 #define AMDID_EXT_3DNOW 0x40000000
229 #define AMDID_3DNOW 0x80000000
231 #define AMDID2_LAHF 0x00000001
232 #define AMDID2_CMP 0x00000002
233 #define AMDID2_SVM 0x00000004
234 #define AMDID2_EXT_APIC 0x00000008
235 #define AMDID2_CR8 0x00000010
236 #define AMDID2_ABM 0x00000020
237 #define AMDID2_SSE4A 0x00000040
238 #define AMDID2_MAS 0x00000080
239 #define AMDID2_PREFETCH 0x00000100
240 #define AMDID2_OSVW 0x00000200
241 #define AMDID2_IBS 0x00000400
242 #define AMDID2_XOP 0x00000800
243 #define AMDID2_SKINIT 0x00001000
244 #define AMDID2_WDT 0x00002000
245 #define AMDID2_LWP 0x00008000
246 #define AMDID2_FMA4 0x00010000
247 #define AMDID2_TCE 0x00020000
248 #define AMDID2_NODE_ID 0x00080000
249 #define AMDID2_TBM 0x00200000
250 #define AMDID2_TOPOLOGY 0x00400000
251 #define AMDID2_PCXC 0x00800000
252 #define AMDID2_PNXC 0x01000000
253 #define AMDID2_DBE 0x04000000
254 #define AMDID2_PTSC 0x08000000
255 #define AMDID2_PTSCEL2I 0x10000000
256 #define AMDID2_MWAITX 0x20000000
259 * CPUID instruction 1 eax info
261 #define CPUID_STEPPING 0x0000000f
262 #define CPUID_MODEL 0x000000f0
263 #define CPUID_FAMILY 0x00000f00
264 #define CPUID_EXT_MODEL 0x000f0000
265 #define CPUID_EXT_FAMILY 0x0ff00000
267 #define CPUID_TO_MODEL(id) \
268 ((((id) & CPUID_MODEL) >> 4) | \
269 ((((id) & CPUID_FAMILY) >= 0x600) ? \
270 (((id) & CPUID_EXT_MODEL) >> 12) : 0))
271 #define CPUID_TO_FAMILY(id) \
272 ((((id) & CPUID_FAMILY) >> 8) + \
273 ((((id) & CPUID_FAMILY) == 0xf00) ? \
274 (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
276 #define CPUID_TO_MODEL(id) \
277 ((((id) & CPUID_MODEL) >> 4) | \
278 (((id) & CPUID_EXT_MODEL) >> 12))
279 #define CPUID_TO_FAMILY(id) \
280 ((((id) & CPUID_FAMILY) >> 8) + \
281 (((id) & CPUID_EXT_FAMILY) >> 20))
285 * CPUID instruction 1 ebx info
287 #define CPUID_BRAND_INDEX 0x000000ff
288 #define CPUID_CLFUSH_SIZE 0x0000ff00
289 #define CPUID_HTT_CORES 0x00ff0000
290 #define CPUID_LOCAL_APIC_ID 0xff000000
293 * CPUID instruction 5 info
295 #define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */
296 #define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */
297 #define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */
298 #define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */
301 * MWAIT cpu power states. Lower 4 bits are sub-states.
303 #define MWAIT_C0 0xf0
304 #define MWAIT_C1 0x00
305 #define MWAIT_C2 0x10
306 #define MWAIT_C3 0x20
307 #define MWAIT_C4 0x30
312 /* Interrupt breaks MWAIT even when masked. */
313 #define MWAIT_INTRBREAK 0x00000001
316 * CPUID leaf 6: Thermal and Power management.
319 #define CPUTPM1_SENSOR 0x00000001
320 #define CPUTPM1_TURBO 0x00000002
321 #define CPUTPM1_ARAT 0x00000004
322 #define CPUTPM1_PLN 0x00000010
323 #define CPUTPM1_ECMD 0x00000020
324 #define CPUTPM1_PTM 0x00000040
325 #define CPUTPM1_HWP 0x00000080
326 #define CPUTPM1_HWP_NOTIFICATION 0x00000100
327 #define CPUTPM1_HWP_ACTIVITY_WINDOW 0x00000200
328 #define CPUTPM1_HWP_PERF_PREF 0x00000400
329 #define CPUTPM1_HWP_PKG 0x00000800
330 #define CPUTPM1_HDC 0x00002000
331 #define CPUTPM1_TURBO30 0x00004000
332 #define CPUTPM1_HWP_CAPABILITIES 0x00008000
333 #define CPUTPM1_HWP_PECI_OVR 0x00010000
334 #define CPUTPM1_HWP_FLEXIBLE 0x00020000
335 #define CPUTPM1_HWP_FAST_MSR 0x00040000
336 #define CPUTPM1_HWP_IGN_IDLE 0x00100000
339 #define CPUTPM_B_NSENSINTTHRESH 0x0000000f
342 #define CPUID_PERF_STAT 0x00000001
343 #define CPUID_PERF_BIAS 0x00000008
346 * CPUID instruction 0xb ebx info.
348 #define CPUID_TYPE_INVAL 0
349 #define CPUID_TYPE_SMT 1
350 #define CPUID_TYPE_CORE 2
353 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1
355 #define CPUID_EXTSTATE_XSAVEOPT 0x00000001
356 #define CPUID_EXTSTATE_XSAVEC 0x00000002
357 #define CPUID_EXTSTATE_XINUSE 0x00000004
358 #define CPUID_EXTSTATE_XSAVES 0x00000008
361 * AMD extended function 8000_0007h ebx info
363 #define AMDRAS_MCA_OF_RECOV 0x00000001
364 #define AMDRAS_SUCCOR 0x00000002
365 #define AMDRAS_HW_ASSERT 0x00000004
366 #define AMDRAS_SCALABLE_MCA 0x00000008
367 #define AMDRAS_PFEH_SUPPORT 0x00000010
370 * AMD extended function 8000_0007h edx info
372 #define AMDPM_TS 0x00000001
373 #define AMDPM_FID 0x00000002
374 #define AMDPM_VID 0x00000004
375 #define AMDPM_TTP 0x00000008
376 #define AMDPM_TM 0x00000010
377 #define AMDPM_STC 0x00000020
378 #define AMDPM_100MHZ_STEPS 0x00000040
379 #define AMDPM_HW_PSTATE 0x00000080
380 #define AMDPM_TSC_INVARIANT 0x00000100
381 #define AMDPM_CPB 0x00000200
384 * AMD extended function 8000_0008h ebx info (amd_extended_feature_extensions)
386 #define AMDFEID_CLZERO 0x00000001
387 #define AMDFEID_IRPERF 0x00000002
388 #define AMDFEID_XSAVEERPTR 0x00000004
389 #define AMDFEID_RDPRU 0x00000010
390 #define AMDFEID_MCOMMIT 0x00000100
391 #define AMDFEID_WBNOINVD 0x00000200
392 #define AMDFEID_IBPB 0x00001000
393 #define AMDFEID_IBRS 0x00004000
394 #define AMDFEID_STIBP 0x00008000
395 /* The below are only defined if the corresponding base feature above exists. */
396 #define AMDFEID_IBRS_ALWAYSON 0x00010000
397 #define AMDFEID_STIBP_ALWAYSON 0x00020000
398 #define AMDFEID_PREFER_IBRS 0x00040000
399 #define AMDFEID_PPIN 0x00800000
400 #define AMDFEID_SSBD 0x01000000
401 /* SSBD via MSRC001_011F instead of MSR 0x48: */
402 #define AMDFEID_VIRT_SSBD 0x02000000
403 #define AMDFEID_SSB_NO 0x04000000
406 * AMD extended function 8000_0008h ecx info
408 #define AMDID_CMP_CORES 0x000000ff
409 #define AMDID_COREID_SIZE 0x0000f000
410 #define AMDID_COREID_SIZE_SHIFT 12
413 * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info
415 #define CPUID_STDEXT_FSGSBASE 0x00000001
416 #define CPUID_STDEXT_TSC_ADJUST 0x00000002
417 #define CPUID_STDEXT_SGX 0x00000004
418 #define CPUID_STDEXT_BMI1 0x00000008
419 #define CPUID_STDEXT_HLE 0x00000010
420 #define CPUID_STDEXT_AVX2 0x00000020
421 #define CPUID_STDEXT_FDP_EXC 0x00000040
422 #define CPUID_STDEXT_SMEP 0x00000080
423 #define CPUID_STDEXT_BMI2 0x00000100
424 #define CPUID_STDEXT_ERMS 0x00000200
425 #define CPUID_STDEXT_INVPCID 0x00000400
426 #define CPUID_STDEXT_RTM 0x00000800
427 #define CPUID_STDEXT_PQM 0x00001000
428 #define CPUID_STDEXT_NFPUSG 0x00002000
429 #define CPUID_STDEXT_MPX 0x00004000
430 #define CPUID_STDEXT_PQE 0x00008000
431 #define CPUID_STDEXT_AVX512F 0x00010000
432 #define CPUID_STDEXT_AVX512DQ 0x00020000
433 #define CPUID_STDEXT_RDSEED 0x00040000
434 #define CPUID_STDEXT_ADX 0x00080000
435 #define CPUID_STDEXT_SMAP 0x00100000
436 #define CPUID_STDEXT_AVX512IFMA 0x00200000
437 /* Formerly PCOMMIT */
438 #define CPUID_STDEXT_CLFLUSHOPT 0x00800000
439 #define CPUID_STDEXT_CLWB 0x01000000
440 #define CPUID_STDEXT_PROCTRACE 0x02000000
441 #define CPUID_STDEXT_AVX512PF 0x04000000
442 #define CPUID_STDEXT_AVX512ER 0x08000000
443 #define CPUID_STDEXT_AVX512CD 0x10000000
444 #define CPUID_STDEXT_SHA 0x20000000
445 #define CPUID_STDEXT_AVX512BW 0x40000000
446 #define CPUID_STDEXT_AVX512VL 0x80000000
449 * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info
451 #define CPUID_STDEXT2_PREFETCHWT1 0x00000001
452 #define CPUID_STDEXT2_AVX512VBMI 0x00000002
453 #define CPUID_STDEXT2_UMIP 0x00000004
454 #define CPUID_STDEXT2_PKU 0x00000008
455 #define CPUID_STDEXT2_OSPKE 0x00000010
456 #define CPUID_STDEXT2_WAITPKG 0x00000020
457 #define CPUID_STDEXT2_AVX512VBMI2 0x00000040
458 #define CPUID_STDEXT2_GFNI 0x00000100
459 #define CPUID_STDEXT2_VAES 0x00000200
460 #define CPUID_STDEXT2_VPCLMULQDQ 0x00000400
461 #define CPUID_STDEXT2_AVX512VNNI 0x00000800
462 #define CPUID_STDEXT2_AVX512BITALG 0x00001000
463 #define CPUID_STDEXT2_TME 0x00002000
464 #define CPUID_STDEXT2_AVX512VPOPCNTDQ 0x00004000
465 #define CPUID_STDEXT2_LA57 0x00010000
466 #define CPUID_STDEXT2_RDPID 0x00400000
467 #define CPUID_STDEXT2_CLDEMOTE 0x02000000
468 #define CPUID_STDEXT2_MOVDIRI 0x08000000
469 #define CPUID_STDEXT2_MOVDIR64B 0x10000000
470 #define CPUID_STDEXT2_ENQCMD 0x20000000
471 #define CPUID_STDEXT2_SGXLC 0x40000000
474 * CPUID instruction 7 Structured Extended Features, leaf 0 edx info
476 #define CPUID_STDEXT3_AVX5124VNNIW 0x00000004
477 #define CPUID_STDEXT3_AVX5124FMAPS 0x00000008
478 #define CPUID_STDEXT3_FSRM 0x00000010
479 #define CPUID_STDEXT3_AVX512VP2INTERSECT 0x00000100
480 #define CPUID_STDEXT3_MCUOPT 0x00000200
481 #define CPUID_STDEXT3_MD_CLEAR 0x00000400
482 #define CPUID_STDEXT3_TSXFA 0x00002000
483 #define CPUID_STDEXT3_PCONFIG 0x00040000
484 #define CPUID_STDEXT3_IBPB 0x04000000
485 #define CPUID_STDEXT3_STIBP 0x08000000
486 #define CPUID_STDEXT3_L1D_FLUSH 0x10000000
487 #define CPUID_STDEXT3_ARCH_CAP 0x20000000
488 #define CPUID_STDEXT3_CORE_CAP 0x40000000
489 #define CPUID_STDEXT3_SSBD 0x80000000
491 /* MSR IA32_ARCH_CAP(ABILITIES) bits */
492 #define IA32_ARCH_CAP_RDCL_NO 0x00000001
493 #define IA32_ARCH_CAP_IBRS_ALL 0x00000002
494 #define IA32_ARCH_CAP_RSBA 0x00000004
495 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x00000008
496 #define IA32_ARCH_CAP_SSB_NO 0x00000010
497 #define IA32_ARCH_CAP_MDS_NO 0x00000020
498 #define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x00000040
499 #define IA32_ARCH_CAP_TSX_CTRL 0x00000080
500 #define IA32_ARCH_CAP_TAA_NO 0x00000100
502 /* MSR IA32_TSX_CTRL bits */
503 #define IA32_TSX_CTRL_RTM_DISABLE 0x00000001
504 #define IA32_TSX_CTRL_TSX_CPUID_CLEAR 0x00000002
507 * CPUID manufacturers identifiers
509 #define AMD_VENDOR_ID "AuthenticAMD"
510 #define CENTAUR_VENDOR_ID "CentaurHauls"
511 #define CYRIX_VENDOR_ID "CyrixInstead"
512 #define INTEL_VENDOR_ID "GenuineIntel"
513 #define NEXGEN_VENDOR_ID "NexGenDriven"
514 #define NSC_VENDOR_ID "Geode by NSC"
515 #define RISE_VENDOR_ID "RiseRiseRise"
516 #define SIS_VENDOR_ID "SiS SiS SiS "
517 #define TRANSMETA_VENDOR_ID "GenuineTMx86"
518 #define UMC_VENDOR_ID "UMC UMC UMC "
519 #define HYGON_VENDOR_ID "HygonGenuine"
522 * Model-specific registers for the i386 family
524 #define MSR_P5_MC_ADDR 0x000
525 #define MSR_P5_MC_TYPE 0x001
526 #define MSR_TSC 0x010
527 #define MSR_P5_CESR 0x011
528 #define MSR_P5_CTR0 0x012
529 #define MSR_P5_CTR1 0x013
530 #define MSR_IA32_PLATFORM_ID 0x017
531 #define MSR_APICBASE 0x01b
532 #define MSR_EBL_CR_POWERON 0x02a
533 #define MSR_TEST_CTL 0x033
534 #define MSR_IA32_FEATURE_CONTROL 0x03a
535 #define MSR_IA32_SPEC_CTRL 0x048
536 #define MSR_IA32_PRED_CMD 0x049
537 #define MSR_BIOS_UPDT_TRIG 0x079
538 #define MSR_BBL_CR_D0 0x088
539 #define MSR_BBL_CR_D1 0x089
540 #define MSR_BBL_CR_D2 0x08a
541 #define MSR_BIOS_SIGN 0x08b
542 #define MSR_PERFCTR0 0x0c1
543 #define MSR_PERFCTR1 0x0c2
544 #define MSR_PLATFORM_INFO 0x0ce
545 #define MSR_MPERF 0x0e7
546 #define MSR_APERF 0x0e8
547 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
548 #define MSR_MTRRcap 0x0fe
549 #define MSR_IA32_ARCH_CAP 0x10a
550 #define MSR_IA32_FLUSH_CMD 0x10b
551 #define MSR_TSX_FORCE_ABORT 0x10f
552 #define MSR_BBL_CR_ADDR 0x116
553 #define MSR_BBL_CR_DECC 0x118
554 #define MSR_BBL_CR_CTL 0x119
555 #define MSR_BBL_CR_TRIG 0x11a
556 #define MSR_BBL_CR_BUSY 0x11b
557 #define MSR_BBL_CR_CTL3 0x11e
558 #define MSR_IA32_TSX_CTRL 0x122
559 #define MSR_IA32_MCU_OPT_CTRL 0x123
560 #define MSR_SYSENTER_CS_MSR 0x174
561 #define MSR_SYSENTER_ESP_MSR 0x175
562 #define MSR_SYSENTER_EIP_MSR 0x176
563 #define MSR_MCG_CAP 0x179
564 #define MSR_MCG_STATUS 0x17a
565 #define MSR_MCG_CTL 0x17b
566 #define MSR_EVNTSEL0 0x186
567 #define MSR_EVNTSEL1 0x187
568 #define MSR_THERM_CONTROL 0x19a
569 #define MSR_THERM_INTERRUPT 0x19b
570 #define MSR_THERM_STATUS 0x19c
571 #define MSR_IA32_MISC_ENABLE 0x1a0
572 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2
573 #define MSR_TURBO_RATIO_LIMIT 0x1ad
574 #define MSR_TURBO_RATIO_LIMIT1 0x1ae
575 #define MSR_IA32_ENERGY_PERF_BIAS 0x1b0
576 #define MSR_DEBUGCTLMSR 0x1d9
577 #define MSR_LASTBRANCHFROMIP 0x1db
578 #define MSR_LASTBRANCHTOIP 0x1dc
579 #define MSR_LASTINTFROMIP 0x1dd
580 #define MSR_LASTINTTOIP 0x1de
581 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
582 #define MSR_MTRRVarBase 0x200
583 #define MSR_MTRR64kBase 0x250
584 #define MSR_MTRR16kBase 0x258
585 #define MSR_MTRR4kBase 0x268
586 #define MSR_PAT 0x277
587 #define MSR_MC0_CTL2 0x280
588 #define MSR_MTRRdefType 0x2ff
589 #define MSR_MC0_CTL 0x400
590 #define MSR_MC0_STATUS 0x401
591 #define MSR_MC0_ADDR 0x402
592 #define MSR_MC0_MISC 0x403
593 #define MSR_MC1_CTL 0x404
594 #define MSR_MC1_STATUS 0x405
595 #define MSR_MC1_ADDR 0x406
596 #define MSR_MC1_MISC 0x407
597 #define MSR_MC2_CTL 0x408
598 #define MSR_MC2_STATUS 0x409
599 #define MSR_MC2_ADDR 0x40a
600 #define MSR_MC2_MISC 0x40b
601 #define MSR_MC3_CTL 0x40c
602 #define MSR_MC3_STATUS 0x40d
603 #define MSR_MC3_ADDR 0x40e
604 #define MSR_MC3_MISC 0x40f
605 #define MSR_MC4_CTL 0x410
606 #define MSR_MC4_STATUS 0x411
607 #define MSR_MC4_ADDR 0x412
608 #define MSR_MC4_MISC 0x413
609 #define MSR_RAPL_POWER_UNIT 0x606
610 #define MSR_PKG_ENERGY_STATUS 0x611
611 #define MSR_DRAM_ENERGY_STATUS 0x619
612 #define MSR_PP0_ENERGY_STATUS 0x639
613 #define MSR_PP1_ENERGY_STATUS 0x641
614 #define MSR_PPERF 0x64e
615 #define MSR_TSC_DEADLINE 0x6e0 /* Writes are not serializing */
616 #define MSR_IA32_PM_ENABLE 0x770
617 #define MSR_IA32_HWP_CAPABILITIES 0x771
618 #define MSR_IA32_HWP_REQUEST_PKG 0x772
619 #define MSR_IA32_HWP_INTERRUPT 0x773
620 #define MSR_IA32_HWP_REQUEST 0x774
621 #define MSR_IA32_HWP_STATUS 0x777
626 #define MSR_VMX_BASIC 0x480
627 #define MSR_VMX_PINBASED_CTLS 0x481
628 #define MSR_VMX_PROCBASED_CTLS 0x482
629 #define MSR_VMX_EXIT_CTLS 0x483
630 #define MSR_VMX_ENTRY_CTLS 0x484
631 #define MSR_VMX_CR0_FIXED0 0x486
632 #define MSR_VMX_CR0_FIXED1 0x487
633 #define MSR_VMX_CR4_FIXED0 0x488
634 #define MSR_VMX_CR4_FIXED1 0x489
635 #define MSR_VMX_PROCBASED_CTLS2 0x48b
636 #define MSR_VMX_EPT_VPID_CAP 0x48c
637 #define MSR_VMX_TRUE_PINBASED_CTLS 0x48d
638 #define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e
639 #define MSR_VMX_TRUE_EXIT_CTLS 0x48f
640 #define MSR_VMX_TRUE_ENTRY_CTLS 0x490
644 * Writes are not serializing.
646 #define MSR_APIC_000 0x800
647 #define MSR_APIC_ID 0x802
648 #define MSR_APIC_VERSION 0x803
649 #define MSR_APIC_TPR 0x808
650 #define MSR_APIC_EOI 0x80b
651 #define MSR_APIC_LDR 0x80d
652 #define MSR_APIC_SVR 0x80f
653 #define MSR_APIC_ISR0 0x810
654 #define MSR_APIC_ISR1 0x811
655 #define MSR_APIC_ISR2 0x812
656 #define MSR_APIC_ISR3 0x813
657 #define MSR_APIC_ISR4 0x814
658 #define MSR_APIC_ISR5 0x815
659 #define MSR_APIC_ISR6 0x816
660 #define MSR_APIC_ISR7 0x817
661 #define MSR_APIC_TMR0 0x818
662 #define MSR_APIC_IRR0 0x820
663 #define MSR_APIC_ESR 0x828
664 #define MSR_APIC_LVT_CMCI 0x82F
665 #define MSR_APIC_ICR 0x830
666 #define MSR_APIC_LVT_TIMER 0x832
667 #define MSR_APIC_LVT_THERMAL 0x833
668 #define MSR_APIC_LVT_PCINT 0x834
669 #define MSR_APIC_LVT_LINT0 0x835
670 #define MSR_APIC_LVT_LINT1 0x836
671 #define MSR_APIC_LVT_ERROR 0x837
672 #define MSR_APIC_ICR_TIMER 0x838
673 #define MSR_APIC_CCR_TIMER 0x839
674 #define MSR_APIC_DCR_TIMER 0x83e
675 #define MSR_APIC_SELF_IPI 0x83f
677 #define MSR_IA32_XSS 0xda0
680 * Intel Processor Trace (PT) MSRs.
682 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 /* Trace Output Base Register (R/W) */
683 #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x561 /* Trace Output Mask Pointers Register (R/W) */
684 #define MSR_IA32_RTIT_CTL 0x570 /* Trace Control Register (R/W) */
685 #define RTIT_CTL_TRACEEN (1 << 0)
686 #define RTIT_CTL_CYCEN (1 << 1)
687 #define RTIT_CTL_OS (1 << 2)
688 #define RTIT_CTL_USER (1 << 3)
689 #define RTIT_CTL_PWREVTEN (1 << 4)
690 #define RTIT_CTL_FUPONPTW (1 << 5)
691 #define RTIT_CTL_FABRICEN (1 << 6)
692 #define RTIT_CTL_CR3FILTER (1 << 7)
693 #define RTIT_CTL_TOPA (1 << 8)
694 #define RTIT_CTL_MTCEN (1 << 9)
695 #define RTIT_CTL_TSCEN (1 << 10)
696 #define RTIT_CTL_DISRETC (1 << 11)
697 #define RTIT_CTL_PTWEN (1 << 12)
698 #define RTIT_CTL_BRANCHEN (1 << 13)
699 #define RTIT_CTL_MTC_FREQ_S 14
700 #define RTIT_CTL_MTC_FREQ(n) ((n) << RTIT_CTL_MTC_FREQ_S)
701 #define RTIT_CTL_MTC_FREQ_M (0xf << RTIT_CTL_MTC_FREQ_S)
702 #define RTIT_CTL_CYC_THRESH_S 19
703 #define RTIT_CTL_CYC_THRESH_M (0xf << RTIT_CTL_CYC_THRESH_S)
704 #define RTIT_CTL_PSB_FREQ_S 24
705 #define RTIT_CTL_PSB_FREQ_M (0xf << RTIT_CTL_PSB_FREQ_S)
706 #define RTIT_CTL_ADDR_CFG_S(n) (32 + (n) * 4)
707 #define RTIT_CTL_ADDR0_CFG_S 32
708 #define RTIT_CTL_ADDR0_CFG_M (0xfULL << RTIT_CTL_ADDR0_CFG_S)
709 #define RTIT_CTL_ADDR1_CFG_S 36
710 #define RTIT_CTL_ADDR1_CFG_M (0xfULL << RTIT_CTL_ADDR1_CFG_S)
711 #define RTIT_CTL_ADDR2_CFG_S 40
712 #define RTIT_CTL_ADDR2_CFG_M (0xfULL << RTIT_CTL_ADDR2_CFG_S)
713 #define RTIT_CTL_ADDR3_CFG_S 44
714 #define RTIT_CTL_ADDR3_CFG_M (0xfULL << RTIT_CTL_ADDR3_CFG_S)
715 #define MSR_IA32_RTIT_STATUS 0x571 /* Tracing Status Register (R/W) */
716 #define RTIT_STATUS_FILTEREN (1 << 0)
717 #define RTIT_STATUS_CONTEXTEN (1 << 1)
718 #define RTIT_STATUS_TRIGGEREN (1 << 2)
719 #define RTIT_STATUS_ERROR (1 << 4)
720 #define RTIT_STATUS_STOPPED (1 << 5)
721 #define RTIT_STATUS_PACKETBYTECNT_S 32
722 #define RTIT_STATUS_PACKETBYTECNT_M (0x1ffffULL << RTIT_STATUS_PACKETBYTECNT_S)
723 #define MSR_IA32_RTIT_CR3_MATCH 0x572 /* Trace Filter CR3 Match Register (R/W) */
724 #define MSR_IA32_RTIT_ADDR_A(n) (0x580 + (n) * 2)
725 #define MSR_IA32_RTIT_ADDR_B(n) (0x581 + (n) * 2)
726 #define MSR_IA32_RTIT_ADDR0_A 0x580 /* Region 0 Start Address (R/W) */
727 #define MSR_IA32_RTIT_ADDR0_B 0x581 /* Region 0 End Address (R/W) */
728 #define MSR_IA32_RTIT_ADDR1_A 0x582 /* Region 1 Start Address (R/W) */
729 #define MSR_IA32_RTIT_ADDR1_B 0x583 /* Region 1 End Address (R/W) */
730 #define MSR_IA32_RTIT_ADDR2_A 0x584 /* Region 2 Start Address (R/W) */
731 #define MSR_IA32_RTIT_ADDR2_B 0x585 /* Region 2 End Address (R/W) */
732 #define MSR_IA32_RTIT_ADDR3_A 0x586 /* Region 3 Start Address (R/W) */
733 #define MSR_IA32_RTIT_ADDR3_B 0x587 /* Region 3 End Address (R/W) */
735 /* Intel Processor Trace Table of Physical Addresses (ToPA). */
736 #define TOPA_SIZE_S 6
737 #define TOPA_SIZE_M (0xf << TOPA_SIZE_S)
738 #define TOPA_SIZE_4K (0 << TOPA_SIZE_S)
739 #define TOPA_SIZE_8K (1 << TOPA_SIZE_S)
740 #define TOPA_SIZE_16K (2 << TOPA_SIZE_S)
741 #define TOPA_SIZE_32K (3 << TOPA_SIZE_S)
742 #define TOPA_SIZE_64K (4 << TOPA_SIZE_S)
743 #define TOPA_SIZE_128K (5 << TOPA_SIZE_S)
744 #define TOPA_SIZE_256K (6 << TOPA_SIZE_S)
745 #define TOPA_SIZE_512K (7 << TOPA_SIZE_S)
746 #define TOPA_SIZE_1M (8 << TOPA_SIZE_S)
747 #define TOPA_SIZE_2M (9 << TOPA_SIZE_S)
748 #define TOPA_SIZE_4M (10 << TOPA_SIZE_S)
749 #define TOPA_SIZE_8M (11 << TOPA_SIZE_S)
750 #define TOPA_SIZE_16M (12 << TOPA_SIZE_S)
751 #define TOPA_SIZE_32M (13 << TOPA_SIZE_S)
752 #define TOPA_SIZE_64M (14 << TOPA_SIZE_S)
753 #define TOPA_SIZE_128M (15 << TOPA_SIZE_S)
754 #define TOPA_STOP (1 << 4)
755 #define TOPA_INT (1 << 2)
756 #define TOPA_END (1 << 0)
759 * Constants related to MSR's.
761 #define APICBASE_RESERVED 0x000002ff
762 #define APICBASE_BSP 0x00000100
763 #define APICBASE_X2APIC 0x00000400
764 #define APICBASE_ENABLED 0x00000800
765 #define APICBASE_ADDRESS 0xfffff000
767 /* MSR_IA32_FEATURE_CONTROL related */
768 #define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */
769 #define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */
770 #define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */
772 /* MSR IA32_MISC_ENABLE */
773 #define IA32_MISC_EN_FASTSTR 0x0000000000000001ULL
774 #define IA32_MISC_EN_ATCCE 0x0000000000000008ULL
775 #define IA32_MISC_EN_PERFMON 0x0000000000000080ULL
776 #define IA32_MISC_EN_PEBSU 0x0000000000001000ULL
777 #define IA32_MISC_EN_ESSTE 0x0000000000010000ULL
778 #define IA32_MISC_EN_MONE 0x0000000000040000ULL
779 #define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL
780 #define IA32_MISC_EN_xTPRD 0x0000000000800000ULL
781 #define IA32_MISC_EN_XDD 0x0000000400000000ULL
784 * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel'
785 * document 336996-001 Speculative Execution Side Channel Mitigations.
787 * AMD uses the same MSRs and bit definitions, as described in 111006-B
788 * "Indirect Branch Control Extension" and 124441 "Speculative Store Bypass
791 /* MSR IA32_SPEC_CTRL */
792 #define IA32_SPEC_CTRL_IBRS 0x00000001
793 #define IA32_SPEC_CTRL_STIBP 0x00000002
794 #define IA32_SPEC_CTRL_SSBD 0x00000004
796 /* MSR IA32_PRED_CMD */
797 #define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL
799 /* MSR IA32_FLUSH_CMD */
800 #define IA32_FLUSH_CMD_L1D 0x00000001
802 /* MSR IA32_MCU_OPT_CTRL */
803 #define IA32_RNGDS_MITG_DIS 0x00000001
805 /* MSR IA32_HWP_CAPABILITIES */
806 #define IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(x) (((x) >> 0) & 0xff)
807 #define IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(x) (((x) >> 8) & 0xff)
808 #define IA32_HWP_CAPABILITIES_EFFICIENT_PERFORMANCE(x) (((x) >> 16) & 0xff)
809 #define IA32_HWP_CAPABILITIES_LOWEST_PERFORMANCE(x) (((x) >> 24) & 0xff)
811 /* MSR IA32_HWP_REQUEST */
812 #define IA32_HWP_REQUEST_MINIMUM_VALID (1ULL << 63)
813 #define IA32_HWP_REQUEST_MAXIMUM_VALID (1ULL << 62)
814 #define IA32_HWP_REQUEST_DESIRED_VALID (1ULL << 61)
815 #define IA32_HWP_REQUEST_EPP_VALID (1ULL << 60)
816 #define IA32_HWP_REQUEST_ACTIVITY_WINDOW_VALID (1ULL << 59)
817 #define IA32_HWP_REQUEST_PACKAGE_CONTROL (1ULL << 42)
818 #define IA32_HWP_ACTIVITY_WINDOW (0x3ffULL << 32)
819 #define IA32_HWP_REQUEST_ENERGY_PERFORMANCE_PREFERENCE (0xffULL << 24)
820 #define IA32_HWP_DESIRED_PERFORMANCE (0xffULL << 16)
821 #define IA32_HWP_REQUEST_MAXIMUM_PERFORMANCE (0xffULL << 8)
822 #define IA32_HWP_MINIMUM_PERFORMANCE (0xffULL << 0)
824 /* MSR IA32_ENERGY_PERF_BIAS */
825 #define IA32_ENERGY_PERF_BIAS_POLICY_HINT_MASK (0xfULL << 0)
830 #define PAT_UNCACHEABLE 0x00
831 #define PAT_WRITE_COMBINING 0x01
832 #define PAT_WRITE_THROUGH 0x04
833 #define PAT_WRITE_PROTECTED 0x05
834 #define PAT_WRITE_BACK 0x06
835 #define PAT_UNCACHED 0x07
836 #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i)))
837 #define PAT_MASK(i) PAT_VALUE(i, 0xff)
840 * Constants related to MTRRs
842 #define MTRR_UNCACHEABLE 0x00
843 #define MTRR_WRITE_COMBINING 0x01
844 #define MTRR_WRITE_THROUGH 0x04
845 #define MTRR_WRITE_PROTECTED 0x05
846 #define MTRR_WRITE_BACK 0x06
847 #define MTRR_N64K 8 /* numbers of fixed-size entries */
850 #define MTRR_CAP_WC 0x0000000000000400
851 #define MTRR_CAP_FIXED 0x0000000000000100
852 #define MTRR_CAP_VCNT 0x00000000000000ff
853 #define MTRR_DEF_ENABLE 0x0000000000000800
854 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400
855 #define MTRR_DEF_TYPE 0x00000000000000ff
856 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000
857 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff
858 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000
859 #define MTRR_PHYSMASK_VALID 0x0000000000000800
862 * Cyrix configuration registers, accessible as IO ports.
864 #define CCR0 0xc0 /* Configuration control register 0 */
865 #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
867 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
868 #define CCR0_A20M 0x04 /* Enables A20M# input pin */
869 #define CCR0_KEN 0x08 /* Enables KEN# input pin */
870 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
871 #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
873 #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
875 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
877 #define CCR1 0xc1 /* Configuration control register 1 */
878 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
879 #define CCR1_SMI 0x02 /* Enables SMM pins */
880 #define CCR1_SMAC 0x04 /* System management memory access */
881 #define CCR1_MMAC 0x08 /* Main memory access */
882 #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
883 #define CCR1_SM3 0x80 /* SMM address space address region 3 */
886 #define CCR2_WB 0x02 /* Enables WB cache interface pins */
887 #define CCR2_SADS 0x02 /* Slow ADS */
888 #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
889 #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
890 #define CCR2_WT1 0x10 /* WT region 1 */
891 #define CCR2_WPR1 0x10 /* Write-protect region 1 */
892 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering
894 #define CCR2_BWRT 0x40 /* Enables burst write cycles */
895 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
898 #define CCR3_SMILOCK 0x01 /* SMM register lock */
899 #define CCR3_NMI 0x02 /* Enables NMI during SMM */
900 #define CCR3_LINBRST 0x04 /* Linear address burst cycles */
901 #define CCR3_SMMMODE 0x08 /* SMM Mode */
902 #define CCR3_MAPEN0 0x10 /* Enables Map0 */
903 #define CCR3_MAPEN1 0x20 /* Enables Map1 */
904 #define CCR3_MAPEN2 0x40 /* Enables Map2 */
905 #define CCR3_MAPEN3 0x80 /* Enables Map3 */
908 #define CCR4_IOMASK 0x07
909 #define CCR4_MEM 0x08 /* Enables momory bypassing */
910 #define CCR4_DTE 0x10 /* Enables directory table entry cache */
911 #define CCR4_FASTFPE 0x20 /* Fast FPU exception */
912 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */
915 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
916 #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
917 #define CCR5_LBR1 0x10 /* Local bus region 1 */
918 #define CCR5_ARREN 0x20 /* Enables ARR region */
924 /* Performance Control Register (5x86 only). */
926 #define PCR0_RSTK 0x01 /* Enables return stack */
927 #define PCR0_BTB 0x02 /* Enables branch target buffer */
928 #define PCR0_LOOP 0x04 /* Enables loop */
929 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
931 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
932 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
933 #define PCR0_LSSER 0x80 /* Disable reorder */
935 /* Device Identification Registers */
940 * Machine Check register constants.
942 #define MCG_CAP_COUNT 0x000000ff
943 #define MCG_CAP_CTL_P 0x00000100
944 #define MCG_CAP_EXT_P 0x00000200
945 #define MCG_CAP_CMCI_P 0x00000400
946 #define MCG_CAP_TES_P 0x00000800
947 #define MCG_CAP_EXT_CNT 0x00ff0000
948 #define MCG_CAP_SER_P 0x01000000
949 #define MCG_STATUS_RIPV 0x00000001
950 #define MCG_STATUS_EIPV 0x00000002
951 #define MCG_STATUS_MCIP 0x00000004
952 #define MCG_CTL_ENABLE 0xffffffffffffffff
953 #define MCG_CTL_DISABLE 0x0000000000000000
954 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
955 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
956 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
957 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
958 #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */
959 #define MC_STATUS_MCA_ERROR 0x000000000000ffff
960 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000
961 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000
962 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */
963 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */
964 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */
965 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */
966 #define MC_STATUS_PCC 0x0200000000000000
967 #define MC_STATUS_ADDRV 0x0400000000000000
968 #define MC_STATUS_MISCV 0x0800000000000000
969 #define MC_STATUS_EN 0x1000000000000000
970 #define MC_STATUS_UC 0x2000000000000000
971 #define MC_STATUS_OVER 0x4000000000000000
972 #define MC_STATUS_VAL 0x8000000000000000
973 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */
974 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */
975 #define MC_CTL2_THRESHOLD 0x0000000000007fff
976 #define MC_CTL2_CMCI_EN 0x0000000040000000
977 #define MC_AMDNB_BANK 4
978 #define MC_MISC_AMD_VAL 0x8000000000000000 /* Counter presence valid */
979 #define MC_MISC_AMD_CNTP 0x4000000000000000 /* Counter present */
980 #define MC_MISC_AMD_LOCK 0x2000000000000000 /* Register locked */
981 #define MC_MISC_AMD_INTP 0x1000000000000000 /* Int. type can generate interrupts */
982 #define MC_MISC_AMD_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */
983 #define MC_MISC_AMD_LVT_SHIFT 52
984 #define MC_MISC_AMD_CNTEN 0x0008000000000000 /* Counter enabled */
985 #define MC_MISC_AMD_INT_MASK 0x0006000000000000 /* Interrupt type */
986 #define MC_MISC_AMD_INT_LVT 0x0002000000000000 /* Interrupt via Extended LVT */
987 #define MC_MISC_AMD_INT_SMI 0x0004000000000000 /* SMI */
988 #define MC_MISC_AMD_OVERFLOW 0x0001000000000000 /* Counter overflow */
989 #define MC_MISC_AMD_CNT_MASK 0x00000fff00000000 /* Counter value */
990 #define MC_MISC_AMD_CNT_SHIFT 32
991 #define MC_MISC_AMD_CNT_MAX 0xfff
992 #define MC_MISC_AMD_PTR_MASK 0x00000000ff000000 /* Pointer to additional registers */
993 #define MC_MISC_AMD_PTR_SHIFT 24
995 /* AMD Scalable MCA */
996 #define MSR_SMCA_MC0_CTL 0xc0002000
997 #define MSR_SMCA_MC0_STATUS 0xc0002001
998 #define MSR_SMCA_MC0_ADDR 0xc0002002
999 #define MSR_SMCA_MC0_MISC0 0xc0002003
1000 #define MSR_SMCA_MC_CTL(x) (MSR_SMCA_MC0_CTL + 0x10 * (x))
1001 #define MSR_SMCA_MC_STATUS(x) (MSR_SMCA_MC0_STATUS + 0x10 * (x))
1002 #define MSR_SMCA_MC_ADDR(x) (MSR_SMCA_MC0_ADDR + 0x10 * (x))
1003 #define MSR_SMCA_MC_MISC(x) (MSR_SMCA_MC0_MISC0 + 0x10 * (x))
1006 * The following four 3-byte registers control the non-cacheable regions.
1007 * These registers must be written as three separate bytes.
1009 * NCRx+0: A31-A24 of starting address
1010 * NCRx+1: A23-A16 of starting address
1011 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
1013 * The non-cacheable region's starting address must be aligned to the
1014 * size indicated by the NCR_SIZE_xx field.
1021 #define NCR_SIZE_0K 0
1022 #define NCR_SIZE_4K 1
1023 #define NCR_SIZE_8K 2
1024 #define NCR_SIZE_16K 3
1025 #define NCR_SIZE_32K 4
1026 #define NCR_SIZE_64K 5
1027 #define NCR_SIZE_128K 6
1028 #define NCR_SIZE_256K 7
1029 #define NCR_SIZE_512K 8
1030 #define NCR_SIZE_1M 9
1031 #define NCR_SIZE_2M 10
1032 #define NCR_SIZE_4M 11
1033 #define NCR_SIZE_8M 12
1034 #define NCR_SIZE_16M 13
1035 #define NCR_SIZE_32M 14
1036 #define NCR_SIZE_4G 15
1039 * The address region registers are used to specify the location and
1040 * size for the eight address regions.
1042 * ARRx + 0: A31-A24 of start address
1043 * ARRx + 1: A23-A16 of start address
1044 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
1055 #define ARR_SIZE_0K 0
1056 #define ARR_SIZE_4K 1
1057 #define ARR_SIZE_8K 2
1058 #define ARR_SIZE_16K 3
1059 #define ARR_SIZE_32K 4
1060 #define ARR_SIZE_64K 5
1061 #define ARR_SIZE_128K 6
1062 #define ARR_SIZE_256K 7
1063 #define ARR_SIZE_512K 8
1064 #define ARR_SIZE_1M 9
1065 #define ARR_SIZE_2M 10
1066 #define ARR_SIZE_4M 11
1067 #define ARR_SIZE_8M 12
1068 #define ARR_SIZE_16M 13
1069 #define ARR_SIZE_32M 14
1070 #define ARR_SIZE_4G 15
1073 * The region control registers specify the attributes associated with
1074 * the ARRx addres regions.
1085 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
1086 #define RCR_RCE 0x01 /* Enables caching for ARR7. */
1087 #define RCR_WWO 0x02 /* Weak write ordering. */
1088 #define RCR_WL 0x04 /* Weak locking. */
1089 #define RCR_WG 0x08 /* Write gathering. */
1090 #define RCR_WT 0x10 /* Write-through. */
1091 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
1093 /* AMD Write Allocate Top-Of-Memory and Control Register */
1094 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
1095 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
1096 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
1099 #define MSR_EFER 0xc0000080 /* extended features */
1100 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
1101 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
1102 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
1103 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
1104 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
1105 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
1106 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
1107 #define MSR_TSC_AUX 0xc0000103
1108 #define MSR_PERFEVSEL0 0xc0010000
1109 #define MSR_PERFEVSEL1 0xc0010001
1110 #define MSR_PERFEVSEL2 0xc0010002
1111 #define MSR_PERFEVSEL3 0xc0010003
1112 #define MSR_K7_PERFCTR0 0xc0010004
1113 #define MSR_K7_PERFCTR1 0xc0010005
1114 #define MSR_K7_PERFCTR2 0xc0010006
1115 #define MSR_K7_PERFCTR3 0xc0010007
1116 #define MSR_SYSCFG 0xc0010010
1117 #define MSR_HWCR 0xc0010015
1118 #define MSR_IORRBASE0 0xc0010016
1119 #define MSR_IORRMASK0 0xc0010017
1120 #define MSR_IORRBASE1 0xc0010018
1121 #define MSR_IORRMASK1 0xc0010019
1122 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
1123 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
1124 #define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */
1125 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
1126 #define MSR_MC0_CTL_MASK 0xc0010044
1127 #define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */
1128 #define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */
1129 #define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */
1130 #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */
1131 #define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */
1132 #define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */
1133 #define MSR_VM_CR 0xc0010114 /* SVM: feature control */
1134 #define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */
1135 #define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */
1136 #define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */
1137 #define MSR_LS_CFG 0xc0011020
1138 #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */
1140 /* MSR_VM_CR related */
1141 #define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */
1143 /* VIA ACE crypto featureset: for via_feature_rng */
1144 #define VIA_HAS_RNG 1 /* cpu has RNG */
1146 /* VIA ACE crypto featureset: for via_feature_xcrypt */
1147 #define VIA_HAS_AES 1 /* cpu has AES */
1148 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
1149 #define VIA_HAS_MM 4 /* cpu has RSA instructions */
1150 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
1152 /* Centaur Extended Feature flags */
1153 #define VIA_CPUID_HAS_RNG 0x000004
1154 #define VIA_CPUID_DO_RNG 0x000008
1155 #define VIA_CPUID_HAS_ACE 0x000040
1156 #define VIA_CPUID_DO_ACE 0x000080
1157 #define VIA_CPUID_HAS_ACE2 0x000100
1158 #define VIA_CPUID_DO_ACE2 0x000200
1159 #define VIA_CPUID_HAS_PHE 0x000400
1160 #define VIA_CPUID_DO_PHE 0x000800
1161 #define VIA_CPUID_HAS_PMM 0x001000
1162 #define VIA_CPUID_DO_PMM 0x002000
1164 /* VIA ACE xcrypt-* instruction context control options */
1165 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f
1166 #define VIA_CRYPT_CWLO_ALG_M 0x00000070
1167 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000
1168 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080
1169 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000
1170 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080
1171 #define VIA_CRYPT_CWLO_NORMAL 0x00000000
1172 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100
1173 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000
1174 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200
1175 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
1176 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
1177 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
1179 #endif /* !_MACHINE_SPECIALREG_H_ */