2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
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13 * 4. Neither the name of the University nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
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17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
33 #ifndef _MACHINE_SPECIALREG_H_
34 #define _MACHINE_SPECIALREG_H_
37 * Bits in 386 special registers:
39 #define CR0_PE 0x00000001 /* Protected mode Enable */
40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
43 #define CR0_PG 0x80000000 /* PaGing enable */
46 * Bits in 486 special registers:
48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
52 #define CR0_NW 0x20000000 /* Not Write-through */
53 #define CR0_CD 0x40000000 /* Cache Disable */
56 * Bits in PPro special registers
58 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
59 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
60 #define CR4_TSD 0x00000004 /* Time stamp disable */
61 #define CR4_DE 0x00000008 /* Debugging extensions */
62 #define CR4_PSE 0x00000010 /* Page size extensions */
63 #define CR4_PAE 0x00000020 /* Physical address extension */
64 #define CR4_MCE 0x00000040 /* Machine check enable */
65 #define CR4_PGE 0x00000080 /* Page global enable */
66 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
67 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
68 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
69 #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */
72 * Bits in AMD64 special registers. EFER is 64 bits wide.
74 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
75 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */
76 #define EFER_LMA 0x000000400 /* Long mode active (R) */
77 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
80 * Intel Extended Features registers
82 #define XCR0 0 /* XFEATURE_ENABLED_MASK register */
84 #define XFEATURE_ENABLED_X87 0x00000001
85 #define XFEATURE_ENABLED_SSE 0x00000002
86 #define XFEATURE_ENABLED_AVX 0x00000004
88 #define XFEATURE_AVX \
89 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX)
92 * CPUID instruction features register
94 #define CPUID_FPU 0x00000001
95 #define CPUID_VME 0x00000002
96 #define CPUID_DE 0x00000004
97 #define CPUID_PSE 0x00000008
98 #define CPUID_TSC 0x00000010
99 #define CPUID_MSR 0x00000020
100 #define CPUID_PAE 0x00000040
101 #define CPUID_MCE 0x00000080
102 #define CPUID_CX8 0x00000100
103 #define CPUID_APIC 0x00000200
104 #define CPUID_B10 0x00000400
105 #define CPUID_SEP 0x00000800
106 #define CPUID_MTRR 0x00001000
107 #define CPUID_PGE 0x00002000
108 #define CPUID_MCA 0x00004000
109 #define CPUID_CMOV 0x00008000
110 #define CPUID_PAT 0x00010000
111 #define CPUID_PSE36 0x00020000
112 #define CPUID_PSN 0x00040000
113 #define CPUID_CLFSH 0x00080000
114 #define CPUID_B20 0x00100000
115 #define CPUID_DS 0x00200000
116 #define CPUID_ACPI 0x00400000
117 #define CPUID_MMX 0x00800000
118 #define CPUID_FXSR 0x01000000
119 #define CPUID_SSE 0x02000000
120 #define CPUID_XMM 0x02000000
121 #define CPUID_SSE2 0x04000000
122 #define CPUID_SS 0x08000000
123 #define CPUID_HTT 0x10000000
124 #define CPUID_TM 0x20000000
125 #define CPUID_IA64 0x40000000
126 #define CPUID_PBE 0x80000000
128 #define CPUID2_SSE3 0x00000001
129 #define CPUID2_PCLMULQDQ 0x00000002
130 #define CPUID2_DTES64 0x00000004
131 #define CPUID2_MON 0x00000008
132 #define CPUID2_DS_CPL 0x00000010
133 #define CPUID2_VMX 0x00000020
134 #define CPUID2_SMX 0x00000040
135 #define CPUID2_EST 0x00000080
136 #define CPUID2_TM2 0x00000100
137 #define CPUID2_SSSE3 0x00000200
138 #define CPUID2_CNXTID 0x00000400
139 #define CPUID2_FMA 0x00001000
140 #define CPUID2_CX16 0x00002000
141 #define CPUID2_XTPR 0x00004000
142 #define CPUID2_PDCM 0x00008000
143 #define CPUID2_PCID 0x00020000
144 #define CPUID2_DCA 0x00040000
145 #define CPUID2_SSE41 0x00080000
146 #define CPUID2_SSE42 0x00100000
147 #define CPUID2_X2APIC 0x00200000
148 #define CPUID2_MOVBE 0x00400000
149 #define CPUID2_POPCNT 0x00800000
150 #define CPUID2_TSCDLT 0x01000000
151 #define CPUID2_AESNI 0x02000000
152 #define CPUID2_XSAVE 0x04000000
153 #define CPUID2_OSXSAVE 0x08000000
154 #define CPUID2_AVX 0x10000000
155 #define CPUID2_F16C 0x20000000
156 #define CPUID2_HV 0x80000000
159 * Important bits in the Thermal and Power Management flags
160 * CPUID.6 EAX and ECX.
162 #define CPUTPM1_SENSOR 0x00000001
163 #define CPUTPM1_TURBO 0x00000002
164 #define CPUTPM1_ARAT 0x00000004
165 #define CPUTPM2_EFFREQ 0x00000001
168 * Important bits in the AMD extended cpuid flags
170 #define AMDID_SYSCALL 0x00000800
171 #define AMDID_MP 0x00080000
172 #define AMDID_NX 0x00100000
173 #define AMDID_EXT_MMX 0x00400000
174 #define AMDID_FFXSR 0x01000000
175 #define AMDID_PAGE1GB 0x04000000
176 #define AMDID_RDTSCP 0x08000000
177 #define AMDID_LM 0x20000000
178 #define AMDID_EXT_3DNOW 0x40000000
179 #define AMDID_3DNOW 0x80000000
181 #define AMDID2_LAHF 0x00000001
182 #define AMDID2_CMP 0x00000002
183 #define AMDID2_SVM 0x00000004
184 #define AMDID2_EXT_APIC 0x00000008
185 #define AMDID2_CR8 0x00000010
186 #define AMDID2_ABM 0x00000020
187 #define AMDID2_SSE4A 0x00000040
188 #define AMDID2_MAS 0x00000080
189 #define AMDID2_PREFETCH 0x00000100
190 #define AMDID2_OSVW 0x00000200
191 #define AMDID2_IBS 0x00000400
192 #define AMDID2_XOP 0x00000800
193 #define AMDID2_SKINIT 0x00001000
194 #define AMDID2_WDT 0x00002000
195 #define AMDID2_LWP 0x00008000
196 #define AMDID2_FMA4 0x00010000
197 #define AMDID2_NODE_ID 0x00080000
198 #define AMDID2_TBM 0x00200000
199 #define AMDID2_TOPOLOGY 0x00400000
202 * CPUID instruction 1 eax info
204 #define CPUID_STEPPING 0x0000000f
205 #define CPUID_MODEL 0x000000f0
206 #define CPUID_FAMILY 0x00000f00
207 #define CPUID_EXT_MODEL 0x000f0000
208 #define CPUID_EXT_FAMILY 0x0ff00000
210 #define CPUID_TO_MODEL(id) \
211 ((((id) & CPUID_MODEL) >> 4) | \
212 ((((id) & CPUID_FAMILY) >= 0x600) ? \
213 (((id) & CPUID_EXT_MODEL) >> 12) : 0))
214 #define CPUID_TO_FAMILY(id) \
215 ((((id) & CPUID_FAMILY) >> 8) + \
216 ((((id) & CPUID_FAMILY) == 0xf00) ? \
217 (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
219 #define CPUID_TO_MODEL(id) \
220 ((((id) & CPUID_MODEL) >> 4) | \
221 (((id) & CPUID_EXT_MODEL) >> 12))
222 #define CPUID_TO_FAMILY(id) \
223 ((((id) & CPUID_FAMILY) >> 8) + \
224 (((id) & CPUID_EXT_FAMILY) >> 20))
228 * CPUID instruction 1 ebx info
230 #define CPUID_BRAND_INDEX 0x000000ff
231 #define CPUID_CLFUSH_SIZE 0x0000ff00
232 #define CPUID_HTT_CORES 0x00ff0000
233 #define CPUID_LOCAL_APIC_ID 0xff000000
236 * CPUID instruction 6 ecx info
238 #define CPUID_PERF_STAT 0x00000001
239 #define CPUID_PERF_BIAS 0x00000008
242 * CPUID instruction 0xb ebx info.
244 #define CPUID_TYPE_INVAL 0
245 #define CPUID_TYPE_SMT 1
246 #define CPUID_TYPE_CORE 2
249 * AMD extended function 8000_0007h edx info
251 #define AMDPM_TS 0x00000001
252 #define AMDPM_FID 0x00000002
253 #define AMDPM_VID 0x00000004
254 #define AMDPM_TTP 0x00000008
255 #define AMDPM_TM 0x00000010
256 #define AMDPM_STC 0x00000020
257 #define AMDPM_100MHZ_STEPS 0x00000040
258 #define AMDPM_HW_PSTATE 0x00000080
259 #define AMDPM_TSC_INVARIANT 0x00000100
260 #define AMDPM_CPB 0x00000200
263 * AMD extended function 8000_0008h ecx info
265 #define AMDID_CMP_CORES 0x000000ff
266 #define AMDID_COREID_SIZE 0x0000f000
267 #define AMDID_COREID_SIZE_SHIFT 12
270 * CPUID manufacturers identifiers
272 #define AMD_VENDOR_ID "AuthenticAMD"
273 #define CENTAUR_VENDOR_ID "CentaurHauls"
274 #define CYRIX_VENDOR_ID "CyrixInstead"
275 #define INTEL_VENDOR_ID "GenuineIntel"
276 #define NEXGEN_VENDOR_ID "NexGenDriven"
277 #define NSC_VENDOR_ID "Geode by NSC"
278 #define RISE_VENDOR_ID "RiseRiseRise"
279 #define SIS_VENDOR_ID "SiS SiS SiS "
280 #define TRANSMETA_VENDOR_ID "GenuineTMx86"
281 #define UMC_VENDOR_ID "UMC UMC UMC "
284 * Model-specific registers for the i386 family
286 #define MSR_P5_MC_ADDR 0x000
287 #define MSR_P5_MC_TYPE 0x001
288 #define MSR_TSC 0x010
289 #define MSR_P5_CESR 0x011
290 #define MSR_P5_CTR0 0x012
291 #define MSR_P5_CTR1 0x013
292 #define MSR_IA32_PLATFORM_ID 0x017
293 #define MSR_APICBASE 0x01b
294 #define MSR_EBL_CR_POWERON 0x02a
295 #define MSR_TEST_CTL 0x033
296 #define MSR_BIOS_UPDT_TRIG 0x079
297 #define MSR_BBL_CR_D0 0x088
298 #define MSR_BBL_CR_D1 0x089
299 #define MSR_BBL_CR_D2 0x08a
300 #define MSR_BIOS_SIGN 0x08b
301 #define MSR_PERFCTR0 0x0c1
302 #define MSR_PERFCTR1 0x0c2
303 #define MSR_MPERF 0x0e7
304 #define MSR_APERF 0x0e8
305 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
306 #define MSR_MTRRcap 0x0fe
307 #define MSR_BBL_CR_ADDR 0x116
308 #define MSR_BBL_CR_DECC 0x118
309 #define MSR_BBL_CR_CTL 0x119
310 #define MSR_BBL_CR_TRIG 0x11a
311 #define MSR_BBL_CR_BUSY 0x11b
312 #define MSR_BBL_CR_CTL3 0x11e
313 #define MSR_SYSENTER_CS_MSR 0x174
314 #define MSR_SYSENTER_ESP_MSR 0x175
315 #define MSR_SYSENTER_EIP_MSR 0x176
316 #define MSR_MCG_CAP 0x179
317 #define MSR_MCG_STATUS 0x17a
318 #define MSR_MCG_CTL 0x17b
319 #define MSR_EVNTSEL0 0x186
320 #define MSR_EVNTSEL1 0x187
321 #define MSR_THERM_CONTROL 0x19a
322 #define MSR_THERM_INTERRUPT 0x19b
323 #define MSR_THERM_STATUS 0x19c
324 #define MSR_IA32_MISC_ENABLE 0x1a0
325 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2
326 #define MSR_DEBUGCTLMSR 0x1d9
327 #define MSR_LASTBRANCHFROMIP 0x1db
328 #define MSR_LASTBRANCHTOIP 0x1dc
329 #define MSR_LASTINTFROMIP 0x1dd
330 #define MSR_LASTINTTOIP 0x1de
331 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
332 #define MSR_MTRRVarBase 0x200
333 #define MSR_MTRR64kBase 0x250
334 #define MSR_MTRR16kBase 0x258
335 #define MSR_MTRR4kBase 0x268
336 #define MSR_PAT 0x277
337 #define MSR_MC0_CTL2 0x280
338 #define MSR_MTRRdefType 0x2ff
339 #define MSR_MC0_CTL 0x400
340 #define MSR_MC0_STATUS 0x401
341 #define MSR_MC0_ADDR 0x402
342 #define MSR_MC0_MISC 0x403
343 #define MSR_MC1_CTL 0x404
344 #define MSR_MC1_STATUS 0x405
345 #define MSR_MC1_ADDR 0x406
346 #define MSR_MC1_MISC 0x407
347 #define MSR_MC2_CTL 0x408
348 #define MSR_MC2_STATUS 0x409
349 #define MSR_MC2_ADDR 0x40a
350 #define MSR_MC2_MISC 0x40b
351 #define MSR_MC3_CTL 0x40c
352 #define MSR_MC3_STATUS 0x40d
353 #define MSR_MC3_ADDR 0x40e
354 #define MSR_MC3_MISC 0x40f
355 #define MSR_MC4_CTL 0x410
356 #define MSR_MC4_STATUS 0x411
357 #define MSR_MC4_ADDR 0x412
358 #define MSR_MC4_MISC 0x413
361 * Constants related to MSR's.
363 #define APICBASE_RESERVED 0x000006ff
364 #define APICBASE_BSP 0x00000100
365 #define APICBASE_ENABLED 0x00000800
366 #define APICBASE_ADDRESS 0xfffff000
371 #define PAT_UNCACHEABLE 0x00
372 #define PAT_WRITE_COMBINING 0x01
373 #define PAT_WRITE_THROUGH 0x04
374 #define PAT_WRITE_PROTECTED 0x05
375 #define PAT_WRITE_BACK 0x06
376 #define PAT_UNCACHED 0x07
377 #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i)))
378 #define PAT_MASK(i) PAT_VALUE(i, 0xff)
381 * Constants related to MTRRs
383 #define MTRR_UNCACHEABLE 0x00
384 #define MTRR_WRITE_COMBINING 0x01
385 #define MTRR_WRITE_THROUGH 0x04
386 #define MTRR_WRITE_PROTECTED 0x05
387 #define MTRR_WRITE_BACK 0x06
388 #define MTRR_N64K 8 /* numbers of fixed-size entries */
391 #define MTRR_CAP_WC 0x0000000000000400
392 #define MTRR_CAP_FIXED 0x0000000000000100
393 #define MTRR_CAP_VCNT 0x00000000000000ff
394 #define MTRR_DEF_ENABLE 0x0000000000000800
395 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400
396 #define MTRR_DEF_TYPE 0x00000000000000ff
397 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000
398 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff
399 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000
400 #define MTRR_PHYSMASK_VALID 0x0000000000000800
403 * Cyrix configuration registers, accessible as IO ports.
405 #define CCR0 0xc0 /* Configuration control register 0 */
406 #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
408 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
409 #define CCR0_A20M 0x04 /* Enables A20M# input pin */
410 #define CCR0_KEN 0x08 /* Enables KEN# input pin */
411 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
412 #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
414 #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
416 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
418 #define CCR1 0xc1 /* Configuration control register 1 */
419 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
420 #define CCR1_SMI 0x02 /* Enables SMM pins */
421 #define CCR1_SMAC 0x04 /* System management memory access */
422 #define CCR1_MMAC 0x08 /* Main memory access */
423 #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
424 #define CCR1_SM3 0x80 /* SMM address space address region 3 */
427 #define CCR2_WB 0x02 /* Enables WB cache interface pins */
428 #define CCR2_SADS 0x02 /* Slow ADS */
429 #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
430 #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
431 #define CCR2_WT1 0x10 /* WT region 1 */
432 #define CCR2_WPR1 0x10 /* Write-protect region 1 */
433 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering
435 #define CCR2_BWRT 0x40 /* Enables burst write cycles */
436 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
439 #define CCR3_SMILOCK 0x01 /* SMM register lock */
440 #define CCR3_NMI 0x02 /* Enables NMI during SMM */
441 #define CCR3_LINBRST 0x04 /* Linear address burst cycles */
442 #define CCR3_SMMMODE 0x08 /* SMM Mode */
443 #define CCR3_MAPEN0 0x10 /* Enables Map0 */
444 #define CCR3_MAPEN1 0x20 /* Enables Map1 */
445 #define CCR3_MAPEN2 0x40 /* Enables Map2 */
446 #define CCR3_MAPEN3 0x80 /* Enables Map3 */
449 #define CCR4_IOMASK 0x07
450 #define CCR4_MEM 0x08 /* Enables momory bypassing */
451 #define CCR4_DTE 0x10 /* Enables directory table entry cache */
452 #define CCR4_FASTFPE 0x20 /* Fast FPU exception */
453 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */
456 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
457 #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
458 #define CCR5_LBR1 0x10 /* Local bus region 1 */
459 #define CCR5_ARREN 0x20 /* Enables ARR region */
465 /* Performance Control Register (5x86 only). */
467 #define PCR0_RSTK 0x01 /* Enables return stack */
468 #define PCR0_BTB 0x02 /* Enables branch target buffer */
469 #define PCR0_LOOP 0x04 /* Enables loop */
470 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
472 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
473 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
474 #define PCR0_LSSER 0x80 /* Disable reorder */
476 /* Device Identification Registers */
481 * Machine Check register constants.
483 #define MCG_CAP_COUNT 0x000000ff
484 #define MCG_CAP_CTL_P 0x00000100
485 #define MCG_CAP_EXT_P 0x00000200
486 #define MCG_CAP_CMCI_P 0x00000400
487 #define MCG_CAP_TES_P 0x00000800
488 #define MCG_CAP_EXT_CNT 0x00ff0000
489 #define MCG_CAP_SER_P 0x01000000
490 #define MCG_STATUS_RIPV 0x00000001
491 #define MCG_STATUS_EIPV 0x00000002
492 #define MCG_STATUS_MCIP 0x00000004
493 #define MCG_CTL_ENABLE 0xffffffffffffffff
494 #define MCG_CTL_DISABLE 0x0000000000000000
495 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
496 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
497 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
498 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
499 #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */
500 #define MC_STATUS_MCA_ERROR 0x000000000000ffff
501 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000
502 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000
503 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */
504 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */
505 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */
506 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */
507 #define MC_STATUS_PCC 0x0200000000000000
508 #define MC_STATUS_ADDRV 0x0400000000000000
509 #define MC_STATUS_MISCV 0x0800000000000000
510 #define MC_STATUS_EN 0x1000000000000000
511 #define MC_STATUS_UC 0x2000000000000000
512 #define MC_STATUS_OVER 0x4000000000000000
513 #define MC_STATUS_VAL 0x8000000000000000
514 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */
515 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */
516 #define MC_CTL2_THRESHOLD 0x0000000000007fff
517 #define MC_CTL2_CMCI_EN 0x0000000040000000
520 * The following four 3-byte registers control the non-cacheable regions.
521 * These registers must be written as three separate bytes.
523 * NCRx+0: A31-A24 of starting address
524 * NCRx+1: A23-A16 of starting address
525 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
527 * The non-cacheable region's starting address must be aligned to the
528 * size indicated by the NCR_SIZE_xx field.
535 #define NCR_SIZE_0K 0
536 #define NCR_SIZE_4K 1
537 #define NCR_SIZE_8K 2
538 #define NCR_SIZE_16K 3
539 #define NCR_SIZE_32K 4
540 #define NCR_SIZE_64K 5
541 #define NCR_SIZE_128K 6
542 #define NCR_SIZE_256K 7
543 #define NCR_SIZE_512K 8
544 #define NCR_SIZE_1M 9
545 #define NCR_SIZE_2M 10
546 #define NCR_SIZE_4M 11
547 #define NCR_SIZE_8M 12
548 #define NCR_SIZE_16M 13
549 #define NCR_SIZE_32M 14
550 #define NCR_SIZE_4G 15
553 * The address region registers are used to specify the location and
554 * size for the eight address regions.
556 * ARRx + 0: A31-A24 of start address
557 * ARRx + 1: A23-A16 of start address
558 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
569 #define ARR_SIZE_0K 0
570 #define ARR_SIZE_4K 1
571 #define ARR_SIZE_8K 2
572 #define ARR_SIZE_16K 3
573 #define ARR_SIZE_32K 4
574 #define ARR_SIZE_64K 5
575 #define ARR_SIZE_128K 6
576 #define ARR_SIZE_256K 7
577 #define ARR_SIZE_512K 8
578 #define ARR_SIZE_1M 9
579 #define ARR_SIZE_2M 10
580 #define ARR_SIZE_4M 11
581 #define ARR_SIZE_8M 12
582 #define ARR_SIZE_16M 13
583 #define ARR_SIZE_32M 14
584 #define ARR_SIZE_4G 15
587 * The region control registers specify the attributes associated with
588 * the ARRx addres regions.
599 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
600 #define RCR_RCE 0x01 /* Enables caching for ARR7. */
601 #define RCR_WWO 0x02 /* Weak write ordering. */
602 #define RCR_WL 0x04 /* Weak locking. */
603 #define RCR_WG 0x08 /* Write gathering. */
604 #define RCR_WT 0x10 /* Write-through. */
605 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
607 /* AMD Write Allocate Top-Of-Memory and Control Register */
608 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
609 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
610 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
613 #define MSR_EFER 0xc0000080 /* extended features */
614 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
615 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
616 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
617 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
618 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
619 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
620 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
621 #define MSR_PERFEVSEL0 0xc0010000
622 #define MSR_PERFEVSEL1 0xc0010001
623 #define MSR_PERFEVSEL2 0xc0010002
624 #define MSR_PERFEVSEL3 0xc0010003
627 #define MSR_PERFCTR0 0xc0010004
628 #define MSR_PERFCTR1 0xc0010005
629 #define MSR_PERFCTR2 0xc0010006
630 #define MSR_PERFCTR3 0xc0010007
631 #define MSR_SYSCFG 0xc0010010
632 #define MSR_HWCR 0xc0010015
633 #define MSR_IORRBASE0 0xc0010016
634 #define MSR_IORRMASK0 0xc0010017
635 #define MSR_IORRBASE1 0xc0010018
636 #define MSR_IORRMASK1 0xc0010019
637 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
638 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
639 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
640 #define MSR_MC0_CTL_MASK 0xc0010044
642 /* VIA ACE crypto featureset: for via_feature_rng */
643 #define VIA_HAS_RNG 1 /* cpu has RNG */
645 /* VIA ACE crypto featureset: for via_feature_xcrypt */
646 #define VIA_HAS_AES 1 /* cpu has AES */
647 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
648 #define VIA_HAS_MM 4 /* cpu has RSA instructions */
649 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
651 /* Centaur Extended Feature flags */
652 #define VIA_CPUID_HAS_RNG 0x000004
653 #define VIA_CPUID_DO_RNG 0x000008
654 #define VIA_CPUID_HAS_ACE 0x000040
655 #define VIA_CPUID_DO_ACE 0x000080
656 #define VIA_CPUID_HAS_ACE2 0x000100
657 #define VIA_CPUID_DO_ACE2 0x000200
658 #define VIA_CPUID_HAS_PHE 0x000400
659 #define VIA_CPUID_DO_PHE 0x000800
660 #define VIA_CPUID_HAS_PMM 0x001000
661 #define VIA_CPUID_DO_PMM 0x002000
663 /* VIA ACE xcrypt-* instruction context control options */
664 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f
665 #define VIA_CRYPT_CWLO_ALG_M 0x00000070
666 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000
667 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080
668 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000
669 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080
670 #define VIA_CRYPT_CWLO_NORMAL 0x00000000
671 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100
672 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000
673 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200
674 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
675 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
676 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
678 #endif /* !_MACHINE_SPECIALREG_H_ */