2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1991 The Regents of the University of California.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the University nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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31 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
35 #ifndef _MACHINE_SPECIALREG_H_
36 #define _MACHINE_SPECIALREG_H_
39 * Bits in 386 special registers:
41 #define CR0_PE 0x00000001 /* Protected mode Enable */
42 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
43 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
44 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
45 #define CR0_PG 0x80000000 /* PaGing enable */
48 * Bits in 486 special registers:
50 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
51 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
53 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
54 #define CR0_NW 0x20000000 /* Not Write-through */
55 #define CR0_CD 0x40000000 /* Cache Disable */
57 #define CR3_PCID_SAVE 0x8000000000000000
58 #define CR3_PCID_MASK 0xfff
61 * Bits in PPro special registers
63 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
64 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
65 #define CR4_TSD 0x00000004 /* Time stamp disable */
66 #define CR4_DE 0x00000008 /* Debugging extensions */
67 #define CR4_PSE 0x00000010 /* Page size extensions */
68 #define CR4_PAE 0x00000020 /* Physical address extension */
69 #define CR4_MCE 0x00000040 /* Machine check enable */
70 #define CR4_PGE 0x00000080 /* Page global enable */
71 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
72 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
73 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
74 #define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */
75 #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */
76 #define CR4_PCIDE 0x00020000 /* Enable Context ID */
77 #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */
78 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */
79 #define CR4_SMAP 0x00200000 /* Supervisor-Mode Access Prevention */
82 * Bits in AMD64 special registers. EFER is 64 bits wide.
84 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
85 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */
86 #define EFER_LMA 0x000000400 /* Long mode active (R) */
87 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
88 #define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */
89 #define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */
90 #define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */
91 #define EFER_TCE 0x000008000 /* Translation Cache Extension */
94 * Intel Extended Features registers
96 #define XCR0 0 /* XFEATURE_ENABLED_MASK register */
98 #define XFEATURE_ENABLED_X87 0x00000001
99 #define XFEATURE_ENABLED_SSE 0x00000002
100 #define XFEATURE_ENABLED_YMM_HI128 0x00000004
101 #define XFEATURE_ENABLED_AVX XFEATURE_ENABLED_YMM_HI128
102 #define XFEATURE_ENABLED_BNDREGS 0x00000008
103 #define XFEATURE_ENABLED_BNDCSR 0x00000010
104 #define XFEATURE_ENABLED_OPMASK 0x00000020
105 #define XFEATURE_ENABLED_ZMM_HI256 0x00000040
106 #define XFEATURE_ENABLED_HI16_ZMM 0x00000080
108 #define XFEATURE_AVX \
109 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX)
110 #define XFEATURE_AVX512 \
111 (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 | \
112 XFEATURE_ENABLED_HI16_ZMM)
113 #define XFEATURE_MPX \
114 (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR)
117 * CPUID instruction features register
119 #define CPUID_FPU 0x00000001
120 #define CPUID_VME 0x00000002
121 #define CPUID_DE 0x00000004
122 #define CPUID_PSE 0x00000008
123 #define CPUID_TSC 0x00000010
124 #define CPUID_MSR 0x00000020
125 #define CPUID_PAE 0x00000040
126 #define CPUID_MCE 0x00000080
127 #define CPUID_CX8 0x00000100
128 #define CPUID_APIC 0x00000200
129 #define CPUID_B10 0x00000400
130 #define CPUID_SEP 0x00000800
131 #define CPUID_MTRR 0x00001000
132 #define CPUID_PGE 0x00002000
133 #define CPUID_MCA 0x00004000
134 #define CPUID_CMOV 0x00008000
135 #define CPUID_PAT 0x00010000
136 #define CPUID_PSE36 0x00020000
137 #define CPUID_PSN 0x00040000
138 #define CPUID_CLFSH 0x00080000
139 #define CPUID_B20 0x00100000
140 #define CPUID_DS 0x00200000
141 #define CPUID_ACPI 0x00400000
142 #define CPUID_MMX 0x00800000
143 #define CPUID_FXSR 0x01000000
144 #define CPUID_SSE 0x02000000
145 #define CPUID_XMM 0x02000000
146 #define CPUID_SSE2 0x04000000
147 #define CPUID_SS 0x08000000
148 #define CPUID_HTT 0x10000000
149 #define CPUID_TM 0x20000000
150 #define CPUID_IA64 0x40000000
151 #define CPUID_PBE 0x80000000
153 #define CPUID2_SSE3 0x00000001
154 #define CPUID2_PCLMULQDQ 0x00000002
155 #define CPUID2_DTES64 0x00000004
156 #define CPUID2_MON 0x00000008
157 #define CPUID2_DS_CPL 0x00000010
158 #define CPUID2_VMX 0x00000020
159 #define CPUID2_SMX 0x00000040
160 #define CPUID2_EST 0x00000080
161 #define CPUID2_TM2 0x00000100
162 #define CPUID2_SSSE3 0x00000200
163 #define CPUID2_CNXTID 0x00000400
164 #define CPUID2_SDBG 0x00000800
165 #define CPUID2_FMA 0x00001000
166 #define CPUID2_CX16 0x00002000
167 #define CPUID2_XTPR 0x00004000
168 #define CPUID2_PDCM 0x00008000
169 #define CPUID2_PCID 0x00020000
170 #define CPUID2_DCA 0x00040000
171 #define CPUID2_SSE41 0x00080000
172 #define CPUID2_SSE42 0x00100000
173 #define CPUID2_X2APIC 0x00200000
174 #define CPUID2_MOVBE 0x00400000
175 #define CPUID2_POPCNT 0x00800000
176 #define CPUID2_TSCDLT 0x01000000
177 #define CPUID2_AESNI 0x02000000
178 #define CPUID2_XSAVE 0x04000000
179 #define CPUID2_OSXSAVE 0x08000000
180 #define CPUID2_AVX 0x10000000
181 #define CPUID2_F16C 0x20000000
182 #define CPUID2_RDRAND 0x40000000
183 #define CPUID2_HV 0x80000000
186 * Important bits in the Thermal and Power Management flags
187 * CPUID.6 EAX and ECX.
189 #define CPUTPM1_SENSOR 0x00000001
190 #define CPUTPM1_TURBO 0x00000002
191 #define CPUTPM1_ARAT 0x00000004
192 #define CPUTPM2_EFFREQ 0x00000001
194 /* Intel Processor Trace CPUID. */
197 #define CPUPT_CR3 (1 << 0) /* CR3 Filtering Support */
198 #define CPUPT_PSB (1 << 1) /* Configurable PSB and Cycle-Accurate Mode Supported */
199 #define CPUPT_IPF (1 << 2) /* IP Filtering and TraceStop supported */
200 #define CPUPT_MTC (1 << 3) /* MTC Supported */
201 #define CPUPT_PRW (1 << 4) /* PTWRITE Supported */
202 #define CPUPT_PWR (1 << 5) /* Power Event Trace Supported */
205 #define CPUPT_TOPA (1 << 0) /* ToPA Output Supported */
206 #define CPUPT_TOPA_MULTI (1 << 1) /* ToPA Tables Allow Multiple Output Entries */
207 #define CPUPT_SINGLE (1 << 2) /* Single-Range Output Supported */
208 #define CPUPT_TT_OUT (1 << 3) /* Output to Trace Transport Subsystem Supported */
209 #define CPUPT_LINEAR_IP (1 << 31) /* IP Payloads are Linear IP, otherwise IP is effective */
212 #define CPUPT_NADDR_S 0 /* Number of Address Ranges */
213 #define CPUPT_NADDR_M (0x7 << CPUPT_NADDR_S)
214 #define CPUPT_MTC_BITMAP_S 16 /* Bitmap of supported MTC Period Encodings */
215 #define CPUPT_MTC_BITMAP_M (0xffff << CPUPT_MTC_BITMAP_S)
218 #define CPUPT_CT_BITMAP_S 0 /* Bitmap of supported Cycle Threshold values */
219 #define CPUPT_CT_BITMAP_M (0xffff << CPUPT_CT_BITMAP_S)
220 #define CPUPT_PFE_BITMAP_S 16 /* Bitmap of supported Configurable PSB Frequency encoding */
221 #define CPUPT_PFE_BITMAP_M (0xffff << CPUPT_PFE_BITMAP_S)
224 * Important bits in the AMD extended cpuid flags
226 #define AMDID_SYSCALL 0x00000800
227 #define AMDID_MP 0x00080000
228 #define AMDID_NX 0x00100000
229 #define AMDID_EXT_MMX 0x00400000
230 #define AMDID_FFXSR 0x02000000
231 #define AMDID_PAGE1GB 0x04000000
232 #define AMDID_RDTSCP 0x08000000
233 #define AMDID_LM 0x20000000
234 #define AMDID_EXT_3DNOW 0x40000000
235 #define AMDID_3DNOW 0x80000000
237 #define AMDID2_LAHF 0x00000001
238 #define AMDID2_CMP 0x00000002
239 #define AMDID2_SVM 0x00000004
240 #define AMDID2_EXT_APIC 0x00000008
241 #define AMDID2_CR8 0x00000010
242 #define AMDID2_ABM 0x00000020
243 #define AMDID2_SSE4A 0x00000040
244 #define AMDID2_MAS 0x00000080
245 #define AMDID2_PREFETCH 0x00000100
246 #define AMDID2_OSVW 0x00000200
247 #define AMDID2_IBS 0x00000400
248 #define AMDID2_XOP 0x00000800
249 #define AMDID2_SKINIT 0x00001000
250 #define AMDID2_WDT 0x00002000
251 #define AMDID2_LWP 0x00008000
252 #define AMDID2_FMA4 0x00010000
253 #define AMDID2_TCE 0x00020000
254 #define AMDID2_NODE_ID 0x00080000
255 #define AMDID2_TBM 0x00200000
256 #define AMDID2_TOPOLOGY 0x00400000
257 #define AMDID2_PCXC 0x00800000
258 #define AMDID2_PNXC 0x01000000
259 #define AMDID2_DBE 0x04000000
260 #define AMDID2_PTSC 0x08000000
261 #define AMDID2_PTSCEL2I 0x10000000
262 #define AMDID2_MWAITX 0x20000000
265 * CPUID instruction 1 eax info
267 #define CPUID_STEPPING 0x0000000f
268 #define CPUID_MODEL 0x000000f0
269 #define CPUID_FAMILY 0x00000f00
270 #define CPUID_EXT_MODEL 0x000f0000
271 #define CPUID_EXT_FAMILY 0x0ff00000
273 #define CPUID_TO_MODEL(id) \
274 ((((id) & CPUID_MODEL) >> 4) | \
275 ((((id) & CPUID_FAMILY) >= 0x600) ? \
276 (((id) & CPUID_EXT_MODEL) >> 12) : 0))
277 #define CPUID_TO_FAMILY(id) \
278 ((((id) & CPUID_FAMILY) >> 8) + \
279 ((((id) & CPUID_FAMILY) == 0xf00) ? \
280 (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
282 #define CPUID_TO_MODEL(id) \
283 ((((id) & CPUID_MODEL) >> 4) | \
284 (((id) & CPUID_EXT_MODEL) >> 12))
285 #define CPUID_TO_FAMILY(id) \
286 ((((id) & CPUID_FAMILY) >> 8) + \
287 (((id) & CPUID_EXT_FAMILY) >> 20))
291 * CPUID instruction 1 ebx info
293 #define CPUID_BRAND_INDEX 0x000000ff
294 #define CPUID_CLFUSH_SIZE 0x0000ff00
295 #define CPUID_HTT_CORES 0x00ff0000
296 #define CPUID_LOCAL_APIC_ID 0xff000000
299 * CPUID instruction 5 info
301 #define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */
302 #define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */
303 #define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */
304 #define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */
307 * MWAIT cpu power states. Lower 4 bits are sub-states.
309 #define MWAIT_C0 0xf0
310 #define MWAIT_C1 0x00
311 #define MWAIT_C2 0x10
312 #define MWAIT_C3 0x20
313 #define MWAIT_C4 0x30
318 /* Interrupt breaks MWAIT even when masked. */
319 #define MWAIT_INTRBREAK 0x00000001
322 * CPUID instruction 6 ecx info
324 #define CPUID_PERF_STAT 0x00000001
325 #define CPUID_PERF_BIAS 0x00000008
328 * CPUID instruction 0xb ebx info.
330 #define CPUID_TYPE_INVAL 0
331 #define CPUID_TYPE_SMT 1
332 #define CPUID_TYPE_CORE 2
335 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1
337 #define CPUID_EXTSTATE_XSAVEOPT 0x00000001
338 #define CPUID_EXTSTATE_XSAVEC 0x00000002
339 #define CPUID_EXTSTATE_XINUSE 0x00000004
340 #define CPUID_EXTSTATE_XSAVES 0x00000008
343 * AMD extended function 8000_0007h ebx info
345 #define AMDRAS_MCA_OF_RECOV 0x00000001
346 #define AMDRAS_SUCCOR 0x00000002
347 #define AMDRAS_HW_ASSERT 0x00000004
348 #define AMDRAS_SCALABLE_MCA 0x00000008
349 #define AMDRAS_PFEH_SUPPORT 0x00000010
352 * AMD extended function 8000_0007h edx info
354 #define AMDPM_TS 0x00000001
355 #define AMDPM_FID 0x00000002
356 #define AMDPM_VID 0x00000004
357 #define AMDPM_TTP 0x00000008
358 #define AMDPM_TM 0x00000010
359 #define AMDPM_STC 0x00000020
360 #define AMDPM_100MHZ_STEPS 0x00000040
361 #define AMDPM_HW_PSTATE 0x00000080
362 #define AMDPM_TSC_INVARIANT 0x00000100
363 #define AMDPM_CPB 0x00000200
366 * AMD extended function 8000_0008h ebx info (amd_extended_feature_extensions)
368 #define AMDFEID_CLZERO 0x00000001
369 #define AMDFEID_IRPERF 0x00000002
370 #define AMDFEID_XSAVEERPTR 0x00000004
373 * AMD extended function 8000_0008h ecx info
375 #define AMDID_CMP_CORES 0x000000ff
376 #define AMDID_COREID_SIZE 0x0000f000
377 #define AMDID_COREID_SIZE_SHIFT 12
380 * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info
382 #define CPUID_STDEXT_FSGSBASE 0x00000001
383 #define CPUID_STDEXT_TSC_ADJUST 0x00000002
384 #define CPUID_STDEXT_SGX 0x00000004
385 #define CPUID_STDEXT_BMI1 0x00000008
386 #define CPUID_STDEXT_HLE 0x00000010
387 #define CPUID_STDEXT_AVX2 0x00000020
388 #define CPUID_STDEXT_FDP_EXC 0x00000040
389 #define CPUID_STDEXT_SMEP 0x00000080
390 #define CPUID_STDEXT_BMI2 0x00000100
391 #define CPUID_STDEXT_ERMS 0x00000200
392 #define CPUID_STDEXT_INVPCID 0x00000400
393 #define CPUID_STDEXT_RTM 0x00000800
394 #define CPUID_STDEXT_PQM 0x00001000
395 #define CPUID_STDEXT_NFPUSG 0x00002000
396 #define CPUID_STDEXT_MPX 0x00004000
397 #define CPUID_STDEXT_PQE 0x00008000
398 #define CPUID_STDEXT_AVX512F 0x00010000
399 #define CPUID_STDEXT_AVX512DQ 0x00020000
400 #define CPUID_STDEXT_RDSEED 0x00040000
401 #define CPUID_STDEXT_ADX 0x00080000
402 #define CPUID_STDEXT_SMAP 0x00100000
403 #define CPUID_STDEXT_AVX512IFMA 0x00200000
404 #define CPUID_STDEXT_PCOMMIT 0x00400000
405 #define CPUID_STDEXT_CLFLUSHOPT 0x00800000
406 #define CPUID_STDEXT_CLWB 0x01000000
407 #define CPUID_STDEXT_PROCTRACE 0x02000000
408 #define CPUID_STDEXT_AVX512PF 0x04000000
409 #define CPUID_STDEXT_AVX512ER 0x08000000
410 #define CPUID_STDEXT_AVX512CD 0x10000000
411 #define CPUID_STDEXT_SHA 0x20000000
412 #define CPUID_STDEXT_AVX512BW 0x40000000
413 #define CPUID_STDEXT_AVX512VL 0x80000000
416 * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info
418 #define CPUID_STDEXT2_PREFETCHWT1 0x00000001
419 #define CPUID_STDEXT2_UMIP 0x00000004
420 #define CPUID_STDEXT2_PKU 0x00000008
421 #define CPUID_STDEXT2_OSPKE 0x00000010
422 #define CPUID_STDEXT2_RDPID 0x00400000
423 #define CPUID_STDEXT2_SGXLC 0x40000000
426 * CPUID instruction 7 Structured Extended Features, leaf 0 edx info
428 #define CPUID_STDEXT3_IBPB 0x04000000
429 #define CPUID_STDEXT3_STIBP 0x08000000
430 #define CPUID_STDEXT3_L1D_FLUSH 0x10000000
431 #define CPUID_STDEXT3_ARCH_CAP 0x20000000
432 #define CPUID_STDEXT3_SSBD 0x80000000
434 /* MSR IA32_ARCH_CAP(ABILITIES) bits */
435 #define IA32_ARCH_CAP_RDCL_NO 0x00000001
436 #define IA32_ARCH_CAP_IBRS_ALL 0x00000002
437 #define IA32_ARCH_CAP_SSBD_NO 0x00000004
440 * CPUID manufacturers identifiers
442 #define AMD_VENDOR_ID "AuthenticAMD"
443 #define CENTAUR_VENDOR_ID "CentaurHauls"
444 #define CYRIX_VENDOR_ID "CyrixInstead"
445 #define INTEL_VENDOR_ID "GenuineIntel"
446 #define NEXGEN_VENDOR_ID "NexGenDriven"
447 #define NSC_VENDOR_ID "Geode by NSC"
448 #define RISE_VENDOR_ID "RiseRiseRise"
449 #define SIS_VENDOR_ID "SiS SiS SiS "
450 #define TRANSMETA_VENDOR_ID "GenuineTMx86"
451 #define UMC_VENDOR_ID "UMC UMC UMC "
454 * Model-specific registers for the i386 family
456 #define MSR_P5_MC_ADDR 0x000
457 #define MSR_P5_MC_TYPE 0x001
458 #define MSR_TSC 0x010
459 #define MSR_P5_CESR 0x011
460 #define MSR_P5_CTR0 0x012
461 #define MSR_P5_CTR1 0x013
462 #define MSR_IA32_PLATFORM_ID 0x017
463 #define MSR_APICBASE 0x01b
464 #define MSR_EBL_CR_POWERON 0x02a
465 #define MSR_TEST_CTL 0x033
466 #define MSR_IA32_FEATURE_CONTROL 0x03a
467 #define MSR_IA32_SPEC_CTRL 0x048
468 #define MSR_IA32_PRED_CMD 0x049
469 #define MSR_BIOS_UPDT_TRIG 0x079
470 #define MSR_BBL_CR_D0 0x088
471 #define MSR_BBL_CR_D1 0x089
472 #define MSR_BBL_CR_D2 0x08a
473 #define MSR_BIOS_SIGN 0x08b
474 #define MSR_PERFCTR0 0x0c1
475 #define MSR_PERFCTR1 0x0c2
476 #define MSR_PLATFORM_INFO 0x0ce
477 #define MSR_MPERF 0x0e7
478 #define MSR_APERF 0x0e8
479 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
480 #define MSR_MTRRcap 0x0fe
481 #define MSR_IA32_ARCH_CAP 0x10a
482 #define MSR_IA32_FLUSH_CMD 0x10b
483 #define MSR_BBL_CR_ADDR 0x116
484 #define MSR_BBL_CR_DECC 0x118
485 #define MSR_BBL_CR_CTL 0x119
486 #define MSR_BBL_CR_TRIG 0x11a
487 #define MSR_BBL_CR_BUSY 0x11b
488 #define MSR_BBL_CR_CTL3 0x11e
489 #define MSR_SYSENTER_CS_MSR 0x174
490 #define MSR_SYSENTER_ESP_MSR 0x175
491 #define MSR_SYSENTER_EIP_MSR 0x176
492 #define MSR_MCG_CAP 0x179
493 #define MSR_MCG_STATUS 0x17a
494 #define MSR_MCG_CTL 0x17b
495 #define MSR_EVNTSEL0 0x186
496 #define MSR_EVNTSEL1 0x187
497 #define MSR_THERM_CONTROL 0x19a
498 #define MSR_THERM_INTERRUPT 0x19b
499 #define MSR_THERM_STATUS 0x19c
500 #define MSR_IA32_MISC_ENABLE 0x1a0
501 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2
502 #define MSR_TURBO_RATIO_LIMIT 0x1ad
503 #define MSR_TURBO_RATIO_LIMIT1 0x1ae
504 #define MSR_DEBUGCTLMSR 0x1d9
505 #define MSR_LASTBRANCHFROMIP 0x1db
506 #define MSR_LASTBRANCHTOIP 0x1dc
507 #define MSR_LASTINTFROMIP 0x1dd
508 #define MSR_LASTINTTOIP 0x1de
509 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
510 #define MSR_MTRRVarBase 0x200
511 #define MSR_MTRR64kBase 0x250
512 #define MSR_MTRR16kBase 0x258
513 #define MSR_MTRR4kBase 0x268
514 #define MSR_PAT 0x277
515 #define MSR_MC0_CTL2 0x280
516 #define MSR_MTRRdefType 0x2ff
517 #define MSR_MC0_CTL 0x400
518 #define MSR_MC0_STATUS 0x401
519 #define MSR_MC0_ADDR 0x402
520 #define MSR_MC0_MISC 0x403
521 #define MSR_MC1_CTL 0x404
522 #define MSR_MC1_STATUS 0x405
523 #define MSR_MC1_ADDR 0x406
524 #define MSR_MC1_MISC 0x407
525 #define MSR_MC2_CTL 0x408
526 #define MSR_MC2_STATUS 0x409
527 #define MSR_MC2_ADDR 0x40a
528 #define MSR_MC2_MISC 0x40b
529 #define MSR_MC3_CTL 0x40c
530 #define MSR_MC3_STATUS 0x40d
531 #define MSR_MC3_ADDR 0x40e
532 #define MSR_MC3_MISC 0x40f
533 #define MSR_MC4_CTL 0x410
534 #define MSR_MC4_STATUS 0x411
535 #define MSR_MC4_ADDR 0x412
536 #define MSR_MC4_MISC 0x413
537 #define MSR_RAPL_POWER_UNIT 0x606
538 #define MSR_PKG_ENERGY_STATUS 0x611
539 #define MSR_DRAM_ENERGY_STATUS 0x619
540 #define MSR_PP0_ENERGY_STATUS 0x639
541 #define MSR_PP1_ENERGY_STATUS 0x641
542 #define MSR_TSC_DEADLINE 0x6e0 /* Writes are not serializing */
547 #define MSR_VMX_BASIC 0x480
548 #define MSR_VMX_PINBASED_CTLS 0x481
549 #define MSR_VMX_PROCBASED_CTLS 0x482
550 #define MSR_VMX_EXIT_CTLS 0x483
551 #define MSR_VMX_ENTRY_CTLS 0x484
552 #define MSR_VMX_CR0_FIXED0 0x486
553 #define MSR_VMX_CR0_FIXED1 0x487
554 #define MSR_VMX_CR4_FIXED0 0x488
555 #define MSR_VMX_CR4_FIXED1 0x489
556 #define MSR_VMX_PROCBASED_CTLS2 0x48b
557 #define MSR_VMX_EPT_VPID_CAP 0x48c
558 #define MSR_VMX_TRUE_PINBASED_CTLS 0x48d
559 #define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e
560 #define MSR_VMX_TRUE_EXIT_CTLS 0x48f
561 #define MSR_VMX_TRUE_ENTRY_CTLS 0x490
565 * Writes are not serializing.
567 #define MSR_APIC_000 0x800
568 #define MSR_APIC_ID 0x802
569 #define MSR_APIC_VERSION 0x803
570 #define MSR_APIC_TPR 0x808
571 #define MSR_APIC_EOI 0x80b
572 #define MSR_APIC_LDR 0x80d
573 #define MSR_APIC_SVR 0x80f
574 #define MSR_APIC_ISR0 0x810
575 #define MSR_APIC_ISR1 0x811
576 #define MSR_APIC_ISR2 0x812
577 #define MSR_APIC_ISR3 0x813
578 #define MSR_APIC_ISR4 0x814
579 #define MSR_APIC_ISR5 0x815
580 #define MSR_APIC_ISR6 0x816
581 #define MSR_APIC_ISR7 0x817
582 #define MSR_APIC_TMR0 0x818
583 #define MSR_APIC_IRR0 0x820
584 #define MSR_APIC_ESR 0x828
585 #define MSR_APIC_LVT_CMCI 0x82F
586 #define MSR_APIC_ICR 0x830
587 #define MSR_APIC_LVT_TIMER 0x832
588 #define MSR_APIC_LVT_THERMAL 0x833
589 #define MSR_APIC_LVT_PCINT 0x834
590 #define MSR_APIC_LVT_LINT0 0x835
591 #define MSR_APIC_LVT_LINT1 0x836
592 #define MSR_APIC_LVT_ERROR 0x837
593 #define MSR_APIC_ICR_TIMER 0x838
594 #define MSR_APIC_CCR_TIMER 0x839
595 #define MSR_APIC_DCR_TIMER 0x83e
596 #define MSR_APIC_SELF_IPI 0x83f
598 #define MSR_IA32_XSS 0xda0
601 * Intel Processor Trace (PT) MSRs.
603 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 /* Trace Output Base Register (R/W) */
604 #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x561 /* Trace Output Mask Pointers Register (R/W) */
605 #define MSR_IA32_RTIT_CTL 0x570 /* Trace Control Register (R/W) */
606 #define RTIT_CTL_TRACEEN (1 << 0)
607 #define RTIT_CTL_CYCEN (1 << 1)
608 #define RTIT_CTL_OS (1 << 2)
609 #define RTIT_CTL_USER (1 << 3)
610 #define RTIT_CTL_PWREVTEN (1 << 4)
611 #define RTIT_CTL_FUPONPTW (1 << 5)
612 #define RTIT_CTL_FABRICEN (1 << 6)
613 #define RTIT_CTL_CR3FILTER (1 << 7)
614 #define RTIT_CTL_TOPA (1 << 8)
615 #define RTIT_CTL_MTCEN (1 << 9)
616 #define RTIT_CTL_TSCEN (1 << 10)
617 #define RTIT_CTL_DISRETC (1 << 11)
618 #define RTIT_CTL_PTWEN (1 << 12)
619 #define RTIT_CTL_BRANCHEN (1 << 13)
620 #define RTIT_CTL_MTC_FREQ_S 14
621 #define RTIT_CTL_MTC_FREQ(n) ((n) << RTIT_CTL_MTC_FREQ_S)
622 #define RTIT_CTL_MTC_FREQ_M (0xf << RTIT_CTL_MTC_FREQ_S)
623 #define RTIT_CTL_CYC_THRESH_S 19
624 #define RTIT_CTL_CYC_THRESH_M (0xf << RTIT_CTL_CYC_THRESH_S)
625 #define RTIT_CTL_PSB_FREQ_S 24
626 #define RTIT_CTL_PSB_FREQ_M (0xf << RTIT_CTL_PSB_FREQ_S)
627 #define RTIT_CTL_ADDR_CFG_S(n) (32 + (n) * 4)
628 #define RTIT_CTL_ADDR0_CFG_S 32
629 #define RTIT_CTL_ADDR0_CFG_M (0xfULL << RTIT_CTL_ADDR0_CFG_S)
630 #define RTIT_CTL_ADDR1_CFG_S 36
631 #define RTIT_CTL_ADDR1_CFG_M (0xfULL << RTIT_CTL_ADDR1_CFG_S)
632 #define RTIT_CTL_ADDR2_CFG_S 40
633 #define RTIT_CTL_ADDR2_CFG_M (0xfULL << RTIT_CTL_ADDR2_CFG_S)
634 #define RTIT_CTL_ADDR3_CFG_S 44
635 #define RTIT_CTL_ADDR3_CFG_M (0xfULL << RTIT_CTL_ADDR3_CFG_S)
636 #define MSR_IA32_RTIT_STATUS 0x571 /* Tracing Status Register (R/W) */
637 #define RTIT_STATUS_FILTEREN (1 << 0)
638 #define RTIT_STATUS_CONTEXTEN (1 << 1)
639 #define RTIT_STATUS_TRIGGEREN (1 << 2)
640 #define RTIT_STATUS_ERROR (1 << 4)
641 #define RTIT_STATUS_STOPPED (1 << 5)
642 #define RTIT_STATUS_PACKETBYTECNT_S 32
643 #define RTIT_STATUS_PACKETBYTECNT_M (0x1ffffULL << RTIT_STATUS_PACKETBYTECNT_S)
644 #define MSR_IA32_RTIT_CR3_MATCH 0x572 /* Trace Filter CR3 Match Register (R/W) */
645 #define MSR_IA32_RTIT_ADDR_A(n) (0x580 + (n) * 2)
646 #define MSR_IA32_RTIT_ADDR_B(n) (0x581 + (n) * 2)
647 #define MSR_IA32_RTIT_ADDR0_A 0x580 /* Region 0 Start Address (R/W) */
648 #define MSR_IA32_RTIT_ADDR0_B 0x581 /* Region 0 End Address (R/W) */
649 #define MSR_IA32_RTIT_ADDR1_A 0x582 /* Region 1 Start Address (R/W) */
650 #define MSR_IA32_RTIT_ADDR1_B 0x583 /* Region 1 End Address (R/W) */
651 #define MSR_IA32_RTIT_ADDR2_A 0x584 /* Region 2 Start Address (R/W) */
652 #define MSR_IA32_RTIT_ADDR2_B 0x585 /* Region 2 End Address (R/W) */
653 #define MSR_IA32_RTIT_ADDR3_A 0x586 /* Region 3 Start Address (R/W) */
654 #define MSR_IA32_RTIT_ADDR3_B 0x587 /* Region 3 End Address (R/W) */
656 /* Intel Processor Trace Table of Physical Addresses (ToPA). */
657 #define TOPA_SIZE_S 6
658 #define TOPA_SIZE_M (0xf << TOPA_SIZE_S)
659 #define TOPA_SIZE_4K (0 << TOPA_SIZE_S)
660 #define TOPA_SIZE_8K (1 << TOPA_SIZE_S)
661 #define TOPA_SIZE_16K (2 << TOPA_SIZE_S)
662 #define TOPA_SIZE_32K (3 << TOPA_SIZE_S)
663 #define TOPA_SIZE_64K (4 << TOPA_SIZE_S)
664 #define TOPA_SIZE_128K (5 << TOPA_SIZE_S)
665 #define TOPA_SIZE_256K (6 << TOPA_SIZE_S)
666 #define TOPA_SIZE_512K (7 << TOPA_SIZE_S)
667 #define TOPA_SIZE_1M (8 << TOPA_SIZE_S)
668 #define TOPA_SIZE_2M (9 << TOPA_SIZE_S)
669 #define TOPA_SIZE_4M (10 << TOPA_SIZE_S)
670 #define TOPA_SIZE_8M (11 << TOPA_SIZE_S)
671 #define TOPA_SIZE_16M (12 << TOPA_SIZE_S)
672 #define TOPA_SIZE_32M (13 << TOPA_SIZE_S)
673 #define TOPA_SIZE_64M (14 << TOPA_SIZE_S)
674 #define TOPA_SIZE_128M (15 << TOPA_SIZE_S)
675 #define TOPA_STOP (1 << 4)
676 #define TOPA_INT (1 << 2)
677 #define TOPA_END (1 << 0)
680 * Constants related to MSR's.
682 #define APICBASE_RESERVED 0x000002ff
683 #define APICBASE_BSP 0x00000100
684 #define APICBASE_X2APIC 0x00000400
685 #define APICBASE_ENABLED 0x00000800
686 #define APICBASE_ADDRESS 0xfffff000
688 /* MSR_IA32_FEATURE_CONTROL related */
689 #define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */
690 #define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */
691 #define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */
693 /* MSR IA32_MISC_ENABLE */
694 #define IA32_MISC_EN_FASTSTR 0x0000000000000001ULL
695 #define IA32_MISC_EN_ATCCE 0x0000000000000008ULL
696 #define IA32_MISC_EN_PERFMON 0x0000000000000080ULL
697 #define IA32_MISC_EN_PEBSU 0x0000000000001000ULL
698 #define IA32_MISC_EN_ESSTE 0x0000000000010000ULL
699 #define IA32_MISC_EN_MONE 0x0000000000040000ULL
700 #define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL
701 #define IA32_MISC_EN_xTPRD 0x0000000000800000ULL
702 #define IA32_MISC_EN_XDD 0x0000000400000000ULL
705 * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel'
706 * document 336996-001 Speculative Execution Side Channel Mitigations.
708 /* MSR IA32_SPEC_CTRL */
709 #define IA32_SPEC_CTRL_IBRS 0x00000001
710 #define IA32_SPEC_CTRL_STIBP 0x00000002
711 #define IA32_SPEC_CTRL_SSBD 0x00000004
713 /* MSR IA32_PRED_CMD */
714 #define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL
716 /* MSR IA32_FLUSH_CMD */
717 #define IA32_FLUSH_CMD_L1D 0x00000001
722 #define PAT_UNCACHEABLE 0x00
723 #define PAT_WRITE_COMBINING 0x01
724 #define PAT_WRITE_THROUGH 0x04
725 #define PAT_WRITE_PROTECTED 0x05
726 #define PAT_WRITE_BACK 0x06
727 #define PAT_UNCACHED 0x07
728 #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i)))
729 #define PAT_MASK(i) PAT_VALUE(i, 0xff)
732 * Constants related to MTRRs
734 #define MTRR_UNCACHEABLE 0x00
735 #define MTRR_WRITE_COMBINING 0x01
736 #define MTRR_WRITE_THROUGH 0x04
737 #define MTRR_WRITE_PROTECTED 0x05
738 #define MTRR_WRITE_BACK 0x06
739 #define MTRR_N64K 8 /* numbers of fixed-size entries */
742 #define MTRR_CAP_WC 0x0000000000000400
743 #define MTRR_CAP_FIXED 0x0000000000000100
744 #define MTRR_CAP_VCNT 0x00000000000000ff
745 #define MTRR_DEF_ENABLE 0x0000000000000800
746 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400
747 #define MTRR_DEF_TYPE 0x00000000000000ff
748 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000
749 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff
750 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000
751 #define MTRR_PHYSMASK_VALID 0x0000000000000800
754 * Cyrix configuration registers, accessible as IO ports.
756 #define CCR0 0xc0 /* Configuration control register 0 */
757 #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
759 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
760 #define CCR0_A20M 0x04 /* Enables A20M# input pin */
761 #define CCR0_KEN 0x08 /* Enables KEN# input pin */
762 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
763 #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
765 #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
767 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
769 #define CCR1 0xc1 /* Configuration control register 1 */
770 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
771 #define CCR1_SMI 0x02 /* Enables SMM pins */
772 #define CCR1_SMAC 0x04 /* System management memory access */
773 #define CCR1_MMAC 0x08 /* Main memory access */
774 #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
775 #define CCR1_SM3 0x80 /* SMM address space address region 3 */
778 #define CCR2_WB 0x02 /* Enables WB cache interface pins */
779 #define CCR2_SADS 0x02 /* Slow ADS */
780 #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
781 #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
782 #define CCR2_WT1 0x10 /* WT region 1 */
783 #define CCR2_WPR1 0x10 /* Write-protect region 1 */
784 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering
786 #define CCR2_BWRT 0x40 /* Enables burst write cycles */
787 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
790 #define CCR3_SMILOCK 0x01 /* SMM register lock */
791 #define CCR3_NMI 0x02 /* Enables NMI during SMM */
792 #define CCR3_LINBRST 0x04 /* Linear address burst cycles */
793 #define CCR3_SMMMODE 0x08 /* SMM Mode */
794 #define CCR3_MAPEN0 0x10 /* Enables Map0 */
795 #define CCR3_MAPEN1 0x20 /* Enables Map1 */
796 #define CCR3_MAPEN2 0x40 /* Enables Map2 */
797 #define CCR3_MAPEN3 0x80 /* Enables Map3 */
800 #define CCR4_IOMASK 0x07
801 #define CCR4_MEM 0x08 /* Enables momory bypassing */
802 #define CCR4_DTE 0x10 /* Enables directory table entry cache */
803 #define CCR4_FASTFPE 0x20 /* Fast FPU exception */
804 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */
807 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
808 #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
809 #define CCR5_LBR1 0x10 /* Local bus region 1 */
810 #define CCR5_ARREN 0x20 /* Enables ARR region */
816 /* Performance Control Register (5x86 only). */
818 #define PCR0_RSTK 0x01 /* Enables return stack */
819 #define PCR0_BTB 0x02 /* Enables branch target buffer */
820 #define PCR0_LOOP 0x04 /* Enables loop */
821 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
823 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
824 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
825 #define PCR0_LSSER 0x80 /* Disable reorder */
827 /* Device Identification Registers */
832 * Machine Check register constants.
834 #define MCG_CAP_COUNT 0x000000ff
835 #define MCG_CAP_CTL_P 0x00000100
836 #define MCG_CAP_EXT_P 0x00000200
837 #define MCG_CAP_CMCI_P 0x00000400
838 #define MCG_CAP_TES_P 0x00000800
839 #define MCG_CAP_EXT_CNT 0x00ff0000
840 #define MCG_CAP_SER_P 0x01000000
841 #define MCG_STATUS_RIPV 0x00000001
842 #define MCG_STATUS_EIPV 0x00000002
843 #define MCG_STATUS_MCIP 0x00000004
844 #define MCG_CTL_ENABLE 0xffffffffffffffff
845 #define MCG_CTL_DISABLE 0x0000000000000000
846 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
847 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
848 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
849 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
850 #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */
851 #define MC_STATUS_MCA_ERROR 0x000000000000ffff
852 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000
853 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000
854 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */
855 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */
856 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */
857 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */
858 #define MC_STATUS_PCC 0x0200000000000000
859 #define MC_STATUS_ADDRV 0x0400000000000000
860 #define MC_STATUS_MISCV 0x0800000000000000
861 #define MC_STATUS_EN 0x1000000000000000
862 #define MC_STATUS_UC 0x2000000000000000
863 #define MC_STATUS_OVER 0x4000000000000000
864 #define MC_STATUS_VAL 0x8000000000000000
865 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */
866 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */
867 #define MC_CTL2_THRESHOLD 0x0000000000007fff
868 #define MC_CTL2_CMCI_EN 0x0000000040000000
869 #define MC_AMDNB_BANK 4
870 #define MC_MISC_AMD_VAL 0x8000000000000000 /* Counter presence valid */
871 #define MC_MISC_AMD_CNTP 0x4000000000000000 /* Counter present */
872 #define MC_MISC_AMD_LOCK 0x2000000000000000 /* Register locked */
873 #define MC_MISC_AMD_INTP 0x1000000000000000 /* Int. type can generate interrupts */
874 #define MC_MISC_AMD_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */
875 #define MC_MISC_AMD_LVT_SHIFT 52
876 #define MC_MISC_AMD_CNTEN 0x0008000000000000 /* Counter enabled */
877 #define MC_MISC_AMD_INT_MASK 0x0006000000000000 /* Interrupt type */
878 #define MC_MISC_AMD_INT_LVT 0x0002000000000000 /* Interrupt via Extended LVT */
879 #define MC_MISC_AMD_INT_SMI 0x0004000000000000 /* SMI */
880 #define MC_MISC_AMD_OVERFLOW 0x0001000000000000 /* Counter overflow */
881 #define MC_MISC_AMD_CNT_MASK 0x00000fff00000000 /* Counter value */
882 #define MC_MISC_AMD_CNT_SHIFT 32
883 #define MC_MISC_AMD_CNT_MAX 0xfff
884 #define MC_MISC_AMD_PTR_MASK 0x00000000ff000000 /* Pointer to additional registers */
885 #define MC_MISC_AMD_PTR_SHIFT 24
888 * The following four 3-byte registers control the non-cacheable regions.
889 * These registers must be written as three separate bytes.
891 * NCRx+0: A31-A24 of starting address
892 * NCRx+1: A23-A16 of starting address
893 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
895 * The non-cacheable region's starting address must be aligned to the
896 * size indicated by the NCR_SIZE_xx field.
903 #define NCR_SIZE_0K 0
904 #define NCR_SIZE_4K 1
905 #define NCR_SIZE_8K 2
906 #define NCR_SIZE_16K 3
907 #define NCR_SIZE_32K 4
908 #define NCR_SIZE_64K 5
909 #define NCR_SIZE_128K 6
910 #define NCR_SIZE_256K 7
911 #define NCR_SIZE_512K 8
912 #define NCR_SIZE_1M 9
913 #define NCR_SIZE_2M 10
914 #define NCR_SIZE_4M 11
915 #define NCR_SIZE_8M 12
916 #define NCR_SIZE_16M 13
917 #define NCR_SIZE_32M 14
918 #define NCR_SIZE_4G 15
921 * The address region registers are used to specify the location and
922 * size for the eight address regions.
924 * ARRx + 0: A31-A24 of start address
925 * ARRx + 1: A23-A16 of start address
926 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
937 #define ARR_SIZE_0K 0
938 #define ARR_SIZE_4K 1
939 #define ARR_SIZE_8K 2
940 #define ARR_SIZE_16K 3
941 #define ARR_SIZE_32K 4
942 #define ARR_SIZE_64K 5
943 #define ARR_SIZE_128K 6
944 #define ARR_SIZE_256K 7
945 #define ARR_SIZE_512K 8
946 #define ARR_SIZE_1M 9
947 #define ARR_SIZE_2M 10
948 #define ARR_SIZE_4M 11
949 #define ARR_SIZE_8M 12
950 #define ARR_SIZE_16M 13
951 #define ARR_SIZE_32M 14
952 #define ARR_SIZE_4G 15
955 * The region control registers specify the attributes associated with
956 * the ARRx addres regions.
967 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
968 #define RCR_RCE 0x01 /* Enables caching for ARR7. */
969 #define RCR_WWO 0x02 /* Weak write ordering. */
970 #define RCR_WL 0x04 /* Weak locking. */
971 #define RCR_WG 0x08 /* Write gathering. */
972 #define RCR_WT 0x10 /* Write-through. */
973 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
975 /* AMD Write Allocate Top-Of-Memory and Control Register */
976 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
977 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
978 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
981 #define MSR_EFER 0xc0000080 /* extended features */
982 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
983 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
984 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
985 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
986 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
987 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
988 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
989 #define MSR_PERFEVSEL0 0xc0010000
990 #define MSR_PERFEVSEL1 0xc0010001
991 #define MSR_PERFEVSEL2 0xc0010002
992 #define MSR_PERFEVSEL3 0xc0010003
993 #define MSR_K7_PERFCTR0 0xc0010004
994 #define MSR_K7_PERFCTR1 0xc0010005
995 #define MSR_K7_PERFCTR2 0xc0010006
996 #define MSR_K7_PERFCTR3 0xc0010007
997 #define MSR_SYSCFG 0xc0010010
998 #define MSR_HWCR 0xc0010015
999 #define MSR_IORRBASE0 0xc0010016
1000 #define MSR_IORRMASK0 0xc0010017
1001 #define MSR_IORRBASE1 0xc0010018
1002 #define MSR_IORRMASK1 0xc0010019
1003 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
1004 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
1005 #define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */
1006 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
1007 #define MSR_MC0_CTL_MASK 0xc0010044
1008 #define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */
1009 #define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */
1010 #define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */
1011 #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */
1012 #define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */
1013 #define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */
1014 #define MSR_VM_CR 0xc0010114 /* SVM: feature control */
1015 #define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */
1016 #define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */
1017 #define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */
1018 #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */
1020 /* MSR_VM_CR related */
1021 #define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */
1023 /* VIA ACE crypto featureset: for via_feature_rng */
1024 #define VIA_HAS_RNG 1 /* cpu has RNG */
1026 /* VIA ACE crypto featureset: for via_feature_xcrypt */
1027 #define VIA_HAS_AES 1 /* cpu has AES */
1028 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
1029 #define VIA_HAS_MM 4 /* cpu has RSA instructions */
1030 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
1032 /* Centaur Extended Feature flags */
1033 #define VIA_CPUID_HAS_RNG 0x000004
1034 #define VIA_CPUID_DO_RNG 0x000008
1035 #define VIA_CPUID_HAS_ACE 0x000040
1036 #define VIA_CPUID_DO_ACE 0x000080
1037 #define VIA_CPUID_HAS_ACE2 0x000100
1038 #define VIA_CPUID_DO_ACE2 0x000200
1039 #define VIA_CPUID_HAS_PHE 0x000400
1040 #define VIA_CPUID_DO_PHE 0x000800
1041 #define VIA_CPUID_HAS_PMM 0x001000
1042 #define VIA_CPUID_DO_PMM 0x002000
1044 /* VIA ACE xcrypt-* instruction context control options */
1045 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f
1046 #define VIA_CRYPT_CWLO_ALG_M 0x00000070
1047 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000
1048 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080
1049 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000
1050 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080
1051 #define VIA_CRYPT_CWLO_NORMAL 0x00000000
1052 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100
1053 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000
1054 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200
1055 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
1056 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
1057 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
1059 #endif /* !_MACHINE_SPECIALREG_H_ */