2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 4. Neither the name of the University nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
33 #ifndef _MACHINE_SPECIALREG_H_
34 #define _MACHINE_SPECIALREG_H_
37 * Bits in 386 special registers:
39 #define CR0_PE 0x00000001 /* Protected mode Enable */
40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
43 #define CR0_PG 0x80000000 /* PaGing enable */
46 * Bits in 486 special registers:
48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
52 #define CR0_NW 0x20000000 /* Not Write-through */
53 #define CR0_CD 0x40000000 /* Cache Disable */
55 #define CR3_PCID_SAVE 0x8000000000000000
56 #define CR3_PCID_MASK 0xfff
59 * Bits in PPro special registers
61 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
62 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
63 #define CR4_TSD 0x00000004 /* Time stamp disable */
64 #define CR4_DE 0x00000008 /* Debugging extensions */
65 #define CR4_PSE 0x00000010 /* Page size extensions */
66 #define CR4_PAE 0x00000020 /* Physical address extension */
67 #define CR4_MCE 0x00000040 /* Machine check enable */
68 #define CR4_PGE 0x00000080 /* Page global enable */
69 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
70 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
71 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
72 #define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */
73 #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */
74 #define CR4_PCIDE 0x00020000 /* Enable Context ID */
75 #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */
76 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */
79 * Bits in AMD64 special registers. EFER is 64 bits wide.
81 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
82 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */
83 #define EFER_LMA 0x000000400 /* Long mode active (R) */
84 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
85 #define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */
86 #define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */
87 #define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */
88 #define EFER_TCE 0x000008000 /* Translation Cache Extension */
91 * Intel Extended Features registers
93 #define XCR0 0 /* XFEATURE_ENABLED_MASK register */
95 #define XFEATURE_ENABLED_X87 0x00000001
96 #define XFEATURE_ENABLED_SSE 0x00000002
97 #define XFEATURE_ENABLED_YMM_HI128 0x00000004
98 #define XFEATURE_ENABLED_AVX XFEATURE_ENABLED_YMM_HI128
99 #define XFEATURE_ENABLED_BNDREGS 0x00000008
100 #define XFEATURE_ENABLED_BNDCSR 0x00000010
101 #define XFEATURE_ENABLED_OPMASK 0x00000020
102 #define XFEATURE_ENABLED_ZMM_HI256 0x00000040
103 #define XFEATURE_ENABLED_HI16_ZMM 0x00000080
105 #define XFEATURE_AVX \
106 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX)
107 #define XFEATURE_AVX512 \
108 (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 | \
109 XFEATURE_ENABLED_HI16_ZMM)
110 #define XFEATURE_MPX \
111 (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR)
114 * CPUID instruction features register
116 #define CPUID_FPU 0x00000001
117 #define CPUID_VME 0x00000002
118 #define CPUID_DE 0x00000004
119 #define CPUID_PSE 0x00000008
120 #define CPUID_TSC 0x00000010
121 #define CPUID_MSR 0x00000020
122 #define CPUID_PAE 0x00000040
123 #define CPUID_MCE 0x00000080
124 #define CPUID_CX8 0x00000100
125 #define CPUID_APIC 0x00000200
126 #define CPUID_B10 0x00000400
127 #define CPUID_SEP 0x00000800
128 #define CPUID_MTRR 0x00001000
129 #define CPUID_PGE 0x00002000
130 #define CPUID_MCA 0x00004000
131 #define CPUID_CMOV 0x00008000
132 #define CPUID_PAT 0x00010000
133 #define CPUID_PSE36 0x00020000
134 #define CPUID_PSN 0x00040000
135 #define CPUID_CLFSH 0x00080000
136 #define CPUID_B20 0x00100000
137 #define CPUID_DS 0x00200000
138 #define CPUID_ACPI 0x00400000
139 #define CPUID_MMX 0x00800000
140 #define CPUID_FXSR 0x01000000
141 #define CPUID_SSE 0x02000000
142 #define CPUID_XMM 0x02000000
143 #define CPUID_SSE2 0x04000000
144 #define CPUID_SS 0x08000000
145 #define CPUID_HTT 0x10000000
146 #define CPUID_TM 0x20000000
147 #define CPUID_IA64 0x40000000
148 #define CPUID_PBE 0x80000000
150 #define CPUID2_SSE3 0x00000001
151 #define CPUID2_PCLMULQDQ 0x00000002
152 #define CPUID2_DTES64 0x00000004
153 #define CPUID2_MON 0x00000008
154 #define CPUID2_DS_CPL 0x00000010
155 #define CPUID2_VMX 0x00000020
156 #define CPUID2_SMX 0x00000040
157 #define CPUID2_EST 0x00000080
158 #define CPUID2_TM2 0x00000100
159 #define CPUID2_SSSE3 0x00000200
160 #define CPUID2_CNXTID 0x00000400
161 #define CPUID2_SDBG 0x00000800
162 #define CPUID2_FMA 0x00001000
163 #define CPUID2_CX16 0x00002000
164 #define CPUID2_XTPR 0x00004000
165 #define CPUID2_PDCM 0x00008000
166 #define CPUID2_PCID 0x00020000
167 #define CPUID2_DCA 0x00040000
168 #define CPUID2_SSE41 0x00080000
169 #define CPUID2_SSE42 0x00100000
170 #define CPUID2_X2APIC 0x00200000
171 #define CPUID2_MOVBE 0x00400000
172 #define CPUID2_POPCNT 0x00800000
173 #define CPUID2_TSCDLT 0x01000000
174 #define CPUID2_AESNI 0x02000000
175 #define CPUID2_XSAVE 0x04000000
176 #define CPUID2_OSXSAVE 0x08000000
177 #define CPUID2_AVX 0x10000000
178 #define CPUID2_F16C 0x20000000
179 #define CPUID2_RDRAND 0x40000000
180 #define CPUID2_HV 0x80000000
183 * Important bits in the Thermal and Power Management flags
184 * CPUID.6 EAX and ECX.
186 #define CPUTPM1_SENSOR 0x00000001
187 #define CPUTPM1_TURBO 0x00000002
188 #define CPUTPM1_ARAT 0x00000004
189 #define CPUTPM2_EFFREQ 0x00000001
192 * Important bits in the AMD extended cpuid flags
194 #define AMDID_SYSCALL 0x00000800
195 #define AMDID_MP 0x00080000
196 #define AMDID_NX 0x00100000
197 #define AMDID_EXT_MMX 0x00400000
198 #define AMDID_FFXSR 0x02000000
199 #define AMDID_PAGE1GB 0x04000000
200 #define AMDID_RDTSCP 0x08000000
201 #define AMDID_LM 0x20000000
202 #define AMDID_EXT_3DNOW 0x40000000
203 #define AMDID_3DNOW 0x80000000
205 #define AMDID2_LAHF 0x00000001
206 #define AMDID2_CMP 0x00000002
207 #define AMDID2_SVM 0x00000004
208 #define AMDID2_EXT_APIC 0x00000008
209 #define AMDID2_CR8 0x00000010
210 #define AMDID2_ABM 0x00000020
211 #define AMDID2_SSE4A 0x00000040
212 #define AMDID2_MAS 0x00000080
213 #define AMDID2_PREFETCH 0x00000100
214 #define AMDID2_OSVW 0x00000200
215 #define AMDID2_IBS 0x00000400
216 #define AMDID2_XOP 0x00000800
217 #define AMDID2_SKINIT 0x00001000
218 #define AMDID2_WDT 0x00002000
219 #define AMDID2_LWP 0x00008000
220 #define AMDID2_FMA4 0x00010000
221 #define AMDID2_TCE 0x00020000
222 #define AMDID2_NODE_ID 0x00080000
223 #define AMDID2_TBM 0x00200000
224 #define AMDID2_TOPOLOGY 0x00400000
225 #define AMDID2_PCXC 0x00800000
226 #define AMDID2_PNXC 0x01000000
227 #define AMDID2_DBE 0x04000000
228 #define AMDID2_PTSC 0x08000000
229 #define AMDID2_PTSCEL2I 0x10000000
230 #define AMDID2_MWAITX 0x20000000
233 * CPUID instruction 1 eax info
235 #define CPUID_STEPPING 0x0000000f
236 #define CPUID_MODEL 0x000000f0
237 #define CPUID_FAMILY 0x00000f00
238 #define CPUID_EXT_MODEL 0x000f0000
239 #define CPUID_EXT_FAMILY 0x0ff00000
241 #define CPUID_TO_MODEL(id) \
242 ((((id) & CPUID_MODEL) >> 4) | \
243 ((((id) & CPUID_FAMILY) >= 0x600) ? \
244 (((id) & CPUID_EXT_MODEL) >> 12) : 0))
245 #define CPUID_TO_FAMILY(id) \
246 ((((id) & CPUID_FAMILY) >> 8) + \
247 ((((id) & CPUID_FAMILY) == 0xf00) ? \
248 (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
250 #define CPUID_TO_MODEL(id) \
251 ((((id) & CPUID_MODEL) >> 4) | \
252 (((id) & CPUID_EXT_MODEL) >> 12))
253 #define CPUID_TO_FAMILY(id) \
254 ((((id) & CPUID_FAMILY) >> 8) + \
255 (((id) & CPUID_EXT_FAMILY) >> 20))
259 * CPUID instruction 1 ebx info
261 #define CPUID_BRAND_INDEX 0x000000ff
262 #define CPUID_CLFUSH_SIZE 0x0000ff00
263 #define CPUID_HTT_CORES 0x00ff0000
264 #define CPUID_LOCAL_APIC_ID 0xff000000
267 * CPUID instruction 5 info
269 #define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */
270 #define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */
271 #define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */
272 #define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */
275 * MWAIT cpu power states. Lower 4 bits are sub-states.
277 #define MWAIT_C0 0xf0
278 #define MWAIT_C1 0x00
279 #define MWAIT_C2 0x10
280 #define MWAIT_C3 0x20
281 #define MWAIT_C4 0x30
286 /* Interrupt breaks MWAIT even when masked. */
287 #define MWAIT_INTRBREAK 0x00000001
290 * CPUID instruction 6 ecx info
292 #define CPUID_PERF_STAT 0x00000001
293 #define CPUID_PERF_BIAS 0x00000008
296 * CPUID instruction 0xb ebx info.
298 #define CPUID_TYPE_INVAL 0
299 #define CPUID_TYPE_SMT 1
300 #define CPUID_TYPE_CORE 2
303 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1
305 #define CPUID_EXTSTATE_XSAVEOPT 0x00000001
306 #define CPUID_EXTSTATE_XSAVEC 0x00000002
307 #define CPUID_EXTSTATE_XINUSE 0x00000004
308 #define CPUID_EXTSTATE_XSAVES 0x00000008
311 * AMD extended function 8000_0007h edx info
313 #define AMDPM_TS 0x00000001
314 #define AMDPM_FID 0x00000002
315 #define AMDPM_VID 0x00000004
316 #define AMDPM_TTP 0x00000008
317 #define AMDPM_TM 0x00000010
318 #define AMDPM_STC 0x00000020
319 #define AMDPM_100MHZ_STEPS 0x00000040
320 #define AMDPM_HW_PSTATE 0x00000080
321 #define AMDPM_TSC_INVARIANT 0x00000100
322 #define AMDPM_CPB 0x00000200
325 * AMD extended function 8000_0008h ecx info
327 #define AMDID_CMP_CORES 0x000000ff
328 #define AMDID_COREID_SIZE 0x0000f000
329 #define AMDID_COREID_SIZE_SHIFT 12
332 * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info
334 #define CPUID_STDEXT_FSGSBASE 0x00000001
335 #define CPUID_STDEXT_TSC_ADJUST 0x00000002
336 #define CPUID_STDEXT_SGX 0x00000004
337 #define CPUID_STDEXT_BMI1 0x00000008
338 #define CPUID_STDEXT_HLE 0x00000010
339 #define CPUID_STDEXT_AVX2 0x00000020
340 #define CPUID_STDEXT_FDP_EXC 0x00000040
341 #define CPUID_STDEXT_SMEP 0x00000080
342 #define CPUID_STDEXT_BMI2 0x00000100
343 #define CPUID_STDEXT_ERMS 0x00000200
344 #define CPUID_STDEXT_INVPCID 0x00000400
345 #define CPUID_STDEXT_RTM 0x00000800
346 #define CPUID_STDEXT_PQM 0x00001000
347 #define CPUID_STDEXT_NFPUSG 0x00002000
348 #define CPUID_STDEXT_MPX 0x00004000
349 #define CPUID_STDEXT_PQE 0x00008000
350 #define CPUID_STDEXT_AVX512F 0x00010000
351 #define CPUID_STDEXT_AVX512DQ 0x00020000
352 #define CPUID_STDEXT_RDSEED 0x00040000
353 #define CPUID_STDEXT_ADX 0x00080000
354 #define CPUID_STDEXT_SMAP 0x00100000
355 #define CPUID_STDEXT_AVX512IFMA 0x00200000
356 #define CPUID_STDEXT_PCOMMIT 0x00400000
357 #define CPUID_STDEXT_CLFLUSHOPT 0x00800000
358 #define CPUID_STDEXT_CLWB 0x01000000
359 #define CPUID_STDEXT_PROCTRACE 0x02000000
360 #define CPUID_STDEXT_AVX512PF 0x04000000
361 #define CPUID_STDEXT_AVX512ER 0x08000000
362 #define CPUID_STDEXT_AVX512CD 0x10000000
363 #define CPUID_STDEXT_SHA 0x20000000
364 #define CPUID_STDEXT_AVX512BW 0x40000000
367 * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info
369 #define CPUID_STDEXT2_PREFETCHWT1 0x00000001
370 #define CPUID_STDEXT2_UMIP 0x00000004
371 #define CPUID_STDEXT2_PKU 0x00000008
372 #define CPUID_STDEXT2_OSPKE 0x00000010
373 #define CPUID_STDEXT2_RDPID 0x00400000
374 #define CPUID_STDEXT2_SGXLC 0x40000000
377 * CPUID instruction 7 Structured Extended Features, leaf 0 edx info
379 #define CPUID_STDEXT3_IBPB 0x04000000
380 #define CPUID_STDEXT3_STIBP 0x08000000
381 #define CPUID_STDEXT3_L1D_FLUSH 0x10000000
382 #define CPUID_STDEXT3_ARCH_CAP 0x20000000
384 /* MSR IA32_ARCH_CAP(ABILITIES) bits */
385 #define IA32_ARCH_CAP_RDCL_NO 0x00000001
386 #define IA32_ARCH_CAP_IBRS_ALL 0x00000002
389 * CPUID manufacturers identifiers
391 #define AMD_VENDOR_ID "AuthenticAMD"
392 #define CENTAUR_VENDOR_ID "CentaurHauls"
393 #define CYRIX_VENDOR_ID "CyrixInstead"
394 #define INTEL_VENDOR_ID "GenuineIntel"
395 #define NEXGEN_VENDOR_ID "NexGenDriven"
396 #define NSC_VENDOR_ID "Geode by NSC"
397 #define RISE_VENDOR_ID "RiseRiseRise"
398 #define SIS_VENDOR_ID "SiS SiS SiS "
399 #define TRANSMETA_VENDOR_ID "GenuineTMx86"
400 #define UMC_VENDOR_ID "UMC UMC UMC "
403 * Model-specific registers for the i386 family
405 #define MSR_P5_MC_ADDR 0x000
406 #define MSR_P5_MC_TYPE 0x001
407 #define MSR_TSC 0x010
408 #define MSR_P5_CESR 0x011
409 #define MSR_P5_CTR0 0x012
410 #define MSR_P5_CTR1 0x013
411 #define MSR_IA32_PLATFORM_ID 0x017
412 #define MSR_APICBASE 0x01b
413 #define MSR_EBL_CR_POWERON 0x02a
414 #define MSR_TEST_CTL 0x033
415 #define MSR_IA32_FEATURE_CONTROL 0x03a
416 #define MSR_IA32_SPEC_CTRL 0x048
417 #define MSR_IA32_PRED_CMD 0x049
418 #define MSR_BIOS_UPDT_TRIG 0x079
419 #define MSR_BBL_CR_D0 0x088
420 #define MSR_BBL_CR_D1 0x089
421 #define MSR_BBL_CR_D2 0x08a
422 #define MSR_BIOS_SIGN 0x08b
423 #define MSR_PERFCTR0 0x0c1
424 #define MSR_PERFCTR1 0x0c2
425 #define MSR_PLATFORM_INFO 0x0ce
426 #define MSR_MPERF 0x0e7
427 #define MSR_APERF 0x0e8
428 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
429 #define MSR_MTRRcap 0x0fe
430 #define MSR_IA32_ARCH_CAP 0x10a
431 #define MSR_IA32_FLUSH_CMD 0x10b
432 #define MSR_BBL_CR_ADDR 0x116
433 #define MSR_BBL_CR_DECC 0x118
434 #define MSR_BBL_CR_CTL 0x119
435 #define MSR_BBL_CR_TRIG 0x11a
436 #define MSR_BBL_CR_BUSY 0x11b
437 #define MSR_BBL_CR_CTL3 0x11e
438 #define MSR_SYSENTER_CS_MSR 0x174
439 #define MSR_SYSENTER_ESP_MSR 0x175
440 #define MSR_SYSENTER_EIP_MSR 0x176
441 #define MSR_MCG_CAP 0x179
442 #define MSR_MCG_STATUS 0x17a
443 #define MSR_MCG_CTL 0x17b
444 #define MSR_EVNTSEL0 0x186
445 #define MSR_EVNTSEL1 0x187
446 #define MSR_THERM_CONTROL 0x19a
447 #define MSR_THERM_INTERRUPT 0x19b
448 #define MSR_THERM_STATUS 0x19c
449 #define MSR_IA32_MISC_ENABLE 0x1a0
450 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2
451 #define MSR_TURBO_RATIO_LIMIT 0x1ad
452 #define MSR_TURBO_RATIO_LIMIT1 0x1ae
453 #define MSR_DEBUGCTLMSR 0x1d9
454 #define MSR_LASTBRANCHFROMIP 0x1db
455 #define MSR_LASTBRANCHTOIP 0x1dc
456 #define MSR_LASTINTFROMIP 0x1dd
457 #define MSR_LASTINTTOIP 0x1de
458 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
459 #define MSR_MTRRVarBase 0x200
460 #define MSR_MTRR64kBase 0x250
461 #define MSR_MTRR16kBase 0x258
462 #define MSR_MTRR4kBase 0x268
463 #define MSR_PAT 0x277
464 #define MSR_MC0_CTL2 0x280
465 #define MSR_MTRRdefType 0x2ff
466 #define MSR_MC0_CTL 0x400
467 #define MSR_MC0_STATUS 0x401
468 #define MSR_MC0_ADDR 0x402
469 #define MSR_MC0_MISC 0x403
470 #define MSR_MC1_CTL 0x404
471 #define MSR_MC1_STATUS 0x405
472 #define MSR_MC1_ADDR 0x406
473 #define MSR_MC1_MISC 0x407
474 #define MSR_MC2_CTL 0x408
475 #define MSR_MC2_STATUS 0x409
476 #define MSR_MC2_ADDR 0x40a
477 #define MSR_MC2_MISC 0x40b
478 #define MSR_MC3_CTL 0x40c
479 #define MSR_MC3_STATUS 0x40d
480 #define MSR_MC3_ADDR 0x40e
481 #define MSR_MC3_MISC 0x40f
482 #define MSR_MC4_CTL 0x410
483 #define MSR_MC4_STATUS 0x411
484 #define MSR_MC4_ADDR 0x412
485 #define MSR_MC4_MISC 0x413
486 #define MSR_RAPL_POWER_UNIT 0x606
487 #define MSR_PKG_ENERGY_STATUS 0x611
488 #define MSR_DRAM_ENERGY_STATUS 0x619
489 #define MSR_PP0_ENERGY_STATUS 0x639
490 #define MSR_PP1_ENERGY_STATUS 0x641
491 #define MSR_TSC_DEADLINE 0x6e0 /* Writes are not serializing */
496 #define MSR_VMX_BASIC 0x480
497 #define MSR_VMX_PINBASED_CTLS 0x481
498 #define MSR_VMX_PROCBASED_CTLS 0x482
499 #define MSR_VMX_EXIT_CTLS 0x483
500 #define MSR_VMX_ENTRY_CTLS 0x484
501 #define MSR_VMX_CR0_FIXED0 0x486
502 #define MSR_VMX_CR0_FIXED1 0x487
503 #define MSR_VMX_CR4_FIXED0 0x488
504 #define MSR_VMX_CR4_FIXED1 0x489
505 #define MSR_VMX_PROCBASED_CTLS2 0x48b
506 #define MSR_VMX_EPT_VPID_CAP 0x48c
507 #define MSR_VMX_TRUE_PINBASED_CTLS 0x48d
508 #define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e
509 #define MSR_VMX_TRUE_EXIT_CTLS 0x48f
510 #define MSR_VMX_TRUE_ENTRY_CTLS 0x490
514 * Writes are not serializing.
516 #define MSR_APIC_000 0x800
517 #define MSR_APIC_ID 0x802
518 #define MSR_APIC_VERSION 0x803
519 #define MSR_APIC_TPR 0x808
520 #define MSR_APIC_EOI 0x80b
521 #define MSR_APIC_LDR 0x80d
522 #define MSR_APIC_SVR 0x80f
523 #define MSR_APIC_ISR0 0x810
524 #define MSR_APIC_ISR1 0x811
525 #define MSR_APIC_ISR2 0x812
526 #define MSR_APIC_ISR3 0x813
527 #define MSR_APIC_ISR4 0x814
528 #define MSR_APIC_ISR5 0x815
529 #define MSR_APIC_ISR6 0x816
530 #define MSR_APIC_ISR7 0x817
531 #define MSR_APIC_TMR0 0x818
532 #define MSR_APIC_IRR0 0x820
533 #define MSR_APIC_ESR 0x828
534 #define MSR_APIC_LVT_CMCI 0x82F
535 #define MSR_APIC_ICR 0x830
536 #define MSR_APIC_LVT_TIMER 0x832
537 #define MSR_APIC_LVT_THERMAL 0x833
538 #define MSR_APIC_LVT_PCINT 0x834
539 #define MSR_APIC_LVT_LINT0 0x835
540 #define MSR_APIC_LVT_LINT1 0x836
541 #define MSR_APIC_LVT_ERROR 0x837
542 #define MSR_APIC_ICR_TIMER 0x838
543 #define MSR_APIC_CCR_TIMER 0x839
544 #define MSR_APIC_DCR_TIMER 0x83e
545 #define MSR_APIC_SELF_IPI 0x83f
547 #define MSR_IA32_XSS 0xda0
550 * Constants related to MSR's.
552 #define APICBASE_RESERVED 0x000002ff
553 #define APICBASE_BSP 0x00000100
554 #define APICBASE_X2APIC 0x00000400
555 #define APICBASE_ENABLED 0x00000800
556 #define APICBASE_ADDRESS 0xfffff000
558 /* MSR_IA32_FEATURE_CONTROL related */
559 #define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */
560 #define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */
561 #define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */
563 /* MSR IA32_MISC_ENABLE */
564 #define IA32_MISC_EN_FASTSTR 0x0000000000000001ULL
565 #define IA32_MISC_EN_ATCCE 0x0000000000000008ULL
566 #define IA32_MISC_EN_PERFMON 0x0000000000000080ULL
567 #define IA32_MISC_EN_PEBSU 0x0000000000001000ULL
568 #define IA32_MISC_EN_ESSTE 0x0000000000010000ULL
569 #define IA32_MISC_EN_MONE 0x0000000000040000ULL
570 #define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL
571 #define IA32_MISC_EN_xTPRD 0x0000000000800000ULL
572 #define IA32_MISC_EN_XDD 0x0000000400000000ULL
575 * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel'
576 * document 336996-001 Speculative Execution Side Channel Mitigations.
578 /* MSR IA32_SPEC_CTRL */
579 #define IA32_SPEC_CTRL_IBRS 0x00000001
580 #define IA32_SPEC_CTRL_STIBP 0x00000002
582 /* MSR IA32_PRED_CMD */
583 #define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL
585 /* MSR IA32_FLUSH_CMD */
586 #define IA32_FLUSH_CMD_L1D 0x00000001
591 #define PAT_UNCACHEABLE 0x00
592 #define PAT_WRITE_COMBINING 0x01
593 #define PAT_WRITE_THROUGH 0x04
594 #define PAT_WRITE_PROTECTED 0x05
595 #define PAT_WRITE_BACK 0x06
596 #define PAT_UNCACHED 0x07
597 #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i)))
598 #define PAT_MASK(i) PAT_VALUE(i, 0xff)
601 * Constants related to MTRRs
603 #define MTRR_UNCACHEABLE 0x00
604 #define MTRR_WRITE_COMBINING 0x01
605 #define MTRR_WRITE_THROUGH 0x04
606 #define MTRR_WRITE_PROTECTED 0x05
607 #define MTRR_WRITE_BACK 0x06
608 #define MTRR_N64K 8 /* numbers of fixed-size entries */
611 #define MTRR_CAP_WC 0x0000000000000400
612 #define MTRR_CAP_FIXED 0x0000000000000100
613 #define MTRR_CAP_VCNT 0x00000000000000ff
614 #define MTRR_DEF_ENABLE 0x0000000000000800
615 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400
616 #define MTRR_DEF_TYPE 0x00000000000000ff
617 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000
618 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff
619 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000
620 #define MTRR_PHYSMASK_VALID 0x0000000000000800
623 * Cyrix configuration registers, accessible as IO ports.
625 #define CCR0 0xc0 /* Configuration control register 0 */
626 #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
628 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
629 #define CCR0_A20M 0x04 /* Enables A20M# input pin */
630 #define CCR0_KEN 0x08 /* Enables KEN# input pin */
631 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
632 #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
634 #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
636 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
638 #define CCR1 0xc1 /* Configuration control register 1 */
639 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
640 #define CCR1_SMI 0x02 /* Enables SMM pins */
641 #define CCR1_SMAC 0x04 /* System management memory access */
642 #define CCR1_MMAC 0x08 /* Main memory access */
643 #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
644 #define CCR1_SM3 0x80 /* SMM address space address region 3 */
647 #define CCR2_WB 0x02 /* Enables WB cache interface pins */
648 #define CCR2_SADS 0x02 /* Slow ADS */
649 #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
650 #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
651 #define CCR2_WT1 0x10 /* WT region 1 */
652 #define CCR2_WPR1 0x10 /* Write-protect region 1 */
653 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering
655 #define CCR2_BWRT 0x40 /* Enables burst write cycles */
656 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
659 #define CCR3_SMILOCK 0x01 /* SMM register lock */
660 #define CCR3_NMI 0x02 /* Enables NMI during SMM */
661 #define CCR3_LINBRST 0x04 /* Linear address burst cycles */
662 #define CCR3_SMMMODE 0x08 /* SMM Mode */
663 #define CCR3_MAPEN0 0x10 /* Enables Map0 */
664 #define CCR3_MAPEN1 0x20 /* Enables Map1 */
665 #define CCR3_MAPEN2 0x40 /* Enables Map2 */
666 #define CCR3_MAPEN3 0x80 /* Enables Map3 */
669 #define CCR4_IOMASK 0x07
670 #define CCR4_MEM 0x08 /* Enables momory bypassing */
671 #define CCR4_DTE 0x10 /* Enables directory table entry cache */
672 #define CCR4_FASTFPE 0x20 /* Fast FPU exception */
673 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */
676 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
677 #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
678 #define CCR5_LBR1 0x10 /* Local bus region 1 */
679 #define CCR5_ARREN 0x20 /* Enables ARR region */
685 /* Performance Control Register (5x86 only). */
687 #define PCR0_RSTK 0x01 /* Enables return stack */
688 #define PCR0_BTB 0x02 /* Enables branch target buffer */
689 #define PCR0_LOOP 0x04 /* Enables loop */
690 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
692 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
693 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
694 #define PCR0_LSSER 0x80 /* Disable reorder */
696 /* Device Identification Registers */
701 * Machine Check register constants.
703 #define MCG_CAP_COUNT 0x000000ff
704 #define MCG_CAP_CTL_P 0x00000100
705 #define MCG_CAP_EXT_P 0x00000200
706 #define MCG_CAP_CMCI_P 0x00000400
707 #define MCG_CAP_TES_P 0x00000800
708 #define MCG_CAP_EXT_CNT 0x00ff0000
709 #define MCG_CAP_SER_P 0x01000000
710 #define MCG_STATUS_RIPV 0x00000001
711 #define MCG_STATUS_EIPV 0x00000002
712 #define MCG_STATUS_MCIP 0x00000004
713 #define MCG_CTL_ENABLE 0xffffffffffffffff
714 #define MCG_CTL_DISABLE 0x0000000000000000
715 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
716 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
717 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
718 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
719 #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */
720 #define MC_STATUS_MCA_ERROR 0x000000000000ffff
721 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000
722 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000
723 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */
724 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */
725 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */
726 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */
727 #define MC_STATUS_PCC 0x0200000000000000
728 #define MC_STATUS_ADDRV 0x0400000000000000
729 #define MC_STATUS_MISCV 0x0800000000000000
730 #define MC_STATUS_EN 0x1000000000000000
731 #define MC_STATUS_UC 0x2000000000000000
732 #define MC_STATUS_OVER 0x4000000000000000
733 #define MC_STATUS_VAL 0x8000000000000000
734 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */
735 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */
736 #define MC_CTL2_THRESHOLD 0x0000000000007fff
737 #define MC_CTL2_CMCI_EN 0x0000000040000000
738 #define MC_AMDNB_BANK 4
739 #define MC_MISC_AMDNB_VAL 0x8000000000000000 /* Counter presence valid */
740 #define MC_MISC_AMDNB_CNTP 0x4000000000000000 /* Counter present */
741 #define MC_MISC_AMDNB_LOCK 0x2000000000000000 /* Register locked */
742 #define MC_MISC_AMDNB_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */
743 #define MC_MISC_AMDNB_LVT_SHIFT 52
744 #define MC_MISC_AMDNB_CNTEN 0x0008000000000000 /* Counter enabled */
745 #define MC_MISC_AMDNB_INT_MASK 0x0006000000000000 /* Interrupt type */
746 #define MC_MISC_AMDNB_INT_LVT 0x0002000000000000 /* Interrupt via Extended LVT */
747 #define MC_MISC_AMDNB_INT_SMI 0x0004000000000000 /* SMI */
748 #define MC_MISC_AMDNB_OVERFLOW 0x0001000000000000 /* Counter overflow */
749 #define MC_MISC_AMDNB_CNT_MASK 0x00000fff00000000 /* Counter value */
750 #define MC_MISC_AMDNB_CNT_SHIFT 32
751 #define MC_MISC_AMDNB_CNT_MAX 0xfff
752 #define MC_MISC_AMDNB_PTR_MASK 0x00000000ff000000 /* Pointer to additional registers */
753 #define MC_MISC_AMDNB_PTR_SHIFT 24
756 * The following four 3-byte registers control the non-cacheable regions.
757 * These registers must be written as three separate bytes.
759 * NCRx+0: A31-A24 of starting address
760 * NCRx+1: A23-A16 of starting address
761 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
763 * The non-cacheable region's starting address must be aligned to the
764 * size indicated by the NCR_SIZE_xx field.
771 #define NCR_SIZE_0K 0
772 #define NCR_SIZE_4K 1
773 #define NCR_SIZE_8K 2
774 #define NCR_SIZE_16K 3
775 #define NCR_SIZE_32K 4
776 #define NCR_SIZE_64K 5
777 #define NCR_SIZE_128K 6
778 #define NCR_SIZE_256K 7
779 #define NCR_SIZE_512K 8
780 #define NCR_SIZE_1M 9
781 #define NCR_SIZE_2M 10
782 #define NCR_SIZE_4M 11
783 #define NCR_SIZE_8M 12
784 #define NCR_SIZE_16M 13
785 #define NCR_SIZE_32M 14
786 #define NCR_SIZE_4G 15
789 * The address region registers are used to specify the location and
790 * size for the eight address regions.
792 * ARRx + 0: A31-A24 of start address
793 * ARRx + 1: A23-A16 of start address
794 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
805 #define ARR_SIZE_0K 0
806 #define ARR_SIZE_4K 1
807 #define ARR_SIZE_8K 2
808 #define ARR_SIZE_16K 3
809 #define ARR_SIZE_32K 4
810 #define ARR_SIZE_64K 5
811 #define ARR_SIZE_128K 6
812 #define ARR_SIZE_256K 7
813 #define ARR_SIZE_512K 8
814 #define ARR_SIZE_1M 9
815 #define ARR_SIZE_2M 10
816 #define ARR_SIZE_4M 11
817 #define ARR_SIZE_8M 12
818 #define ARR_SIZE_16M 13
819 #define ARR_SIZE_32M 14
820 #define ARR_SIZE_4G 15
823 * The region control registers specify the attributes associated with
824 * the ARRx addres regions.
835 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
836 #define RCR_RCE 0x01 /* Enables caching for ARR7. */
837 #define RCR_WWO 0x02 /* Weak write ordering. */
838 #define RCR_WL 0x04 /* Weak locking. */
839 #define RCR_WG 0x08 /* Write gathering. */
840 #define RCR_WT 0x10 /* Write-through. */
841 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
843 /* AMD Write Allocate Top-Of-Memory and Control Register */
844 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
845 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
846 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
849 #define MSR_EFER 0xc0000080 /* extended features */
850 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
851 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
852 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
853 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
854 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
855 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
856 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
857 #define MSR_PERFEVSEL0 0xc0010000
858 #define MSR_PERFEVSEL1 0xc0010001
859 #define MSR_PERFEVSEL2 0xc0010002
860 #define MSR_PERFEVSEL3 0xc0010003
861 #define MSR_K7_PERFCTR0 0xc0010004
862 #define MSR_K7_PERFCTR1 0xc0010005
863 #define MSR_K7_PERFCTR2 0xc0010006
864 #define MSR_K7_PERFCTR3 0xc0010007
865 #define MSR_SYSCFG 0xc0010010
866 #define MSR_HWCR 0xc0010015
867 #define MSR_IORRBASE0 0xc0010016
868 #define MSR_IORRMASK0 0xc0010017
869 #define MSR_IORRBASE1 0xc0010018
870 #define MSR_IORRMASK1 0xc0010019
871 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
872 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
873 #define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */
874 #define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */
875 #define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */
876 #define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */
877 #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */
878 #define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */
879 #define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */
880 #define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */
881 #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */
882 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
883 #define MSR_MC0_CTL_MASK 0xc0010044
884 #define MSR_VM_CR 0xc0010114 /* SVM: feature control */
885 #define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */
887 /* MSR_VM_CR related */
888 #define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */
890 /* VIA ACE crypto featureset: for via_feature_rng */
891 #define VIA_HAS_RNG 1 /* cpu has RNG */
893 /* VIA ACE crypto featureset: for via_feature_xcrypt */
894 #define VIA_HAS_AES 1 /* cpu has AES */
895 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
896 #define VIA_HAS_MM 4 /* cpu has RSA instructions */
897 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
899 /* Centaur Extended Feature flags */
900 #define VIA_CPUID_HAS_RNG 0x000004
901 #define VIA_CPUID_DO_RNG 0x000008
902 #define VIA_CPUID_HAS_ACE 0x000040
903 #define VIA_CPUID_DO_ACE 0x000080
904 #define VIA_CPUID_HAS_ACE2 0x000100
905 #define VIA_CPUID_DO_ACE2 0x000200
906 #define VIA_CPUID_HAS_PHE 0x000400
907 #define VIA_CPUID_DO_PHE 0x000800
908 #define VIA_CPUID_HAS_PMM 0x001000
909 #define VIA_CPUID_DO_PMM 0x002000
911 /* VIA ACE xcrypt-* instruction context control options */
912 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f
913 #define VIA_CRYPT_CWLO_ALG_M 0x00000070
914 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000
915 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080
916 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000
917 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080
918 #define VIA_CRYPT_CWLO_NORMAL 0x00000000
919 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100
920 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000
921 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200
922 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
923 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
924 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
926 #endif /* !_MACHINE_SPECIALREG_H_ */