2 * Copyright (c) 2013 The FreeBSD Foundation
5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
6 * under sponsorship from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/malloc.h>
38 #include <sys/interrupt.h>
39 #include <sys/kernel.h>
43 #include <sys/memdesc.h>
44 #include <sys/mutex.h>
45 #include <sys/sysctl.h>
47 #include <sys/taskqueue.h>
51 #include <dev/pci/pcireg.h>
52 #include <dev/pci/pcivar.h>
54 #include <vm/vm_extern.h>
55 #include <vm/vm_kern.h>
56 #include <vm/vm_object.h>
57 #include <vm/vm_page.h>
58 #include <vm/vm_map.h>
59 #include <machine/atomic.h>
60 #include <machine/bus.h>
61 #include <machine/md_var.h>
62 #include <machine/specialreg.h>
63 #include <x86/include/busdma_impl.h>
64 #include <x86/iommu/intel_reg.h>
65 #include <x86/iommu/busdma_dmar.h>
66 #include <x86/iommu/intel_dmar.h>
69 * busdma_dmar.c, the implementation of the busdma(9) interface using
70 * DMAR units from Intel VT-d.
74 dmar_bus_dma_is_dev_disabled(int domain, int bus, int slot, int func)
78 snprintf(str, sizeof(str), "hw.busdma.pci%d.%d.%d.%d.bounce",
79 domain, bus, slot, func);
80 env = kern_getenv(str);
88 * Given original device, find the requester ID that will be seen by
89 * the DMAR unit and used for page table lookup. PCI bridges may take
90 * ownership of transactions from downstream devices, so it may not be
91 * the same as the BSF of the target device. In those cases, all
92 * devices downstream of the bridge must share a single mapping
93 * domain, and must collectively be assigned to use either DMAR or
97 dmar_get_requester(device_t dev, uint16_t *rid)
100 device_t l, pci, pcib, pcip, pcibp, requester;
105 pci_class = devclass_find("pci");
108 *rid = pci_get_rid(dev);
111 * Walk the bridge hierarchy from the target device to the
112 * host port to find the translating bridge nearest the DMAR
116 pci = device_get_parent(l);
117 KASSERT(pci != NULL, ("dmar_get_requester(%s): NULL parent "
118 "for %s", device_get_name(dev), device_get_name(l)));
119 KASSERT(device_get_devclass(pci) == pci_class,
120 ("dmar_get_requester(%s): non-pci parent %s for %s",
121 device_get_name(dev), device_get_name(pci),
122 device_get_name(l)));
124 pcib = device_get_parent(pci);
125 KASSERT(pcib != NULL, ("dmar_get_requester(%s): NULL bridge "
126 "for %s", device_get_name(dev), device_get_name(pci)));
129 * The parent of our "bridge" isn't another PCI bus,
130 * so pcib isn't a PCI->PCI bridge but rather a host
131 * port, and the requester ID won't be translated
134 pcip = device_get_parent(pcib);
135 if (device_get_devclass(pcip) != pci_class)
137 pcibp = device_get_parent(pcip);
139 if (pci_find_cap(l, PCIY_EXPRESS, &cap_offset) == 0) {
141 * Do not stop the loop even if the target
142 * device is PCIe, because it is possible (but
143 * unlikely) to have a PCI->PCIe bridge
144 * somewhere in the hierarchy.
149 * Device is not PCIe, it cannot be seen as a
150 * requester by DMAR unit. Check whether the
153 bridge_is_pcie = pci_find_cap(pcib, PCIY_EXPRESS,
158 * Check for a buggy PCIe/PCI bridge that
159 * doesn't report the express capability. If
160 * the bridge above it is express but isn't a
161 * PCI bridge, then we know pcib is actually a
164 if (!bridge_is_pcie && pci_find_cap(pcibp,
165 PCIY_EXPRESS, &cap_offset) == 0) {
166 pcie_flags = pci_read_config(pcibp,
167 cap_offset + PCIER_FLAGS, 2);
168 if ((pcie_flags & PCIEM_FLAGS_TYPE) !=
169 PCIEM_TYPE_PCI_BRIDGE)
170 bridge_is_pcie = true;
173 if (bridge_is_pcie) {
175 * The current device is not PCIe, but
176 * the bridge above it is. This is a
177 * PCIe->PCI bridge. Assume that the
178 * requester ID will be the secondary
179 * bus number with slot and function
182 * XXX: Doesn't handle the case where
183 * the bridge is PCIe->PCI-X, and the
184 * bridge will only take ownership of
185 * requests in some cases. We should
186 * provide context entries with the
187 * same page tables for taken and
188 * non-taken transactions.
190 *rid = PCI_RID(pci_get_bus(l), 0, 0);
194 * Neither the device nor the bridge
195 * above it are PCIe. This is a
196 * conventional PCI->PCI bridge, which
197 * will use the bridge's BSF as the
200 *rid = pci_get_rid(pcib);
209 dmar_instantiate_ctx(struct dmar_unit *dmar, device_t dev, bool rmrr)
212 struct dmar_ctx *ctx;
216 requester = dmar_get_requester(dev, &rid);
219 * If the user requested the IOMMU disabled for the device, we
220 * cannot disable the DMAR, due to possibility of other
221 * devices on the same DMAR still requiring translation.
222 * Instead provide the identity mapping for the device
225 disabled = dmar_bus_dma_is_dev_disabled(pci_get_domain(requester),
226 pci_get_bus(requester), pci_get_slot(requester),
227 pci_get_function(requester));
228 ctx = dmar_get_ctx(dmar, requester, rid, disabled, rmrr);
233 * Keep the first reference on context, release the
237 if ((ctx->flags & DMAR_CTX_DISABLED) == 0) {
238 ctx->flags |= DMAR_CTX_DISABLED;
241 dmar_free_ctx_locked(dmar, ctx);
249 dmar_get_dma_tag(device_t dev, device_t child)
251 struct dmar_unit *dmar;
252 struct dmar_ctx *ctx;
255 dmar = dmar_find(child);
256 /* Not in scope of any DMAR ? */
259 if (!dmar->dma_enabled)
261 dmar_quirks_pre_use(dmar);
262 dmar_instantiate_rmrr_ctxs(dmar);
264 ctx = dmar_instantiate_ctx(dmar, child, false);
265 res = ctx == NULL ? NULL : (bus_dma_tag_t)&ctx->ctx_tag;
269 static MALLOC_DEFINE(M_DMAR_DMAMAP, "dmar_dmamap", "Intel DMAR DMA Map");
271 static void dmar_bus_schedule_dmamap(struct dmar_unit *unit,
272 struct bus_dmamap_dmar *map);
275 dmar_bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment,
276 bus_addr_t boundary, bus_addr_t lowaddr, bus_addr_t highaddr,
277 bus_dma_filter_t *filter, void *filterarg, bus_size_t maxsize,
278 int nsegments, bus_size_t maxsegsz, int flags, bus_dma_lock_t *lockfunc,
279 void *lockfuncarg, bus_dma_tag_t *dmat)
281 struct bus_dma_tag_dmar *newtag, *oldtag;
285 error = common_bus_dma_tag_create(parent != NULL ?
286 &((struct bus_dma_tag_dmar *)parent)->common : NULL, alignment,
287 boundary, lowaddr, highaddr, filter, filterarg, maxsize,
288 nsegments, maxsegsz, flags, lockfunc, lockfuncarg,
289 sizeof(struct bus_dma_tag_dmar), (void **)&newtag);
293 oldtag = (struct bus_dma_tag_dmar *)parent;
294 newtag->common.impl = &bus_dma_dmar_impl;
295 newtag->ctx = oldtag->ctx;
296 newtag->owner = oldtag->owner;
298 *dmat = (bus_dma_tag_t)newtag;
300 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d",
301 __func__, newtag, (newtag != NULL ? newtag->common.flags : 0),
307 dmar_bus_dma_tag_destroy(bus_dma_tag_t dmat1)
309 struct bus_dma_tag_dmar *dmat, *dmat_copy, *parent;
313 dmat_copy = dmat = (struct bus_dma_tag_dmar *)dmat1;
316 if (dmat->map_count != 0) {
320 while (dmat != NULL) {
321 parent = (struct bus_dma_tag_dmar *)dmat->common.parent;
322 if (atomic_fetchadd_int(&dmat->common.ref_count, -1) ==
324 if (dmat == &dmat->ctx->ctx_tag)
325 dmar_free_ctx(dmat->ctx);
326 free(dmat->segments, M_DMAR_DMAMAP);
327 free(dmat, M_DEVBUF);
334 CTR3(KTR_BUSDMA, "%s tag %p error %d", __func__, dmat_copy, error);
339 dmar_bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp)
341 struct bus_dma_tag_dmar *tag;
342 struct bus_dmamap_dmar *map;
344 tag = (struct bus_dma_tag_dmar *)dmat;
345 map = malloc(sizeof(*map), M_DMAR_DMAMAP, M_NOWAIT | M_ZERO);
350 if (tag->segments == NULL) {
351 tag->segments = malloc(sizeof(bus_dma_segment_t) *
352 tag->common.nsegments, M_DMAR_DMAMAP, M_NOWAIT);
353 if (tag->segments == NULL) {
354 free(map, M_DMAR_DMAMAP);
359 TAILQ_INIT(&map->map_entries);
362 map->cansleep = false;
364 *mapp = (bus_dmamap_t)map;
370 dmar_bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map1)
372 struct bus_dma_tag_dmar *tag;
373 struct bus_dmamap_dmar *map;
375 tag = (struct bus_dma_tag_dmar *)dmat;
376 map = (struct bus_dmamap_dmar *)map1;
378 DMAR_CTX_LOCK(tag->ctx);
379 if (!TAILQ_EMPTY(&map->map_entries)) {
380 DMAR_CTX_UNLOCK(tag->ctx);
383 DMAR_CTX_UNLOCK(tag->ctx);
384 free(map, M_DMAR_DMAMAP);
392 dmar_bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags,
395 struct bus_dma_tag_dmar *tag;
396 struct bus_dmamap_dmar *map;
400 error = dmar_bus_dmamap_create(dmat, flags, mapp);
404 mflags = (flags & BUS_DMA_NOWAIT) != 0 ? M_NOWAIT : M_WAITOK;
405 mflags |= (flags & BUS_DMA_ZERO) != 0 ? M_ZERO : 0;
406 attr = (flags & BUS_DMA_NOCACHE) != 0 ? VM_MEMATTR_UNCACHEABLE :
409 tag = (struct bus_dma_tag_dmar *)dmat;
410 map = (struct bus_dmamap_dmar *)*mapp;
412 if (tag->common.maxsize < PAGE_SIZE &&
413 tag->common.alignment <= tag->common.maxsize &&
414 attr == VM_MEMATTR_DEFAULT) {
415 *vaddr = malloc(tag->common.maxsize, M_DEVBUF, mflags);
416 map->flags |= BUS_DMAMAP_DMAR_MALLOC;
418 *vaddr = (void *)kmem_alloc_attr(kernel_arena,
419 tag->common.maxsize, mflags, 0ul, BUS_SPACE_MAXADDR,
421 map->flags |= BUS_DMAMAP_DMAR_KMEM_ALLOC;
423 if (*vaddr == NULL) {
424 dmar_bus_dmamap_destroy(dmat, *mapp);
432 dmar_bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map1)
434 struct bus_dma_tag_dmar *tag;
435 struct bus_dmamap_dmar *map;
437 tag = (struct bus_dma_tag_dmar *)dmat;
438 map = (struct bus_dmamap_dmar *)map1;
440 if ((map->flags & BUS_DMAMAP_DMAR_MALLOC) != 0) {
441 free(vaddr, M_DEVBUF);
442 map->flags &= ~BUS_DMAMAP_DMAR_MALLOC;
444 KASSERT((map->flags & BUS_DMAMAP_DMAR_KMEM_ALLOC) != 0,
445 ("dmar_bus_dmamem_free for non alloced map %p", map));
446 kmem_free(kernel_arena, (vm_offset_t)vaddr, tag->common.maxsize);
447 map->flags &= ~BUS_DMAMAP_DMAR_KMEM_ALLOC;
450 dmar_bus_dmamap_destroy(dmat, map1);
454 dmar_bus_dmamap_load_something1(struct bus_dma_tag_dmar *tag,
455 struct bus_dmamap_dmar *map, vm_page_t *ma, int offset, bus_size_t buflen,
456 int flags, bus_dma_segment_t *segs, int *segp,
457 struct dmar_map_entries_tailq *unroll_list)
459 struct dmar_ctx *ctx;
460 struct dmar_map_entry *entry;
463 int error, idx, gas_flags, seg;
465 KASSERT(offset < DMAR_PAGE_SIZE, ("offset %d", offset));
467 segs = tag->segments;
474 if (seg >= tag->common.nsegments) {
478 buflen1 = buflen > tag->common.maxsegsz ?
479 tag->common.maxsegsz : buflen;
480 size = round_page(offset + buflen1);
483 * (Too) optimistically allow split if there are more
484 * then one segments left.
486 gas_flags = map->cansleep ? DMAR_GM_CANWAIT : 0;
487 if (seg + 1 < tag->common.nsegments)
488 gas_flags |= DMAR_GM_CANSPLIT;
490 error = dmar_gas_map(ctx, &tag->common, size, offset,
491 DMAR_MAP_ENTRY_READ | DMAR_MAP_ENTRY_WRITE,
492 gas_flags, ma + idx, &entry);
495 if ((gas_flags & DMAR_GM_CANSPLIT) != 0) {
496 KASSERT(size >= entry->end - entry->start,
497 ("split increased entry size %jx %jx %jx",
498 (uintmax_t)size, (uintmax_t)entry->start,
499 (uintmax_t)entry->end));
500 size = entry->end - entry->start;
504 KASSERT(entry->end - entry->start == size,
505 ("no split allowed %jx %jx %jx",
506 (uintmax_t)size, (uintmax_t)entry->start,
507 (uintmax_t)entry->end));
509 if (offset + buflen1 > size)
510 buflen1 = size - offset;
511 if (buflen1 > tag->common.maxsegsz)
512 buflen1 = tag->common.maxsegsz;
514 KASSERT(((entry->start + offset) & (tag->common.alignment - 1))
516 ("alignment failed: ctx %p start 0x%jx offset %x "
517 "align 0x%jx", ctx, (uintmax_t)entry->start, offset,
518 (uintmax_t)tag->common.alignment));
519 KASSERT(entry->end <= tag->common.lowaddr ||
520 entry->start >= tag->common.highaddr,
521 ("entry placement failed: ctx %p start 0x%jx end 0x%jx "
522 "lowaddr 0x%jx highaddr 0x%jx", ctx,
523 (uintmax_t)entry->start, (uintmax_t)entry->end,
524 (uintmax_t)tag->common.lowaddr,
525 (uintmax_t)tag->common.highaddr));
526 KASSERT(dmar_test_boundary(entry->start + offset, buflen1,
527 tag->common.boundary),
528 ("boundary failed: ctx %p start 0x%jx end 0x%jx "
529 "boundary 0x%jx", ctx, (uintmax_t)entry->start,
530 (uintmax_t)entry->end, (uintmax_t)tag->common.boundary));
531 KASSERT(buflen1 <= tag->common.maxsegsz,
532 ("segment too large: ctx %p start 0x%jx end 0x%jx "
533 "buflen1 0x%jx maxsegsz 0x%jx", ctx,
534 (uintmax_t)entry->start, (uintmax_t)entry->end,
535 (uintmax_t)buflen1, (uintmax_t)tag->common.maxsegsz));
538 TAILQ_INSERT_TAIL(&map->map_entries, entry, dmamap_link);
539 entry->flags |= DMAR_MAP_ENTRY_MAP;
540 DMAR_CTX_UNLOCK(ctx);
541 TAILQ_INSERT_TAIL(unroll_list, entry, unroll_link);
543 segs[seg].ds_addr = entry->start + offset;
544 segs[seg].ds_len = buflen1;
546 idx += OFF_TO_IDX(trunc_page(offset + buflen1));
548 offset &= DMAR_PAGE_MASK;
557 dmar_bus_dmamap_load_something(struct bus_dma_tag_dmar *tag,
558 struct bus_dmamap_dmar *map, vm_page_t *ma, int offset, bus_size_t buflen,
559 int flags, bus_dma_segment_t *segs, int *segp)
561 struct dmar_ctx *ctx;
562 struct dmar_map_entry *entry, *entry1;
563 struct dmar_map_entries_tailq unroll_list;
567 atomic_add_long(&ctx->loads, 1);
569 TAILQ_INIT(&unroll_list);
570 error = dmar_bus_dmamap_load_something1(tag, map, ma, offset,
571 buflen, flags, segs, segp, &unroll_list);
574 * The busdma interface does not allow us to report
575 * partial buffer load, so unfortunately we have to
576 * revert all work done.
579 TAILQ_FOREACH_SAFE(entry, &unroll_list, unroll_link,
582 * No entries other than what we have created
583 * during the failed run might have been
584 * inserted there in between, since we own ctx
587 TAILQ_REMOVE(&map->map_entries, entry, dmamap_link);
588 TAILQ_REMOVE(&unroll_list, entry, unroll_link);
589 TAILQ_INSERT_TAIL(&ctx->unload_entries, entry,
592 DMAR_CTX_UNLOCK(ctx);
593 taskqueue_enqueue(ctx->dmar->delayed_taskqueue,
597 if (error == ENOMEM && (flags & BUS_DMA_NOWAIT) == 0 &&
600 if (error == EINPROGRESS)
601 dmar_bus_schedule_dmamap(ctx->dmar, map);
606 dmar_bus_dmamap_load_ma(bus_dma_tag_t dmat, bus_dmamap_t map1,
607 struct vm_page **ma, bus_size_t tlen, int ma_offs, int flags,
608 bus_dma_segment_t *segs, int *segp)
610 struct bus_dma_tag_dmar *tag;
611 struct bus_dmamap_dmar *map;
613 tag = (struct bus_dma_tag_dmar *)dmat;
614 map = (struct bus_dmamap_dmar *)map1;
615 return (dmar_bus_dmamap_load_something(tag, map, ma, ma_offs, tlen,
620 dmar_bus_dmamap_load_phys(bus_dma_tag_t dmat, bus_dmamap_t map1,
621 vm_paddr_t buf, bus_size_t buflen, int flags, bus_dma_segment_t *segs,
624 struct bus_dma_tag_dmar *tag;
625 struct bus_dmamap_dmar *map;
627 vm_paddr_t pstart, pend;
628 int error, i, ma_cnt, offset;
630 tag = (struct bus_dma_tag_dmar *)dmat;
631 map = (struct bus_dmamap_dmar *)map1;
632 pstart = trunc_page(buf);
633 pend = round_page(buf + buflen);
634 offset = buf & PAGE_MASK;
635 ma_cnt = OFF_TO_IDX(pend - pstart);
636 ma = malloc(sizeof(vm_page_t) * ma_cnt, M_DEVBUF, map->cansleep ?
637 M_WAITOK : M_NOWAIT);
640 for (i = 0; i < ma_cnt; i++)
641 ma[i] = PHYS_TO_VM_PAGE(pstart + i * PAGE_SIZE);
642 error = dmar_bus_dmamap_load_something(tag, map, ma, offset, buflen,
649 dmar_bus_dmamap_load_buffer(bus_dma_tag_t dmat, bus_dmamap_t map1, void *buf,
650 bus_size_t buflen, pmap_t pmap, int flags, bus_dma_segment_t *segs,
653 struct bus_dma_tag_dmar *tag;
654 struct bus_dmamap_dmar *map;
656 vm_paddr_t pstart, pend, paddr;
657 int error, i, ma_cnt, offset;
659 tag = (struct bus_dma_tag_dmar *)dmat;
660 map = (struct bus_dmamap_dmar *)map1;
661 pstart = trunc_page((vm_offset_t)buf);
662 pend = round_page((vm_offset_t)buf + buflen);
663 offset = (vm_offset_t)buf & PAGE_MASK;
664 ma_cnt = OFF_TO_IDX(pend - pstart);
665 ma = malloc(sizeof(vm_page_t) * ma_cnt, M_DEVBUF, map->cansleep ?
666 M_WAITOK : M_NOWAIT);
671 * If dumping, do not attempt to call
672 * PHYS_TO_VM_PAGE() at all. It may return non-NULL
673 * but the vm_page returned might be not initialized,
674 * e.g. for the kernel itself.
676 KASSERT(pmap == kernel_pmap, ("non-kernel address write"));
677 fma = malloc(sizeof(struct vm_page) * ma_cnt, M_DEVBUF,
678 M_ZERO | (map->cansleep ? M_WAITOK : M_NOWAIT));
683 for (i = 0; i < ma_cnt; i++, pstart += PAGE_SIZE) {
684 paddr = pmap_kextract(pstart);
685 vm_page_initfake(&fma[i], paddr, VM_MEMATTR_DEFAULT);
690 for (i = 0; i < ma_cnt; i++, pstart += PAGE_SIZE) {
691 if (pmap == kernel_pmap)
692 paddr = pmap_kextract(pstart);
694 paddr = pmap_extract(pmap, pstart);
695 ma[i] = PHYS_TO_VM_PAGE(paddr);
696 KASSERT(VM_PAGE_TO_PHYS(ma[i]) == paddr,
697 ("PHYS_TO_VM_PAGE failed %jx %jx m %p",
698 (uintmax_t)paddr, (uintmax_t)VM_PAGE_TO_PHYS(ma[i]),
702 error = dmar_bus_dmamap_load_something(tag, map, ma, offset, buflen,
710 dmar_bus_dmamap_waitok(bus_dma_tag_t dmat, bus_dmamap_t map1,
711 struct memdesc *mem, bus_dmamap_callback_t *callback, void *callback_arg)
713 struct bus_dmamap_dmar *map;
717 map = (struct bus_dmamap_dmar *)map1;
719 map->tag = (struct bus_dma_tag_dmar *)dmat;
720 map->callback = callback;
721 map->callback_arg = callback_arg;
724 static bus_dma_segment_t *
725 dmar_bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map1,
726 bus_dma_segment_t *segs, int nsegs, int error)
728 struct bus_dma_tag_dmar *tag;
729 struct bus_dmamap_dmar *map;
731 tag = (struct bus_dma_tag_dmar *)dmat;
732 map = (struct bus_dmamap_dmar *)map1;
735 KASSERT(map->cansleep,
736 ("map not locked and not sleepable context %p", map));
739 * We are called from the delayed context. Relock the
742 (tag->common.lockfunc)(tag->common.lockfuncarg, BUS_DMA_LOCK);
747 segs = tag->segments;
752 * The limitations of busdma KPI forces the dmar to perform the actual
753 * unload, consisting of the unmapping of the map entries page tables,
754 * from the delayed context on i386, since page table page mapping
755 * might require a sleep to be successfull. The unfortunate
756 * consequence is that the DMA requests can be served some time after
757 * the bus_dmamap_unload() call returned.
759 * On amd64, we assume that sf allocation cannot fail.
762 dmar_bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map1)
764 struct bus_dma_tag_dmar *tag;
765 struct bus_dmamap_dmar *map;
766 struct dmar_ctx *ctx;
767 #if defined(__amd64__)
768 struct dmar_map_entries_tailq entries;
771 tag = (struct bus_dma_tag_dmar *)dmat;
772 map = (struct bus_dmamap_dmar *)map1;
774 atomic_add_long(&ctx->unloads, 1);
776 #if defined(__i386__)
778 TAILQ_CONCAT(&ctx->unload_entries, &map->map_entries, dmamap_link);
779 DMAR_CTX_UNLOCK(ctx);
780 taskqueue_enqueue(ctx->dmar->delayed_taskqueue, &ctx->unload_task);
781 #else /* defined(__amd64__) */
782 TAILQ_INIT(&entries);
784 TAILQ_CONCAT(&entries, &map->map_entries, dmamap_link);
785 DMAR_CTX_UNLOCK(ctx);
786 THREAD_NO_SLEEPING();
787 dmar_ctx_unload(ctx, &entries, false);
788 THREAD_SLEEPING_OK();
789 KASSERT(TAILQ_EMPTY(&entries), ("lazy dmar_ctx_unload %p", ctx));
794 dmar_bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map,
799 struct bus_dma_impl bus_dma_dmar_impl = {
800 .tag_create = dmar_bus_dma_tag_create,
801 .tag_destroy = dmar_bus_dma_tag_destroy,
802 .map_create = dmar_bus_dmamap_create,
803 .map_destroy = dmar_bus_dmamap_destroy,
804 .mem_alloc = dmar_bus_dmamem_alloc,
805 .mem_free = dmar_bus_dmamem_free,
806 .load_phys = dmar_bus_dmamap_load_phys,
807 .load_buffer = dmar_bus_dmamap_load_buffer,
808 .load_ma = dmar_bus_dmamap_load_ma,
809 .map_waitok = dmar_bus_dmamap_waitok,
810 .map_complete = dmar_bus_dmamap_complete,
811 .map_unload = dmar_bus_dmamap_unload,
812 .map_sync = dmar_bus_dmamap_sync
816 dmar_bus_task_dmamap(void *arg, int pending)
818 struct bus_dma_tag_dmar *tag;
819 struct bus_dmamap_dmar *map;
820 struct dmar_unit *unit;
821 struct dmar_ctx *ctx;
825 while ((map = TAILQ_FIRST(&unit->delayed_maps)) != NULL) {
826 TAILQ_REMOVE(&unit->delayed_maps, map, delay_link);
830 map->cansleep = true;
832 bus_dmamap_load_mem((bus_dma_tag_t)tag, (bus_dmamap_t)map,
833 &map->mem, map->callback, map->callback_arg,
835 map->cansleep = false;
837 (tag->common.lockfunc)(tag->common.lockfuncarg,
841 map->cansleep = false;
848 dmar_bus_schedule_dmamap(struct dmar_unit *unit, struct bus_dmamap_dmar *map)
850 struct dmar_ctx *ctx;
855 TAILQ_INSERT_TAIL(&unit->delayed_maps, map, delay_link);
857 taskqueue_enqueue(unit->delayed_taskqueue, &unit->dmamap_load_task);
861 dmar_init_busdma(struct dmar_unit *unit)
864 unit->dma_enabled = 1;
865 TUNABLE_INT_FETCH("hw.dmar.dma", &unit->dma_enabled);
866 TAILQ_INIT(&unit->delayed_maps);
867 TASK_INIT(&unit->dmamap_load_task, 0, dmar_bus_task_dmamap, unit);
868 unit->delayed_taskqueue = taskqueue_create("dmar", M_WAITOK,
869 taskqueue_thread_enqueue, &unit->delayed_taskqueue);
870 taskqueue_start_threads(&unit->delayed_taskqueue, 1, PI_DISK,
871 "dmar%d busdma taskq", unit->unit);
876 dmar_fini_busdma(struct dmar_unit *unit)
879 if (unit->delayed_taskqueue == NULL)
882 taskqueue_drain(unit->delayed_taskqueue, &unit->dmamap_load_task);
883 taskqueue_free(unit->delayed_taskqueue);
884 unit->delayed_taskqueue = NULL;