2 * Copyright (c) 2013 The FreeBSD Foundation
5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
6 * under sponsorship from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/malloc.h>
38 #include <sys/interrupt.h>
39 #include <sys/kernel.h>
43 #include <sys/memdesc.h>
44 #include <sys/mutex.h>
45 #include <sys/sysctl.h>
47 #include <sys/taskqueue.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcivar.h>
53 #include <vm/vm_extern.h>
54 #include <vm/vm_kern.h>
55 #include <vm/vm_object.h>
56 #include <vm/vm_page.h>
57 #include <vm/vm_map.h>
58 #include <machine/atomic.h>
59 #include <machine/bus.h>
60 #include <machine/md_var.h>
61 #include <machine/specialreg.h>
62 #include <x86/include/busdma_impl.h>
63 #include <x86/iommu/intel_reg.h>
64 #include <x86/iommu/busdma_dmar.h>
65 #include <x86/iommu/intel_dmar.h>
68 * busdma_dmar.c, the implementation of the busdma(9) interface using
69 * DMAR units from Intel VT-d.
73 dmar_bus_dma_is_dev_disabled(int domain, int bus, int slot, int func)
77 snprintf(str, sizeof(str), "hw.busdma.pci%d.%d.%d.%d.bounce",
78 domain, bus, slot, func);
87 * Given original device, find the requester ID that will be seen by
88 * the DMAR unit and used for page table lookup. PCI bridges may take
89 * ownership of transactions from downstream devices, so it may not be
90 * the same as the BSF of the target device. In those cases, all
91 * devices downstream of the bridge must share a single mapping
92 * domain, and must collectively be assigned to use either DMAR or
96 dmar_get_requester(device_t dev, uint16_t *rid)
99 device_t pci, pcib, requester;
102 pci_class = devclass_find("pci");
105 *rid = pci_get_rid(dev);
108 * Walk the bridge hierarchy from the target device to the
109 * host port to find the translating bridge nearest the DMAR
113 pci = device_get_parent(dev);
114 KASSERT(pci != NULL, ("NULL parent for pci%d:%d:%d:%d",
115 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
116 pci_get_function(dev)));
117 KASSERT(device_get_devclass(pci) == pci_class,
118 ("Non-pci parent for pci%d:%d:%d:%d",
119 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
120 pci_get_function(dev)));
122 pcib = device_get_parent(pci);
123 KASSERT(pcib != NULL, ("NULL bridge for pci%d:%d:%d:%d",
124 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
125 pci_get_function(dev)));
128 * The parent of our "bridge" isn't another PCI bus,
129 * so pcib isn't a PCI->PCI bridge but rather a host
130 * port, and the requester ID won't be translated
133 if (device_get_devclass(device_get_parent(pcib)) != pci_class)
136 if (pci_find_cap(dev, PCIY_EXPRESS, &cap_offset) != 0) {
138 * Device is not PCIe, it cannot be seen as a
139 * requester by DMAR unit.
143 /* Check whether the bus above is PCIe. */
144 if (pci_find_cap(pcib, PCIY_EXPRESS,
147 * The current device is not PCIe, but
148 * the bridge above it is. This is a
149 * PCIe->PCI bridge. Assume that the
150 * requester ID will be the secondary
151 * bus number with slot and function
154 * XXX: Doesn't handle the case where
155 * the bridge is PCIe->PCI-X, and the
156 * bridge will only take ownership of
157 * requests in some cases. We should
158 * provide context entries with the
159 * same page tables for taken and
160 * non-taken transactions.
162 *rid = PCI_RID(pci_get_bus(dev), 0, 0);
165 * Neither the device nor the bridge
166 * above it are PCIe. This is a
167 * conventional PCI->PCI bridge, which
168 * will use the bridge's BSF as the
171 *rid = pci_get_rid(pcib);
175 * Do not stop the loop even if the target device is
176 * PCIe, because it is possible (but unlikely) to have
177 * a PCI->PCIe bridge somewhere in the hierarchy.
186 dmar_instantiate_ctx(struct dmar_unit *dmar, device_t dev, bool rmrr)
189 struct dmar_ctx *ctx;
193 requester = dmar_get_requester(dev, &rid);
196 * If the user requested the IOMMU disabled for the device, we
197 * cannot disable the DMAR, due to possibility of other
198 * devices on the same DMAR still requiring translation.
199 * Instead provide the identity mapping for the device
202 disabled = dmar_bus_dma_is_dev_disabled(pci_get_domain(requester),
203 pci_get_bus(requester), pci_get_slot(requester),
204 pci_get_function(requester));
205 ctx = dmar_get_ctx(dmar, requester, rid, disabled, rmrr);
210 * Keep the first reference on context, release the
214 if ((ctx->flags & DMAR_CTX_DISABLED) == 0) {
215 ctx->flags |= DMAR_CTX_DISABLED;
218 dmar_free_ctx_locked(dmar, ctx);
226 dmar_get_dma_tag(device_t dev, device_t child)
228 struct dmar_unit *dmar;
229 struct dmar_ctx *ctx;
232 dmar = dmar_find(child);
233 /* Not in scope of any DMAR ? */
236 dmar_quirks_pre_use(dmar);
237 dmar_instantiate_rmrr_ctxs(dmar);
239 ctx = dmar_instantiate_ctx(dmar, child, false);
240 res = ctx == NULL ? NULL : (bus_dma_tag_t)&ctx->ctx_tag;
244 static MALLOC_DEFINE(M_DMAR_DMAMAP, "dmar_dmamap", "Intel DMAR DMA Map");
246 static void dmar_bus_schedule_dmamap(struct dmar_unit *unit,
247 struct bus_dmamap_dmar *map);
250 dmar_bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment,
251 bus_addr_t boundary, bus_addr_t lowaddr, bus_addr_t highaddr,
252 bus_dma_filter_t *filter, void *filterarg, bus_size_t maxsize,
253 int nsegments, bus_size_t maxsegsz, int flags, bus_dma_lock_t *lockfunc,
254 void *lockfuncarg, bus_dma_tag_t *dmat)
256 struct bus_dma_tag_dmar *newtag, *oldtag;
260 error = common_bus_dma_tag_create(parent != NULL ?
261 &((struct bus_dma_tag_dmar *)parent)->common : NULL, alignment,
262 boundary, lowaddr, highaddr, filter, filterarg, maxsize,
263 nsegments, maxsegsz, flags, lockfunc, lockfuncarg,
264 sizeof(struct bus_dma_tag_dmar), (void **)&newtag);
268 oldtag = (struct bus_dma_tag_dmar *)parent;
269 newtag->common.impl = &bus_dma_dmar_impl;
270 newtag->ctx = oldtag->ctx;
271 newtag->owner = oldtag->owner;
273 *dmat = (bus_dma_tag_t)newtag;
275 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d",
276 __func__, newtag, (newtag != NULL ? newtag->common.flags : 0),
282 dmar_bus_dma_tag_destroy(bus_dma_tag_t dmat1)
284 struct bus_dma_tag_dmar *dmat, *dmat_copy, *parent;
288 dmat_copy = dmat = (struct bus_dma_tag_dmar *)dmat1;
291 if (dmat->map_count != 0) {
295 while (dmat != NULL) {
296 parent = (struct bus_dma_tag_dmar *)dmat->common.parent;
297 if (atomic_fetchadd_int(&dmat->common.ref_count, -1) ==
299 if (dmat == &dmat->ctx->ctx_tag)
300 dmar_free_ctx(dmat->ctx);
301 free(dmat->segments, M_DMAR_DMAMAP);
302 free(dmat, M_DEVBUF);
309 CTR3(KTR_BUSDMA, "%s tag %p error %d", __func__, dmat_copy, error);
314 dmar_bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp)
316 struct bus_dma_tag_dmar *tag;
317 struct bus_dmamap_dmar *map;
319 tag = (struct bus_dma_tag_dmar *)dmat;
320 map = malloc(sizeof(*map), M_DMAR_DMAMAP, M_NOWAIT | M_ZERO);
325 if (tag->segments == NULL) {
326 tag->segments = malloc(sizeof(bus_dma_segment_t) *
327 tag->common.nsegments, M_DMAR_DMAMAP, M_NOWAIT);
328 if (tag->segments == NULL) {
329 free(map, M_DMAR_DMAMAP);
334 TAILQ_INIT(&map->map_entries);
337 map->cansleep = false;
339 *mapp = (bus_dmamap_t)map;
345 dmar_bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map1)
347 struct bus_dma_tag_dmar *tag;
348 struct bus_dmamap_dmar *map;
350 tag = (struct bus_dma_tag_dmar *)dmat;
351 map = (struct bus_dmamap_dmar *)map1;
353 DMAR_CTX_LOCK(tag->ctx);
354 if (!TAILQ_EMPTY(&map->map_entries)) {
355 DMAR_CTX_UNLOCK(tag->ctx);
358 DMAR_CTX_UNLOCK(tag->ctx);
359 free(map, M_DMAR_DMAMAP);
367 dmar_bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags,
370 struct bus_dma_tag_dmar *tag;
371 struct bus_dmamap_dmar *map;
375 error = dmar_bus_dmamap_create(dmat, flags, mapp);
379 mflags = (flags & BUS_DMA_NOWAIT) != 0 ? M_NOWAIT : M_WAITOK;
380 mflags |= (flags & BUS_DMA_ZERO) != 0 ? M_ZERO : 0;
381 attr = (flags & BUS_DMA_NOCACHE) != 0 ? VM_MEMATTR_UNCACHEABLE :
384 tag = (struct bus_dma_tag_dmar *)dmat;
385 map = (struct bus_dmamap_dmar *)*mapp;
387 if (tag->common.maxsize < PAGE_SIZE &&
388 tag->common.alignment <= tag->common.maxsize &&
389 attr == VM_MEMATTR_DEFAULT) {
390 *vaddr = malloc(tag->common.maxsize, M_DEVBUF, mflags);
391 map->flags |= BUS_DMAMAP_DMAR_MALLOC;
393 *vaddr = (void *)kmem_alloc_attr(kernel_arena,
394 tag->common.maxsize, mflags, 0ul, BUS_SPACE_MAXADDR,
396 map->flags |= BUS_DMAMAP_DMAR_KMEM_ALLOC;
398 if (*vaddr == NULL) {
399 dmar_bus_dmamap_destroy(dmat, *mapp);
407 dmar_bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map1)
409 struct bus_dma_tag_dmar *tag;
410 struct bus_dmamap_dmar *map;
412 tag = (struct bus_dma_tag_dmar *)dmat;
413 map = (struct bus_dmamap_dmar *)map1;
415 if ((map->flags & BUS_DMAMAP_DMAR_MALLOC) != 0) {
416 free(vaddr, M_DEVBUF);
417 map->flags &= ~BUS_DMAMAP_DMAR_MALLOC;
419 KASSERT((map->flags & BUS_DMAMAP_DMAR_KMEM_ALLOC) != 0,
420 ("dmar_bus_dmamem_free for non alloced map %p", map));
421 kmem_free(kernel_arena, (vm_offset_t)vaddr, tag->common.maxsize);
422 map->flags &= ~BUS_DMAMAP_DMAR_KMEM_ALLOC;
425 dmar_bus_dmamap_destroy(dmat, map1);
429 dmar_bus_dmamap_load_something1(struct bus_dma_tag_dmar *tag,
430 struct bus_dmamap_dmar *map, vm_page_t *ma, int offset, bus_size_t buflen,
431 int flags, bus_dma_segment_t *segs, int *segp,
432 struct dmar_map_entries_tailq *unroll_list)
434 struct dmar_ctx *ctx;
435 struct dmar_map_entry *entry;
438 int error, idx, gas_flags, seg;
441 segs = tag->segments;
448 if (seg >= tag->common.nsegments) {
452 buflen1 = buflen > tag->common.maxsegsz ?
453 tag->common.maxsegsz : buflen;
455 size = round_page(offset + buflen1);
458 * (Too) optimistically allow split if there are more
459 * then one segments left.
461 gas_flags = map->cansleep ? DMAR_GM_CANWAIT : 0;
462 if (seg + 1 < tag->common.nsegments)
463 gas_flags |= DMAR_GM_CANSPLIT;
465 error = dmar_gas_map(ctx, &tag->common, size,
466 DMAR_MAP_ENTRY_READ | DMAR_MAP_ENTRY_WRITE,
467 gas_flags, ma + idx, &entry);
470 if ((gas_flags & DMAR_GM_CANSPLIT) != 0) {
471 KASSERT(size >= entry->end - entry->start,
472 ("split increased entry size %jx %jx %jx",
473 (uintmax_t)size, (uintmax_t)entry->start,
474 (uintmax_t)entry->end));
475 size = entry->end - entry->start;
479 KASSERT(entry->end - entry->start == size,
480 ("no split allowed %jx %jx %jx",
481 (uintmax_t)size, (uintmax_t)entry->start,
482 (uintmax_t)entry->end));
485 KASSERT(((entry->start + offset) & (tag->common.alignment - 1))
487 ("alignment failed: ctx %p start 0x%jx offset %x "
488 "align 0x%jx", ctx, (uintmax_t)entry->start, offset,
489 (uintmax_t)tag->common.alignment));
490 KASSERT(entry->end <= tag->common.lowaddr ||
491 entry->start >= tag->common.highaddr,
492 ("entry placement failed: ctx %p start 0x%jx end 0x%jx "
493 "lowaddr 0x%jx highaddr 0x%jx", ctx,
494 (uintmax_t)entry->start, (uintmax_t)entry->end,
495 (uintmax_t)tag->common.lowaddr,
496 (uintmax_t)tag->common.highaddr));
497 KASSERT(dmar_test_boundary(entry->start, entry->end -
498 entry->start, tag->common.boundary),
499 ("boundary failed: ctx %p start 0x%jx end 0x%jx "
500 "boundary 0x%jx", ctx, (uintmax_t)entry->start,
501 (uintmax_t)entry->end, (uintmax_t)tag->common.boundary));
502 KASSERT(buflen1 <= tag->common.maxsegsz,
503 ("segment too large: ctx %p start 0x%jx end 0x%jx "
504 "maxsegsz 0x%jx", ctx, (uintmax_t)entry->start,
505 (uintmax_t)entry->end, (uintmax_t)tag->common.maxsegsz));
508 TAILQ_INSERT_TAIL(&map->map_entries, entry, dmamap_link);
509 entry->flags |= DMAR_MAP_ENTRY_MAP;
510 DMAR_CTX_UNLOCK(ctx);
511 TAILQ_INSERT_TAIL(unroll_list, entry, unroll_link);
513 segs[seg].ds_addr = entry->start + offset;
514 segs[seg].ds_len = buflen1;
516 idx += OFF_TO_IDX(trunc_page(offset + buflen1));
518 offset &= DMAR_PAGE_MASK;
526 dmar_bus_dmamap_load_something(struct bus_dma_tag_dmar *tag,
527 struct bus_dmamap_dmar *map, vm_page_t *ma, int offset, bus_size_t buflen,
528 int flags, bus_dma_segment_t *segs, int *segp)
530 struct dmar_ctx *ctx;
531 struct dmar_map_entry *entry, *entry1;
532 struct dmar_map_entries_tailq unroll_list;
536 atomic_add_long(&ctx->loads, 1);
538 TAILQ_INIT(&unroll_list);
539 error = dmar_bus_dmamap_load_something1(tag, map, ma, offset,
540 buflen, flags, segs, segp, &unroll_list);
543 * The busdma interface does not allow us to report
544 * partial buffer load, so unfortunately we have to
545 * revert all work done.
548 TAILQ_FOREACH_SAFE(entry, &unroll_list, unroll_link,
551 * No entries other than what we have created
552 * during the failed run might have been
553 * inserted there in between, since we own ctx
556 TAILQ_REMOVE(&map->map_entries, entry, dmamap_link);
557 TAILQ_REMOVE(&unroll_list, entry, unroll_link);
558 TAILQ_INSERT_TAIL(&ctx->unload_entries, entry,
561 DMAR_CTX_UNLOCK(ctx);
562 taskqueue_enqueue(ctx->dmar->delayed_taskqueue,
566 if (error == ENOMEM && (flags & BUS_DMA_NOWAIT) == 0 &&
569 if (error == EINPROGRESS)
570 dmar_bus_schedule_dmamap(ctx->dmar, map);
575 dmar_bus_dmamap_load_ma(bus_dma_tag_t dmat, bus_dmamap_t map1,
576 struct vm_page **ma, bus_size_t tlen, int ma_offs, int flags,
577 bus_dma_segment_t *segs, int *segp)
579 struct bus_dma_tag_dmar *tag;
580 struct bus_dmamap_dmar *map;
582 tag = (struct bus_dma_tag_dmar *)dmat;
583 map = (struct bus_dmamap_dmar *)map1;
584 return (dmar_bus_dmamap_load_something(tag, map, ma, ma_offs, tlen,
589 dmar_bus_dmamap_load_phys(bus_dma_tag_t dmat, bus_dmamap_t map1,
590 vm_paddr_t buf, bus_size_t buflen, int flags, bus_dma_segment_t *segs,
593 struct bus_dma_tag_dmar *tag;
594 struct bus_dmamap_dmar *map;
596 vm_paddr_t pstart, pend;
597 int error, i, ma_cnt, offset;
599 tag = (struct bus_dma_tag_dmar *)dmat;
600 map = (struct bus_dmamap_dmar *)map1;
601 pstart = trunc_page(buf);
602 pend = round_page(buf + buflen);
603 offset = buf & PAGE_MASK;
604 ma_cnt = OFF_TO_IDX(pend - pstart);
605 ma = malloc(sizeof(vm_page_t) * ma_cnt, M_DEVBUF, map->cansleep ?
606 M_WAITOK : M_NOWAIT);
609 for (i = 0; i < ma_cnt; i++)
610 ma[i] = PHYS_TO_VM_PAGE(pstart + i * PAGE_SIZE);
611 error = dmar_bus_dmamap_load_something(tag, map, ma, offset, buflen,
618 dmar_bus_dmamap_load_buffer(bus_dma_tag_t dmat, bus_dmamap_t map1, void *buf,
619 bus_size_t buflen, pmap_t pmap, int flags, bus_dma_segment_t *segs,
622 struct bus_dma_tag_dmar *tag;
623 struct bus_dmamap_dmar *map;
625 vm_paddr_t pstart, pend, paddr;
626 int error, i, ma_cnt, offset;
628 tag = (struct bus_dma_tag_dmar *)dmat;
629 map = (struct bus_dmamap_dmar *)map1;
630 pstart = trunc_page((vm_offset_t)buf);
631 pend = round_page((vm_offset_t)buf + buflen);
632 offset = (vm_offset_t)buf & PAGE_MASK;
633 ma_cnt = OFF_TO_IDX(pend - pstart);
634 ma = malloc(sizeof(vm_page_t) * ma_cnt, M_DEVBUF, map->cansleep ?
635 M_WAITOK : M_NOWAIT);
640 * If dumping, do not attempt to call
641 * PHYS_TO_VM_PAGE() at all. It may return non-NULL
642 * but the vm_page returned might be not initialized,
643 * e.g. for the kernel itself.
645 KASSERT(pmap == kernel_pmap, ("non-kernel address write"));
646 fma = malloc(sizeof(struct vm_page) * ma_cnt, M_DEVBUF,
647 M_ZERO | (map->cansleep ? M_WAITOK : M_NOWAIT));
652 for (i = 0; i < ma_cnt; i++, pstart += PAGE_SIZE) {
653 paddr = pmap_kextract(pstart);
654 vm_page_initfake(&fma[i], paddr, VM_MEMATTR_DEFAULT);
659 for (i = 0; i < ma_cnt; i++, pstart += PAGE_SIZE) {
660 if (pmap == kernel_pmap)
661 paddr = pmap_kextract(pstart);
663 paddr = pmap_extract(pmap, pstart);
664 ma[i] = PHYS_TO_VM_PAGE(paddr);
665 KASSERT(VM_PAGE_TO_PHYS(ma[i]) == paddr,
666 ("PHYS_TO_VM_PAGE failed %jx %jx m %p",
667 (uintmax_t)paddr, (uintmax_t)VM_PAGE_TO_PHYS(ma[i]),
671 error = dmar_bus_dmamap_load_something(tag, map, ma, offset, buflen,
679 dmar_bus_dmamap_waitok(bus_dma_tag_t dmat, bus_dmamap_t map1,
680 struct memdesc *mem, bus_dmamap_callback_t *callback, void *callback_arg)
682 struct bus_dmamap_dmar *map;
686 map = (struct bus_dmamap_dmar *)map1;
688 map->tag = (struct bus_dma_tag_dmar *)dmat;
689 map->callback = callback;
690 map->callback_arg = callback_arg;
693 static bus_dma_segment_t *
694 dmar_bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map1,
695 bus_dma_segment_t *segs, int nsegs, int error)
697 struct bus_dma_tag_dmar *tag;
698 struct bus_dmamap_dmar *map;
700 tag = (struct bus_dma_tag_dmar *)dmat;
701 map = (struct bus_dmamap_dmar *)map1;
704 KASSERT(map->cansleep,
705 ("map not locked and not sleepable context %p", map));
708 * We are called from the delayed context. Relock the
711 (tag->common.lockfunc)(tag->common.lockfuncarg, BUS_DMA_LOCK);
716 segs = tag->segments;
721 * The limitations of busdma KPI forces the dmar to perform the actual
722 * unload, consisting of the unmapping of the map entries page tables,
723 * from the delayed context on i386, since page table page mapping
724 * might require a sleep to be successfull. The unfortunate
725 * consequence is that the DMA requests can be served some time after
726 * the bus_dmamap_unload() call returned.
728 * On amd64, we assume that sf allocation cannot fail.
731 dmar_bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map1)
733 struct bus_dma_tag_dmar *tag;
734 struct bus_dmamap_dmar *map;
735 struct dmar_ctx *ctx;
736 #if defined(__amd64__)
737 struct dmar_map_entries_tailq entries;
740 tag = (struct bus_dma_tag_dmar *)dmat;
741 map = (struct bus_dmamap_dmar *)map1;
743 atomic_add_long(&ctx->unloads, 1);
745 #if defined(__i386__)
747 TAILQ_CONCAT(&ctx->unload_entries, &map->map_entries, dmamap_link);
748 DMAR_CTX_UNLOCK(ctx);
749 taskqueue_enqueue(ctx->dmar->delayed_taskqueue, &ctx->unload_task);
750 #else /* defined(__amd64__) */
751 TAILQ_INIT(&entries);
753 TAILQ_CONCAT(&entries, &map->map_entries, dmamap_link);
754 DMAR_CTX_UNLOCK(ctx);
755 THREAD_NO_SLEEPING();
756 dmar_ctx_unload(ctx, &entries, false);
757 THREAD_SLEEPING_OK();
758 KASSERT(TAILQ_EMPTY(&entries), ("lazy dmar_ctx_unload %p", ctx));
763 dmar_bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map,
768 struct bus_dma_impl bus_dma_dmar_impl = {
769 .tag_create = dmar_bus_dma_tag_create,
770 .tag_destroy = dmar_bus_dma_tag_destroy,
771 .map_create = dmar_bus_dmamap_create,
772 .map_destroy = dmar_bus_dmamap_destroy,
773 .mem_alloc = dmar_bus_dmamem_alloc,
774 .mem_free = dmar_bus_dmamem_free,
775 .load_phys = dmar_bus_dmamap_load_phys,
776 .load_buffer = dmar_bus_dmamap_load_buffer,
777 .load_ma = dmar_bus_dmamap_load_ma,
778 .map_waitok = dmar_bus_dmamap_waitok,
779 .map_complete = dmar_bus_dmamap_complete,
780 .map_unload = dmar_bus_dmamap_unload,
781 .map_sync = dmar_bus_dmamap_sync
785 dmar_bus_task_dmamap(void *arg, int pending)
787 struct bus_dma_tag_dmar *tag;
788 struct bus_dmamap_dmar *map;
789 struct dmar_unit *unit;
790 struct dmar_ctx *ctx;
794 while ((map = TAILQ_FIRST(&unit->delayed_maps)) != NULL) {
795 TAILQ_REMOVE(&unit->delayed_maps, map, delay_link);
799 map->cansleep = true;
801 bus_dmamap_load_mem((bus_dma_tag_t)tag, (bus_dmamap_t)map,
802 &map->mem, map->callback, map->callback_arg,
804 map->cansleep = false;
806 (tag->common.lockfunc)(tag->common.lockfuncarg,
810 map->cansleep = false;
817 dmar_bus_schedule_dmamap(struct dmar_unit *unit, struct bus_dmamap_dmar *map)
819 struct dmar_ctx *ctx;
824 TAILQ_INSERT_TAIL(&unit->delayed_maps, map, delay_link);
826 taskqueue_enqueue(unit->delayed_taskqueue, &unit->dmamap_load_task);
830 dmar_init_busdma(struct dmar_unit *unit)
833 TAILQ_INIT(&unit->delayed_maps);
834 TASK_INIT(&unit->dmamap_load_task, 0, dmar_bus_task_dmamap, unit);
835 unit->delayed_taskqueue = taskqueue_create("dmar", M_WAITOK,
836 taskqueue_thread_enqueue, &unit->delayed_taskqueue);
837 taskqueue_start_threads(&unit->delayed_taskqueue, 1, PI_DISK,
838 "dmar%d busdma taskq", unit->unit);
843 dmar_fini_busdma(struct dmar_unit *unit)
846 if (unit->delayed_taskqueue == NULL)
849 taskqueue_drain(unit->delayed_taskqueue, &unit->dmamap_load_task);
850 taskqueue_free(unit->delayed_taskqueue);
851 unit->delayed_taskqueue = NULL;