2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 The FreeBSD Foundation
7 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
8 * under sponsorship from the FreeBSD Foundation.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
39 #include <sys/interrupt.h>
40 #include <sys/kernel.h>
42 #include <sys/limits.h>
44 #include <sys/memdesc.h>
45 #include <sys/mutex.h>
47 #include <sys/rwlock.h>
49 #include <sys/sysctl.h>
50 #include <sys/taskqueue.h>
55 #include <vm/vm_extern.h>
56 #include <vm/vm_kern.h>
57 #include <vm/vm_object.h>
58 #include <vm/vm_page.h>
59 #include <vm/vm_pager.h>
60 #include <vm/vm_map.h>
61 #include <contrib/dev/acpica/include/acpi.h>
62 #include <contrib/dev/acpica/include/accommon.h>
63 #include <dev/pci/pcireg.h>
64 #include <dev/pci/pcivar.h>
65 #include <machine/atomic.h>
66 #include <machine/bus.h>
67 #include <machine/md_var.h>
68 #include <machine/specialreg.h>
69 #include <x86/include/busdma_impl.h>
70 #include <dev/iommu/busdma_iommu.h>
71 #include <x86/iommu/intel_reg.h>
72 #include <x86/iommu/intel_dmar.h>
74 static MALLOC_DEFINE(M_DMAR_CTX, "dmar_ctx", "Intel DMAR Context");
75 static MALLOC_DEFINE(M_DMAR_DOMAIN, "dmar_dom", "Intel DMAR Domain");
77 static void dmar_domain_unload_task(void *arg, int pending);
78 static void dmar_unref_domain_locked(struct dmar_unit *dmar,
79 struct dmar_domain *domain);
80 static void dmar_domain_destroy(struct dmar_domain *domain);
83 dmar_ensure_ctx_page(struct dmar_unit *dmar, int bus)
86 dmar_root_entry_t *re;
90 * Allocated context page must be linked.
92 ctxm = dmar_pgalloc(dmar->ctx_obj, 1 + bus, IOMMU_PGF_NOALLOC);
97 * Page not present, allocate and link. Note that other
98 * thread might execute this sequence in parallel. This
99 * should be safe, because the context entries written by both
102 TD_PREP_PINNED_ASSERT;
103 ctxm = dmar_pgalloc(dmar->ctx_obj, 1 + bus, IOMMU_PGF_ZERO |
105 re = dmar_map_pgtbl(dmar->ctx_obj, 0, IOMMU_PGF_NOALLOC, &sf);
107 dmar_pte_store(&re->r1, DMAR_ROOT_R1_P | (DMAR_ROOT_R1_CTP_MASK &
108 VM_PAGE_TO_PHYS(ctxm)));
109 dmar_flush_root_to_ram(dmar, re);
110 dmar_unmap_pgtbl(sf);
114 static dmar_ctx_entry_t *
115 dmar_map_ctx_entry(struct dmar_ctx *ctx, struct sf_buf **sfp)
117 struct dmar_unit *dmar;
118 dmar_ctx_entry_t *ctxp;
120 dmar = CTX2DMAR(ctx);
122 ctxp = dmar_map_pgtbl(dmar->ctx_obj, 1 +
123 PCI_RID2BUS(ctx->rid), IOMMU_PGF_NOALLOC | IOMMU_PGF_WAITOK, sfp);
124 ctxp += ctx->rid & 0xff;
129 device_tag_init(struct dmar_ctx *ctx, device_t dev)
131 struct dmar_domain *domain;
134 domain = CTX2DOM(ctx);
135 maxaddr = MIN(domain->iodom.end, BUS_SPACE_MAXADDR);
136 ctx->context.tag->common.ref_count = 1; /* Prevent free */
137 ctx->context.tag->common.impl = &bus_dma_iommu_impl;
138 ctx->context.tag->common.boundary = 0;
139 ctx->context.tag->common.lowaddr = maxaddr;
140 ctx->context.tag->common.highaddr = maxaddr;
141 ctx->context.tag->common.maxsize = maxaddr;
142 ctx->context.tag->common.nsegments = BUS_SPACE_UNRESTRICTED;
143 ctx->context.tag->common.maxsegsz = maxaddr;
144 ctx->context.tag->ctx = CTX2IOCTX(ctx);
145 ctx->context.tag->owner = dev;
149 ctx_id_entry_init_one(dmar_ctx_entry_t *ctxp, struct dmar_domain *domain,
153 * For update due to move, the store is not atomic. It is
154 * possible that DMAR read upper doubleword, while low
155 * doubleword is not yet updated. The domain id is stored in
156 * the upper doubleword, while the table pointer in the lower.
158 * There is no good solution, for the same reason it is wrong
159 * to clear P bit in the ctx entry for update.
161 dmar_pte_store1(&ctxp->ctx2, DMAR_CTX2_DID(domain->domain) |
163 if (ctx_root == NULL) {
164 dmar_pte_store1(&ctxp->ctx1, DMAR_CTX1_T_PASS | DMAR_CTX1_P);
166 dmar_pte_store1(&ctxp->ctx1, DMAR_CTX1_T_UNTR |
167 (DMAR_CTX1_ASR_MASK & VM_PAGE_TO_PHYS(ctx_root)) |
173 ctx_id_entry_init(struct dmar_ctx *ctx, dmar_ctx_entry_t *ctxp, bool move,
176 struct dmar_unit *unit;
177 struct dmar_domain *domain;
181 domain = CTX2DOM(ctx);
182 unit = DOM2DMAR(domain);
183 KASSERT(move || (ctxp->ctx1 == 0 && ctxp->ctx2 == 0),
184 ("dmar%d: initialized ctx entry %d:%d:%d 0x%jx 0x%jx",
185 unit->iommu.unit, busno, pci_get_slot(ctx->context.tag->owner),
186 pci_get_function(ctx->context.tag->owner),
187 ctxp->ctx1, ctxp->ctx2));
189 if ((domain->iodom.flags & IOMMU_DOMAIN_IDMAP) != 0 &&
190 (unit->hw_ecap & DMAR_ECAP_PT) != 0) {
191 KASSERT(domain->pgtbl_obj == NULL,
192 ("ctx %p non-null pgtbl_obj", ctx));
195 ctx_root = dmar_pgalloc(domain->pgtbl_obj, 0,
199 if (iommu_is_buswide_ctx(DMAR2IOMMU(unit), busno)) {
201 for (i = 0; i <= PCI_BUSMAX; i++) {
202 ctx_id_entry_init_one(&ctxp[i], domain, ctx_root);
205 ctx_id_entry_init_one(ctxp, domain, ctx_root);
207 dmar_flush_ctx_to_ram(unit, ctxp);
211 dmar_flush_for_ctx_entry(struct dmar_unit *dmar, bool force)
216 * If dmar declares Caching Mode as Set, follow 11.5 "Caching
217 * Mode Consideration" and do the (global) invalidation of the
218 * negative TLB entries.
220 if ((dmar->hw_cap & DMAR_CAP_CM) == 0 && !force)
222 if (dmar->qi_enabled) {
223 dmar_qi_invalidate_ctx_glob_locked(dmar);
224 if ((dmar->hw_ecap & DMAR_ECAP_DI) != 0 || force)
225 dmar_qi_invalidate_iotlb_glob_locked(dmar);
228 error = dmar_inv_ctx_glob(dmar);
229 if (error == 0 && ((dmar->hw_ecap & DMAR_ECAP_DI) != 0 || force))
230 error = dmar_inv_iotlb_glob(dmar);
235 domain_init_rmrr(struct dmar_domain *domain, device_t dev, int bus,
236 int slot, int func, int dev_domain, int dev_busno,
237 const void *dev_path, int dev_path_len)
239 struct iommu_map_entries_tailq rmrr_entries;
240 struct iommu_map_entry *entry, *entry1;
242 iommu_gaddr_t start, end;
247 TAILQ_INIT(&rmrr_entries);
248 dmar_dev_parse_rmrr(domain, dev_domain, dev_busno, dev_path,
249 dev_path_len, &rmrr_entries);
250 TAILQ_FOREACH_SAFE(entry, &rmrr_entries, unroll_link, entry1) {
252 * VT-d specification requires that the start of an
253 * RMRR entry is 4k-aligned. Buggy BIOSes put
254 * anything into the start and end fields. Truncate
255 * and round as neccesary.
257 * We also allow the overlapping RMRR entries, see
258 * iommu_gas_alloc_region().
260 start = entry->start;
263 printf("dmar%d ctx pci%d:%d:%d RMRR [%#jx, %#jx]\n",
264 domain->iodom.iommu->unit, bus, slot, func,
265 (uintmax_t)start, (uintmax_t)end);
266 entry->start = trunc_page(start);
267 entry->end = round_page(end);
268 if (entry->start == entry->end) {
269 /* Workaround for some AMI (?) BIOSes */
272 device_printf(dev, "");
273 printf("pci%d:%d:%d ", bus, slot, func);
274 printf("BIOS bug: dmar%d RMRR "
275 "region (%jx, %jx) corrected\n",
276 domain->iodom.iommu->unit, start, end);
278 entry->end += DMAR_PAGE_SIZE * 0x20;
280 size = OFF_TO_IDX(entry->end - entry->start);
281 ma = malloc(sizeof(vm_page_t) * size, M_TEMP, M_WAITOK);
282 for (i = 0; i < size; i++) {
283 ma[i] = vm_page_getfake(entry->start + PAGE_SIZE * i,
286 error1 = iommu_gas_map_region(DOM2IODOM(domain), entry,
287 IOMMU_MAP_ENTRY_READ | IOMMU_MAP_ENTRY_WRITE,
288 IOMMU_MF_CANWAIT | IOMMU_MF_RMRR, ma);
290 * Non-failed RMRR entries are owned by context rb
291 * tree. Get rid of the failed entry, but do not stop
292 * the loop. Rest of the parsed RMRR entries are
293 * loaded and removed on the context destruction.
295 if (error1 == 0 && entry->end != entry->start) {
296 IOMMU_LOCK(domain->iodom.iommu);
297 domain->refs++; /* XXXKIB prevent free */
298 domain->iodom.flags |= IOMMU_DOMAIN_RMRR;
299 IOMMU_UNLOCK(domain->iodom.iommu);
303 device_printf(dev, "");
304 printf("pci%d:%d:%d ", bus, slot, func);
306 "dmar%d failed to map RMRR region (%jx, %jx) %d\n",
307 domain->iodom.iommu->unit, start, end,
311 TAILQ_REMOVE(&rmrr_entries, entry, unroll_link);
312 iommu_gas_free_entry(DOM2IODOM(domain), entry);
314 for (i = 0; i < size; i++)
315 vm_page_putfake(ma[i]);
321 static struct dmar_domain *
322 dmar_domain_alloc(struct dmar_unit *dmar, bool id_mapped)
324 struct iommu_domain *iodom;
325 struct dmar_domain *domain;
328 id = alloc_unr(dmar->domids);
331 domain = malloc(sizeof(*domain), M_DMAR_DOMAIN, M_WAITOK | M_ZERO);
332 iodom = DOM2IODOM(domain);
334 LIST_INIT(&domain->contexts);
335 RB_INIT(&domain->iodom.rb_root);
336 TAILQ_INIT(&domain->iodom.unload_entries);
337 TASK_INIT(&domain->iodom.unload_task, 0, dmar_domain_unload_task,
339 mtx_init(&domain->iodom.lock, "dmardom", NULL, MTX_DEF);
341 domain->iodom.iommu = &dmar->iommu;
342 domain_pgtbl_init(domain);
345 * For now, use the maximal usable physical address of the
346 * installed memory to calculate the mgaw on id_mapped domain.
347 * It is useful for the identity mapping, and less so for the
348 * virtualized bus address space.
350 domain->iodom.end = id_mapped ? ptoa(Maxmem) : BUS_SPACE_MAXADDR;
351 mgaw = dmar_maxaddr2mgaw(dmar, domain->iodom.end, !id_mapped);
352 error = domain_set_agaw(domain, mgaw);
356 /* Use all supported address space for remapping. */
357 domain->iodom.end = 1ULL << (domain->agaw - 1);
359 iommu_gas_init_domain(DOM2IODOM(domain));
362 if ((dmar->hw_ecap & DMAR_ECAP_PT) == 0) {
363 domain->pgtbl_obj = domain_get_idmap_pgtbl(domain,
366 domain->iodom.flags |= IOMMU_DOMAIN_IDMAP;
368 error = domain_alloc_pgtbl(domain);
371 /* Disable local apic region access */
372 error = iommu_gas_reserve_region(iodom, 0xfee00000,
380 dmar_domain_destroy(domain);
384 static struct dmar_ctx *
385 dmar_ctx_alloc(struct dmar_domain *domain, uint16_t rid)
387 struct dmar_ctx *ctx;
389 ctx = malloc(sizeof(*ctx), M_DMAR_CTX, M_WAITOK | M_ZERO);
390 ctx->context.domain = DOM2IODOM(domain);
391 ctx->context.tag = malloc(sizeof(struct bus_dma_tag_iommu),
392 M_DMAR_CTX, M_WAITOK | M_ZERO);
399 dmar_ctx_link(struct dmar_ctx *ctx)
401 struct dmar_domain *domain;
403 domain = CTX2DOM(ctx);
404 IOMMU_ASSERT_LOCKED(domain->iodom.iommu);
405 KASSERT(domain->refs >= domain->ctx_cnt,
406 ("dom %p ref underflow %d %d", domain, domain->refs,
410 LIST_INSERT_HEAD(&domain->contexts, ctx, link);
414 dmar_ctx_unlink(struct dmar_ctx *ctx)
416 struct dmar_domain *domain;
418 domain = CTX2DOM(ctx);
419 IOMMU_ASSERT_LOCKED(domain->iodom.iommu);
420 KASSERT(domain->refs > 0,
421 ("domain %p ctx dtr refs %d", domain, domain->refs));
422 KASSERT(domain->ctx_cnt >= domain->refs,
423 ("domain %p ctx dtr refs %d ctx_cnt %d", domain,
424 domain->refs, domain->ctx_cnt));
427 LIST_REMOVE(ctx, link);
431 dmar_domain_destroy(struct dmar_domain *domain)
433 struct dmar_unit *dmar;
435 KASSERT(TAILQ_EMPTY(&domain->iodom.unload_entries),
436 ("unfinished unloads %p", domain));
437 KASSERT(LIST_EMPTY(&domain->contexts),
438 ("destroying dom %p with contexts", domain));
439 KASSERT(domain->ctx_cnt == 0,
440 ("destroying dom %p with ctx_cnt %d", domain, domain->ctx_cnt));
441 KASSERT(domain->refs == 0,
442 ("destroying dom %p with refs %d", domain, domain->refs));
443 if ((domain->iodom.flags & IOMMU_DOMAIN_GAS_INITED) != 0) {
444 DMAR_DOMAIN_LOCK(domain);
445 iommu_gas_fini_domain(DOM2IODOM(domain));
446 DMAR_DOMAIN_UNLOCK(domain);
448 if ((domain->iodom.flags & IOMMU_DOMAIN_PGTBL_INITED) != 0) {
449 if (domain->pgtbl_obj != NULL)
450 DMAR_DOMAIN_PGLOCK(domain);
451 domain_free_pgtbl(domain);
453 mtx_destroy(&domain->iodom.lock);
454 dmar = DOM2DMAR(domain);
455 free_unr(dmar->domids, domain->domain);
456 free(domain, M_DMAR_DOMAIN);
459 static struct dmar_ctx *
460 dmar_get_ctx_for_dev1(struct dmar_unit *dmar, device_t dev, uint16_t rid,
461 int dev_domain, int dev_busno, const void *dev_path, int dev_path_len,
462 bool id_mapped, bool rmrr_init)
464 struct dmar_domain *domain, *domain1;
465 struct dmar_ctx *ctx, *ctx1;
466 struct iommu_unit *unit;
467 dmar_ctx_entry_t *ctxp;
469 int bus, slot, func, error;
473 bus = pci_get_bus(dev);
474 slot = pci_get_slot(dev);
475 func = pci_get_function(dev);
477 bus = PCI_RID2BUS(rid);
478 slot = PCI_RID2SLOT(rid);
479 func = PCI_RID2FUNC(rid);
482 TD_PREP_PINNED_ASSERT;
483 unit = DMAR2IOMMU(dmar);
485 KASSERT(!iommu_is_buswide_ctx(unit, bus) || (slot == 0 && func == 0),
486 ("iommu%d pci%d:%d:%d get_ctx for buswide", dmar->iommu.unit, bus,
488 ctx = dmar_find_ctx_locked(dmar, rid);
492 * Perform the allocations which require sleep or have
493 * higher chance to succeed if the sleep is allowed.
496 dmar_ensure_ctx_page(dmar, PCI_RID2BUS(rid));
497 domain1 = dmar_domain_alloc(dmar, id_mapped);
498 if (domain1 == NULL) {
503 error = domain_init_rmrr(domain1, dev, bus,
504 slot, func, dev_domain, dev_busno, dev_path,
507 dmar_domain_destroy(domain1);
512 ctx1 = dmar_ctx_alloc(domain1, rid);
513 ctxp = dmar_map_ctx_entry(ctx1, &sf);
517 * Recheck the contexts, other thread might have
518 * already allocated needed one.
520 ctx = dmar_find_ctx_locked(dmar, rid);
525 ctx->context.tag->owner = dev;
526 device_tag_init(ctx, dev);
529 * This is the first activated context for the
530 * DMAR unit. Enable the translation after
531 * everything is set up.
533 if (LIST_EMPTY(&dmar->domains))
535 LIST_INSERT_HEAD(&dmar->domains, domain, link);
536 ctx_id_entry_init(ctx, ctxp, false, bus);
539 "dmar%d pci%d:%d:%d:%d rid %x domain %d mgaw %d "
540 "agaw %d %s-mapped\n",
541 dmar->iommu.unit, dmar->segment, bus, slot,
542 func, rid, domain->domain, domain->mgaw,
543 domain->agaw, id_mapped ? "id" : "re");
545 dmar_unmap_pgtbl(sf);
547 dmar_unmap_pgtbl(sf);
548 dmar_domain_destroy(domain1);
549 /* Nothing needs to be done to destroy ctx1. */
550 free(ctx1, M_DMAR_CTX);
551 domain = CTX2DOM(ctx);
552 ctx->refs++; /* tag referenced us */
555 domain = CTX2DOM(ctx);
556 if (ctx->context.tag->owner == NULL)
557 ctx->context.tag->owner = dev;
558 ctx->refs++; /* tag referenced us */
561 error = dmar_flush_for_ctx_entry(dmar, enable);
563 dmar_free_ctx_locked(dmar, ctx);
569 * The dmar lock was potentially dropped between check for the
570 * empty context list and now. Recheck the state of GCMD_TE
571 * to avoid unneeded command.
573 if (enable && !rmrr_init && (dmar->hw_gcmd & DMAR_GCMD_TE) == 0) {
574 error = dmar_enable_translation(dmar);
577 printf("dmar%d: enabled translation\n",
581 printf("dmar%d: enabling translation failed, "
582 "error %d\n", dmar->iommu.unit, error);
583 dmar_free_ctx_locked(dmar, ctx);
594 dmar_get_ctx_for_dev(struct dmar_unit *dmar, device_t dev, uint16_t rid,
595 bool id_mapped, bool rmrr_init)
597 int dev_domain, dev_path_len, dev_busno;
599 dev_domain = pci_get_domain(dev);
600 dev_path_len = dmar_dev_depth(dev);
601 ACPI_DMAR_PCI_PATH dev_path[dev_path_len];
602 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len);
603 return (dmar_get_ctx_for_dev1(dmar, dev, rid, dev_domain, dev_busno,
604 dev_path, dev_path_len, id_mapped, rmrr_init));
608 dmar_get_ctx_for_devpath(struct dmar_unit *dmar, uint16_t rid,
609 int dev_domain, int dev_busno,
610 const void *dev_path, int dev_path_len,
611 bool id_mapped, bool rmrr_init)
614 return (dmar_get_ctx_for_dev1(dmar, NULL, rid, dev_domain, dev_busno,
615 dev_path, dev_path_len, id_mapped, rmrr_init));
619 dmar_move_ctx_to_domain(struct dmar_domain *domain, struct dmar_ctx *ctx)
621 struct dmar_unit *dmar;
622 struct dmar_domain *old_domain;
623 dmar_ctx_entry_t *ctxp;
628 old_domain = CTX2DOM(ctx);
629 if (domain == old_domain)
631 KASSERT(old_domain->iodom.iommu == domain->iodom.iommu,
632 ("domain %p %u moving between dmars %u %u", domain,
633 domain->domain, old_domain->iodom.iommu->unit,
634 domain->iodom.iommu->unit));
635 TD_PREP_PINNED_ASSERT;
637 ctxp = dmar_map_ctx_entry(ctx, &sf);
639 dmar_ctx_unlink(ctx);
640 ctx->context.domain = &domain->iodom;
642 ctx_id_entry_init(ctx, ctxp, true, PCI_BUSMAX + 100);
643 dmar_unmap_pgtbl(sf);
644 error = dmar_flush_for_ctx_entry(dmar, true);
645 /* If flush failed, rolling back would not work as well. */
646 printf("dmar%d rid %x domain %d->%d %s-mapped\n",
647 dmar->iommu.unit, ctx->rid, old_domain->domain, domain->domain,
648 (domain->iodom.flags & IOMMU_DOMAIN_IDMAP) != 0 ? "id" : "re");
649 dmar_unref_domain_locked(dmar, old_domain);
655 dmar_unref_domain_locked(struct dmar_unit *dmar, struct dmar_domain *domain)
658 DMAR_ASSERT_LOCKED(dmar);
659 KASSERT(domain->refs >= 1,
660 ("dmar %d domain %p refs %u", dmar->iommu.unit, domain,
662 KASSERT(domain->refs > domain->ctx_cnt,
663 ("dmar %d domain %p refs %d ctx_cnt %d", dmar->iommu.unit, domain,
664 domain->refs, domain->ctx_cnt));
666 if (domain->refs > 1) {
672 KASSERT((domain->iodom.flags & IOMMU_DOMAIN_RMRR) == 0,
673 ("lost ref on RMRR domain %p", domain));
675 LIST_REMOVE(domain, link);
678 taskqueue_drain(dmar->iommu.delayed_taskqueue,
679 &domain->iodom.unload_task);
680 dmar_domain_destroy(domain);
684 dmar_free_ctx_locked(struct dmar_unit *dmar, struct dmar_ctx *ctx)
687 dmar_ctx_entry_t *ctxp;
688 struct dmar_domain *domain;
690 DMAR_ASSERT_LOCKED(dmar);
691 KASSERT(ctx->refs >= 1,
692 ("dmar %p ctx %p refs %u", dmar, ctx, ctx->refs));
695 * If our reference is not last, only the dereference should
704 KASSERT((ctx->context.flags & IOMMU_CTX_DISABLED) == 0,
705 ("lost ref on disabled ctx %p", ctx));
708 * Otherwise, the context entry must be cleared before the
709 * page table is destroyed. The mapping of the context
710 * entries page could require sleep, unlock the dmar.
713 TD_PREP_PINNED_ASSERT;
714 ctxp = dmar_map_ctx_entry(ctx, &sf);
716 KASSERT(ctx->refs >= 1,
717 ("dmar %p ctx %p refs %u", dmar, ctx, ctx->refs));
720 * Other thread might have referenced the context, in which
721 * case again only the dereference should be performed.
726 dmar_unmap_pgtbl(sf);
731 KASSERT((ctx->context.flags & IOMMU_CTX_DISABLED) == 0,
732 ("lost ref on disabled ctx %p", ctx));
735 * Clear the context pointer and flush the caches.
736 * XXXKIB: cannot do this if any RMRR entries are still present.
738 dmar_pte_clear(&ctxp->ctx1);
740 dmar_flush_ctx_to_ram(dmar, ctxp);
741 dmar_inv_ctx_glob(dmar);
742 if ((dmar->hw_ecap & DMAR_ECAP_DI) != 0) {
743 if (dmar->qi_enabled)
744 dmar_qi_invalidate_iotlb_glob_locked(dmar);
746 dmar_inv_iotlb_glob(dmar);
748 dmar_unmap_pgtbl(sf);
749 domain = CTX2DOM(ctx);
750 dmar_ctx_unlink(ctx);
751 free(ctx->context.tag, M_DMAR_CTX);
752 free(ctx, M_DMAR_CTX);
753 dmar_unref_domain_locked(dmar, domain);
758 dmar_free_ctx(struct dmar_ctx *ctx)
760 struct dmar_unit *dmar;
762 dmar = CTX2DMAR(ctx);
764 dmar_free_ctx_locked(dmar, ctx);
768 * Returns with the domain locked.
771 dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid)
773 struct dmar_domain *domain;
774 struct dmar_ctx *ctx;
776 DMAR_ASSERT_LOCKED(dmar);
778 LIST_FOREACH(domain, &dmar->domains, link) {
779 LIST_FOREACH(ctx, &domain->contexts, link) {
788 dmar_domain_free_entry(struct iommu_map_entry *entry, bool free)
790 struct iommu_domain *domain;
792 domain = entry->domain;
793 IOMMU_DOMAIN_LOCK(domain);
794 if ((entry->flags & IOMMU_MAP_ENTRY_RMRR) != 0)
795 iommu_gas_free_region(domain, entry);
797 iommu_gas_free_space(domain, entry);
798 IOMMU_DOMAIN_UNLOCK(domain);
800 iommu_gas_free_entry(domain, entry);
806 dmar_domain_unload_entry(struct iommu_map_entry *entry, bool free)
808 struct dmar_domain *domain;
809 struct dmar_unit *unit;
811 domain = IODOM2DOM(entry->domain);
812 unit = DOM2DMAR(domain);
813 if (unit->qi_enabled) {
815 dmar_qi_invalidate_locked(IODOM2DOM(entry->domain),
816 entry->start, entry->end - entry->start, &entry->gseq,
819 entry->flags |= IOMMU_MAP_ENTRY_QI_NF;
820 TAILQ_INSERT_TAIL(&unit->tlb_flush_entries, entry, dmamap_link);
823 domain_flush_iotlb_sync(IODOM2DOM(entry->domain),
824 entry->start, entry->end - entry->start);
825 dmar_domain_free_entry(entry, free);
830 dmar_domain_unload_emit_wait(struct dmar_domain *domain,
831 struct iommu_map_entry *entry)
834 if (TAILQ_NEXT(entry, dmamap_link) == NULL)
836 return (domain->batch_no++ % dmar_batch_coalesce == 0);
840 dmar_domain_unload(struct dmar_domain *domain,
841 struct iommu_map_entries_tailq *entries, bool cansleep)
843 struct dmar_unit *unit;
844 struct iommu_domain *iodom;
845 struct iommu_map_entry *entry, *entry1;
848 iodom = DOM2IODOM(domain);
849 unit = DOM2DMAR(domain);
851 TAILQ_FOREACH_SAFE(entry, entries, dmamap_link, entry1) {
852 KASSERT((entry->flags & IOMMU_MAP_ENTRY_MAP) != 0,
853 ("not mapped entry %p %p", domain, entry));
854 error = iodom->ops->unmap(iodom, entry->start, entry->end -
855 entry->start, cansleep ? IOMMU_PGF_WAITOK : 0);
856 KASSERT(error == 0, ("unmap %p error %d", domain, error));
857 if (!unit->qi_enabled) {
858 domain_flush_iotlb_sync(domain, entry->start,
859 entry->end - entry->start);
860 TAILQ_REMOVE(entries, entry, dmamap_link);
861 dmar_domain_free_entry(entry, true);
864 if (TAILQ_EMPTY(entries))
867 KASSERT(unit->qi_enabled, ("loaded entry left"));
869 TAILQ_FOREACH(entry, entries, dmamap_link) {
870 dmar_qi_invalidate_locked(domain, entry->start, entry->end -
871 entry->start, &entry->gseq,
872 dmar_domain_unload_emit_wait(domain, entry));
874 TAILQ_CONCAT(&unit->tlb_flush_entries, entries, dmamap_link);
879 dmar_domain_unload_task(void *arg, int pending)
881 struct dmar_domain *domain;
882 struct iommu_map_entries_tailq entries;
885 TAILQ_INIT(&entries);
888 DMAR_DOMAIN_LOCK(domain);
889 TAILQ_SWAP(&domain->iodom.unload_entries, &entries,
890 iommu_map_entry, dmamap_link);
891 DMAR_DOMAIN_UNLOCK(domain);
892 if (TAILQ_EMPTY(&entries))
894 dmar_domain_unload(domain, &entries, true);
899 iommu_get_ctx(struct iommu_unit *iommu, device_t dev, uint16_t rid,
900 bool id_mapped, bool rmrr_init)
902 struct dmar_unit *dmar;
903 struct dmar_ctx *ret;
905 dmar = IOMMU2DMAR(iommu);
907 ret = dmar_get_ctx_for_dev(dmar, dev, rid, id_mapped, rmrr_init);
909 return (CTX2IOCTX(ret));
913 iommu_free_ctx_locked(struct iommu_unit *iommu, struct iommu_ctx *context)
915 struct dmar_unit *dmar;
916 struct dmar_ctx *ctx;
918 dmar = IOMMU2DMAR(iommu);
919 ctx = IOCTX2CTX(context);
921 dmar_free_ctx_locked(dmar, ctx);
925 iommu_free_ctx(struct iommu_ctx *context)
927 struct dmar_ctx *ctx;
929 ctx = IOCTX2CTX(context);
935 iommu_domain_unload_entry(struct iommu_map_entry *entry, bool free)
938 dmar_domain_unload_entry(entry, free);
942 iommu_domain_unload(struct iommu_domain *iodom,
943 struct iommu_map_entries_tailq *entries, bool cansleep)
945 struct dmar_domain *domain;
947 domain = IODOM2DOM(iodom);
949 dmar_domain_unload(domain, entries, cansleep);